sv_addr.agh

linux-2.6.15.6

/*
!* This file was automatically generated by /n/asic/bin/reg_macro_gen
!* from the file `/n/asic/projects/etrax_ng/doc/work/etrax_ng_regs.rd'.
!* Editing within this file is thus not recommended,
!* make the changes in `/n/asic/projects/etrax_ng/doc/work/etrax_ng_regs.rd' instead.
!*/


/*
!* Bus interface configuration registers
!*/

#define R_WAITSTATES (IO_TYPECAST_UDWORD 0xb0000000)
#define R_WAITSTATES__pcs4_7_zw__BITNR 30
#define R_WAITSTATES__pcs4_7_zw__WIDTH 2
#define R_WAITSTATES__pcs4_7_ew__BITNR 28
#define R_WAITSTATES__pcs4_7_ew__WIDTH 2
#define R_WAITSTATES__pcs4_7_lw__BITNR 24
#define R_WAITSTATES__pcs4_7_lw__WIDTH 4
#define R_WAITSTATES__pcs0_3_zw__BITNR 22
#define R_WAITSTATES__pcs0_3_zw__WIDTH 2
#define R_WAITSTATES__pcs0_3_ew__BITNR 20
#define R_WAITSTATES__pcs0_3_ew__WIDTH 2
#define R_WAITSTATES__pcs0_3_lw__BITNR 16
#define R_WAITSTATES__pcs0_3_lw__WIDTH 4
#define R_WAITSTATES__sram_zw__BITNR 14
#define R_WAITSTATES__sram_zw__WIDTH 2
#define R_WAITSTATES__sram_ew__BITNR 12
#define R_WAITSTATES__sram_ew__WIDTH 2
#define R_WAITSTATES__sram_lw__BITNR 8
#define R_WAITSTATES__sram_lw__WIDTH 4
#define R_WAITSTATES__flash_zw__BITNR 6
#define R_WAITSTATES__flash_zw__WIDTH 2
#define R_WAITSTATES__flash_ew__BITNR 4
#define R_WAITSTATES__flash_ew__WIDTH 2
#define R_WAITSTATES__flash_lw__BITNR 0
#define R_WAITSTATES__flash_lw__WIDTH 4

#define R_BUS_CONFIG (IO_TYPECAST_UDWORD 0xb0000004)
#define R_BUS_CONFIG__sram_type__BITNR 9
#define R_BUS_CONFIG__sram_type__WIDTH 1
#define R_BUS_CONFIG__sram_type__cwe 1
#define R_BUS_CONFIG__sram_type__bwe 0
#define R_BUS_CONFIG__dma_burst__BITNR 8
#define R_BUS_CONFIG__dma_burst__WIDTH 1
#define R_BUS_CONFIG__dma_burst__burst16 1
#define R_BUS_CONFIG__dma_burst__burst32 0
#define R_BUS_CONFIG__pcs4_7_wr__BITNR 7
#define R_BUS_CONFIG__pcs4_7_wr__WIDTH 1
#define R_BUS_CONFIG__pcs4_7_wr__ext 1
#define R_BUS_CONFIG__pcs4_7_wr__norm 0
#define R_BUS_CONFIG__pcs0_3_wr__BITNR 6
#define R_BUS_CONFIG__pcs0_3_wr__WIDTH 1
#define R_BUS_CONFIG__pcs0_3_wr__ext 1
#define R_BUS_CONFIG__pcs0_3_wr__norm 0
#define R_BUS_CONFIG__sram_wr__BITNR 5
#define R_BUS_CONFIG__sram_wr__WIDTH 1
#define R_BUS_CONFIG__sram_wr__ext 1
#define R_BUS_CONFIG__sram_wr__norm 0
#define R_BUS_CONFIG__flash_wr__BITNR 4
#define R_BUS_CONFIG__flash_wr__WIDTH 1
#define R_BUS_CONFIG__flash_wr__ext 1
#define R_BUS_CONFIG__flash_wr__norm 0
#define R_BUS_CONFIG__pcs4_7_bw__BITNR 3
#define R_BUS_CONFIG__pcs4_7_bw__WIDTH 1
#define R_BUS_CONFIG__pcs4_7_bw__bw32 1
#define R_BUS_CONFIG__pcs4_7_bw__bw16 0
#define R_BUS_CONFIG__pcs0_3_bw__BITNR 2
#define R_BUS_CONFIG__pcs0_3_bw__WIDTH 1
#define R_BUS_CONFIG__pcs0_3_bw__bw32 1
#define R_BUS_CONFIG__pcs0_3_bw__bw16 0
#define R_BUS_CONFIG__sram_bw__BITNR 1
#define R_BUS_CONFIG__sram_bw__WIDTH 1
#define R_BUS_CONFIG__sram_bw__bw32 1
#define R_BUS_CONFIG__sram_bw__bw16 0
#define R_BUS_CONFIG__flash_bw__BITNR 0
#define R_BUS_CONFIG__flash_bw__WIDTH 1
#define R_BUS_CONFIG__flash_bw__bw32 1
#define R_BUS_CONFIG__flash_bw__bw16 0

#define R_BUS_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000004)
#define R_BUS_STATUS__pll_lock_tm__BITNR 5
#define R_BUS_STATUS__pll_lock_tm__WIDTH 1
#define R_BUS_STATUS__pll_lock_tm__expired 0
#define R_BUS_STATUS__pll_lock_tm__counting 1
#define R_BUS_STATUS__both_faults__BITNR 4
#define R_BUS_STATUS__both_faults__WIDTH 1
#define R_BUS_STATUS__both_faults__no 0
#define R_BUS_STATUS__both_faults__yes 1
#define R_BUS_STATUS__bsen___BITNR 3
#define R_BUS_STATUS__bsen___WIDTH 1
#define R_BUS_STATUS__bsen___enable 0
#define R_BUS_STATUS__bsen___disable 1
#define R_BUS_STATUS__boot__BITNR 1
#define R_BUS_STATUS__boot__WIDTH 2
#define R_BUS_STATUS__boot__uncached 0
#define R_BUS_STATUS__boot__serial 1
#define R_BUS_STATUS__boot__network 2
#define R_BUS_STATUS__boot__parallel 3
#define R_BUS_STATUS__flashw__BITNR 0
#define R_BUS_STATUS__flashw__WIDTH 1
#define R_BUS_STATUS__flashw__bw32 1
#define R_BUS_STATUS__flashw__bw16 0

#define R_DRAM_TIMING (IO_TYPECAST_UDWORD 0xb0000008)
#define R_DRAM_TIMING__sdram__BITNR 31
#define R_DRAM_TIMING__sdram__WIDTH 1
#define R_DRAM_TIMING__sdram__enable 1
#define R_DRAM_TIMING__sdram__disable 0
#define R_DRAM_TIMING__ref__BITNR 14
#define R_DRAM_TIMING__ref__WIDTH 2
#define R_DRAM_TIMING__ref__e52us 0
#define R_DRAM_TIMING__ref__e13us 1
#define R_DRAM_TIMING__ref__e8700ns 2
#define R_DRAM_TIMING__ref__disable 3
#define R_DRAM_TIMING__rp__BITNR 12
#define R_DRAM_TIMING__rp__WIDTH 2
#define R_DRAM_TIMING__rs__BITNR 10
#define R_DRAM_TIMING__rs__WIDTH 2
#define R_DRAM_TIMING__rh__BITNR 8
#define R_DRAM_TIMING__rh__WIDTH 2
#define R_DRAM_TIMING__w__BITNR 7
#define R_DRAM_TIMING__w__WIDTH 1
#define R_DRAM_TIMING__w__norm 0
#define R_DRAM_TIMING__w__ext 1
#define R_DRAM_TIMING__c__BITNR 6
#define R_DRAM_TIMING__c__WIDTH 1
#define R_DRAM_TIMING__c__norm 0
#define R_DRAM_TIMING__c__ext 1
#define R_DRAM_TIMING__cz__BITNR 4
#define R_DRAM_TIMING__cz__WIDTH 2
#define R_DRAM_TIMING__cp__BITNR 2
#define R_DRAM_TIMING__cp__WIDTH 2
#define R_DRAM_TIMING__cw__BITNR 0
#define R_DRAM_TIMING__cw__WIDTH 2

#define R_SDRAM_TIMING (IO_TYPECAST_UDWORD 0xb0000008)
#define R_SDRAM_TIMING__sdram__BITNR 31
#define R_SDRAM_TIMING__sdram__WIDTH 1
#define R_SDRAM_TIMING__sdram__enable 1
#define R_SDRAM_TIMING__sdram__disable 0
#define R_SDRAM_TIMING__mrs_data__BITNR 16
#define R_SDRAM_TIMING__mrs_data__WIDTH 15
#define R_SDRAM_TIMING__ref__BITNR 14
#define R_SDRAM_TIMING__ref__WIDTH 2
#define R_SDRAM_TIMING__ref__e52us 0
#define R_SDRAM_TIMING__ref__e13us 1
#define R_SDRAM_TIMING__ref__e6500ns 2
#define R_SDRAM_TIMING__ref__disable 3
#define R_SDRAM_TIMING__ddr__BITNR 13
#define R_SDRAM_TIMING__ddr__WIDTH 1
#define R_SDRAM_TIMING__ddr__on 1
#define R_SDRAM_TIMING__ddr__off 0
#define R_SDRAM_TIMING__clk100__BITNR 12
#define R_SDRAM_TIMING__clk100__WIDTH 1
#define R_SDRAM_TIMING__clk100__on 1
#define R_SDRAM_TIMING__clk100__off 0
#define R_SDRAM_TIMING__ps__BITNR 11
#define R_SDRAM_TIMING__ps__WIDTH 1
#define R_SDRAM_TIMING__ps__on 1
#define R_SDRAM_TIMING__ps__off 0
#define R_SDRAM_TIMING__cmd__BITNR 9
#define R_SDRAM_TIMING__cmd__WIDTH 2
#define R_SDRAM_TIMING__cmd__pre 3
#define R_SDRAM_TIMING__cmd__ref 2
#define R_SDRAM_TIMING__cmd__mrs 1
#define R_SDRAM_TIMING__cmd__nop 0
#define R_SDRAM_TIMING__pde__BITNR 8
#define R_SDRAM_TIMING__pde__WIDTH 1
#define R_SDRAM_TIMING__rc__BITNR 6
#define R_SDRAM_TIMING__rc__WIDTH 2
#define R_SDRAM_TIMING__rp__BITNR 4
#define R_SDRAM_TIMING__rp__WIDTH 2
#define R_SDRAM_TIMING__rcd__BITNR 2
#define R_SDRAM_TIMING__rcd__WIDTH 2
#define R_SDRAM_TIMING__cl__BITNR 0
#define R_SDRAM_TIMING__cl__WIDTH 2

#define R_DRAM_CONFIG (IO_TYPECAST_UDWORD 0xb000000c)
#define R_DRAM_CONFIG__wmm1__BITNR 31
#define R_DRAM_CONFIG__wmm1__WIDTH 1
#define R_DRAM_CONFIG__wmm1__wmm 1
#define R_DRAM_CONFIG__wmm1__norm 0
#define R_DRAM_CONFIG__wmm0__BITNR 30
#define R_DRAM_CONFIG__wmm0__WIDTH 1
#define R_DRAM_CONFIG__wmm0__wmm 1
#define R_DRAM_CONFIG__wmm0__norm 0
#define R_DRAM_CONFIG__sh1__BITNR 27
#define R_DRAM_CONFIG__sh1__WIDTH 3
#define R_DRAM_CONFIG__sh0__BITNR 24
#define R_DRAM_CONFIG__sh0__WIDTH 3
#define R_DRAM_CONFIG__w__BITNR 23
#define R_DRAM_CONFIG__w__WIDTH 1
#define R_DRAM_CONFIG__w__bw16 0
#define R_DRAM_CONFIG__w__bw32 1
#define R_DRAM_CONFIG__c__BITNR 22
#define R_DRAM_CONFIG__c__WIDTH 1
#define R_DRAM_CONFIG__c__byte 0
#define R_DRAM_CONFIG__c__bank 1
#define R_DRAM_CONFIG__e__BITNR 21
#define R_DRAM_CONFIG__e__WIDTH 1
#define R_DRAM_CONFIG__e__fast 0
#define R_DRAM_CONFIG__e__edo 1
#define R_DRAM_CONFIG__group_sel__BITNR 16
#define R_DRAM_CONFIG__group_sel__WIDTH 5
#define R_DRAM_CONFIG__group_sel__grp0 0
#define R_DRAM_CONFIG__group_sel__grp1 1
#define R_DRAM_CONFIG__group_sel__bit9 9
#define R_DRAM_CONFIG__group_sel__bit10 10
#define R_DRAM_CONFIG__group_sel__bit11 11
#define R_DRAM_CONFIG__group_sel__bit12 12
#define R_DRAM_CONFIG__group_sel__bit13 13
#define R_DRAM_CONFIG__group_sel__bit14 14
#define R_DRAM_CONFIG__group_sel__bit15 15
#define R_DRAM_CONFIG__group_sel__bit16 16
#define R_DRAM_CONFIG__group_sel__bit17 17
#define R_DRAM_CONFIG__group_sel__bit18 18
#define R_DRAM_CONFIG__group_sel__bit19 19
#define R_DRAM_CONFIG__group_sel__bit20 20
#define R_DRAM_CONFIG__group_sel__bit21 21
#define R_DRAM_CONFIG__group_sel__bit22 22
#define R_DRAM_CONFIG__group_sel__bit23 23
#define R_DRAM_CONFIG__group_sel__bit24 24
#define R_DRAM_CONFIG__group_sel__bit25 25
#define R_DRAM_CONFIG__group_sel__bit26 26
#define R_DRAM_CONFIG__group_sel__bit27 27
#define R_DRAM_CONFIG__group_sel__bit28 28
#define R_DRAM_CONFIG__group_sel__bit29 29
#define R_DRAM_CONFIG__ca1__BITNR 13
#define R_DRAM_CONFIG__ca1__WIDTH 3
#define R_DRAM_CONFIG__bank23sel__BITNR 8
#define R_DRAM_CONFIG__bank23sel__WIDTH 5
#define R_DRAM_CONFIG__bank23sel__bank0 0
#define R_DRAM_CONFIG__bank23sel__bank1 1
#define R_DRAM_CONFIG__bank23sel__bit9 9
#define R_DRAM_CONFIG__bank23sel__bit10 10
#define R_DRAM_CONFIG__bank23sel__bit11 11
#define R_DRAM_CONFIG__bank23sel__bit12 12
#define R_DRAM_CONFIG__bank23sel__bit13 13
#define R_DRAM_CONFIG__bank23sel__bit14 14
#define R_DRAM_CONFIG__bank23sel__bit15 15
#define R_DRAM_CONFIG__bank23sel__bit16 16
#define R_DRAM_CONFIG__bank23sel__bit17 17
#define R_DRAM_CONFIG__bank23sel__bit18 18
#define R_DRAM_CONFIG__bank23sel__bit19 19
#define R_DRAM_CONFIG__bank23sel__bit20 20
#define R_DRAM_CONFIG__bank23sel__bit21 21
#define R_DRAM_CONFIG__bank23sel__bit22 22
#define R_DRAM_CONFIG__bank23sel__bit23 23
#define R_DRAM_CONFIG__bank23sel__bit24 24
#define R_DRAM_CONFIG__bank23sel__bit25 25
#define R_DRAM_CONFIG__bank23sel__bit26 26
#define R_DRAM_CONFIG__bank23sel__bit27 27
#define R_DRAM_CONFIG__bank23sel__bit28 28
#define R_DRAM_CONFIG__bank23sel__bit29 29
#define R_DRAM_CONFIG__ca0__BITNR 5
#define R_DRAM_CONFIG__ca0__WIDTH 3
#define R_DRAM_CONFIG__bank01sel__BITNR 0
#define R_DRAM_CONFIG__bank01sel__WIDTH 5
#define R_DRAM_CONFIG__bank01sel__bank0 0
#define R_DRAM_CONFIG__bank01sel__bank1 1
#define R_DRAM_CONFIG__bank01sel__bit9 9
#define R_DRAM_CONFIG__bank01sel__bit10 10
#define R_DRAM_CONFIG__bank01sel__bit11 11
#define R_DRAM_CONFIG__bank01sel__bit12 12
#define R_DRAM_CONFIG__bank01sel__bit13 13
#define R_DRAM_CONFIG__bank01sel__bit14 14
#define R_DRAM_CONFIG__bank01sel__bit15 15
#define R_DRAM_CONFIG__bank01sel__bit16 16
#define R_DRAM_CONFIG__bank01sel__bit17 17
#define R_DRAM_CONFIG__bank01sel__bit18 18
#define R_DRAM_CONFIG__bank01sel__bit19 19
#define R_DRAM_CONFIG__bank01sel__bit20 20
#define R_DRAM_CONFIG__bank01sel__bit21 21
#define R_DRAM_CONFIG__bank01sel__bit22 22
#define R_DRAM_CONFIG__bank01sel__bit23 23
#define R_DRAM_CONFIG__bank01sel__bit24 24
#define R_DRAM_CONFIG__bank01sel__bit25 25
#define R_DRAM_CONFIG__bank01sel__bit26 26
#define R_DRAM_CONFIG__bank01sel__bit27 27
#define R_DRAM_CONFIG__bank01sel__bit28 28
#define R_DRAM_CONFIG__bank01sel__bit29 29

#define R_SDRAM_CONFIG (IO_TYPECAST_UDWORD 0xb000000c)
#define R_SDRAM_CONFIG__wmm1__BITNR 31
#define R_SDRAM_CONFIG__wmm1__WIDTH 1
#define R_SDRAM_CONFIG__wmm1__wmm 1
#define R_SDRAM_CONFIG__wmm1__norm 0
#define R_SDRAM_CONFIG__wmm0__BITNR 30
#define R_SDRAM_CONFIG__wmm0__WIDTH 1
#define R_SDRAM_CONFIG__wmm0__wmm 1
#define R_SDRAM_CONFIG__wmm0__norm 0
#define R_SDRAM_CONFIG__sh1__BITNR 27
#define R_SDRAM_CONFIG__sh1__WIDTH 3
#define R_SDRAM_CONFIG__sh0__BITNR 24
#define R_SDRAM_CONFIG__sh0__WIDTH 3
#define R_SDRAM_CONFIG__w__BITNR 23
#define R_SDRAM_CONFIG__w__WIDTH 1
#define R_SDRAM_CONFIG__w__bw16 0
#define R_SDRAM_CONFIG__w__bw32 1
#define R_SDRAM_CONFIG__type1__BITNR 22
#define R_SDRAM_CONFIG__type1__WIDTH 1
#define R_SDRAM_CONFIG__type1__bank2 0
#define R_SDRAM_CONFIG__type1__bank4 1
#define R_SDRAM_CONFIG__type0__BITNR 21
#define R_SDRAM_CONFIG__type0__WIDTH 1
#define R_SDRAM_CONFIG__type0__bank2 0
#define R_SDRAM_CONFIG__type0__bank4 1
#define R_SDRAM_CONFIG__group_sel__BITNR 16
#define R_SDRAM_CONFIG__group_sel__WIDTH 5
#define R_SDRAM_CONFIG__group_sel__grp0 0
#define R_SDRAM_CONFIG__group_sel__grp1 1
#define R_SDRAM_CONFIG__group_sel__bit9 9
#define R_SDRAM_CONFIG__group_sel__bit10 10
#define R_SDRAM_CONFIG__group_sel__bit11 11
#define R_SDRAM_CONFIG__group_sel__bit12 12
#define R_SDRAM_CONFIG__group_sel__bit13 13
#define R_SDRAM_CONFIG__group_sel__bit14 14
#define R_SDRAM_CONFIG__group_sel__bit15 15
#define R_SDRAM_CONFIG__group_sel__bit16 16
#define R_SDRAM_CONFIG__group_sel__bit17 17
#define R_SDRAM_CONFIG__group_sel__bit18 18
#define R_SDRAM_CONFIG__group_sel__bit19 19
#define R_SDRAM_CONFIG__group_sel__bit20 20
#define R_SDRAM_CONFIG__group_sel__bit21 21
#define R_SDRAM_CONFIG__group_sel__bit22 22
#define R_SDRAM_CONFIG__group_sel__bit23 23
#define R_SDRAM_CONFIG__group_sel__bit24 24
#define R_SDRAM_CONFIG__group_sel__bit25 25