tioce.h

linux-2.6.15.6

	uint64_t	ce_cxm_debug_mux;			/* 0x005050 */

        uint64_t        ce_pad_005058[501];         /* 0x005058 -- 0x005FF8 */

	/*
	 * DTL: Downstream Transaction Layer Regs (Link#1 and Link#2)
	 * DTL: Link#1 MMRs at start at 0x006000, Link#2 MMRs at 0x008000
	 * DTL: the comment offsets at far right: let 'y' = {6 or 8}
	 *
	 * UTL: Downstream Transaction Layer Regs (Link#1 and Link#2)
	 * UTL: Link#1 MMRs at start at 0x007000, Link#2 MMRs at 0x009000
	 * UTL: the comment offsets at far right: let 'z' = {7 or 9}
	 */
	#define ce_dtl(link_num)	ce_dtl_utl[link_num-1]
	#define ce_utl(link_num)	ce_dtl_utl[link_num-1]
	struct ce_dtl_utl_reg {
		/* DTL */
		uint64_t	ce_dtl_dtdr_credit_limit;	/* 0x00y000 */
		uint64_t	ce_dtl_dtdr_credit_force;	/* 0x00y008 */
		uint64_t	ce_dtl_dyn_credit_status;	/* 0x00y010 */
		uint64_t	ce_dtl_dtl_last_credit_stat;	/* 0x00y018 */
		uint64_t	ce_dtl_dtl_ctrl;		/* 0x00y020 */
		uint64_t	ce_pad_00y028[5];   /* 0x00y028 -- 0x00y048 */
		uint64_t	ce_dtl_debug_sel;		/* 0x00y050 */
		uint64_t	ce_pad_00y058[501]; /* 0x00y058 -- 0x00yFF8 */

		/* UTL */
		uint64_t	ce_utl_utl_ctrl;		/* 0x00z000 */
		uint64_t	ce_utl_debug_sel;		/* 0x00z008 */
		uint64_t	ce_pad_00z010[510]; /* 0x00z010 -- 0x00zFF8 */
	} ce_dtl_utl[2];

	uint64_t	ce_pad_00A000[514];	    /* 0x00A000 -- 0x00B008 */

	/*
	 * URE: Upstream Request Engine
         */
	uint64_t	ce_ure_dyn_credit_status;		/* 0x00B010 */
	uint64_t	ce_ure_last_credit_status;		/* 0x00B018 */
	uint64_t	ce_ure_credit_limit;			/* 0x00B020 */
	uint64_t	ce_pad_00B028;				/* 0x00B028 */
	uint64_t	ce_ure_control;				/* 0x00B030 */
	uint64_t	ce_ure_status;				/* 0x00B038 */
	uint64_t	ce_pad_00B040[2];	    /* 0x00B040 -- 0x00B048 */
	uint64_t	ce_ure_debug_sel;			/* 0x00B050 */
	uint64_t	ce_ure_pcie_debug_sel;			/* 0x00B058 */
	uint64_t	ce_ure_ssp_err_cmd_wrd;			/* 0x00B060 */
	uint64_t	ce_ure_ssp_err_addr;			/* 0x00B068 */
	uint64_t	ce_ure_page_map;			/* 0x00B070 */
	uint64_t	ce_ure_dir_map[TIOCE_NUM_PORTS];	/* 0x00B078 */
	uint64_t	ce_ure_pipe_sel1;			/* 0x00B088 */
	uint64_t	ce_ure_pipe_mask1;			/* 0x00B090 */
	uint64_t	ce_ure_pipe_sel2;			/* 0x00B098 */
	uint64_t	ce_ure_pipe_mask2;			/* 0x00B0A0 */
	uint64_t	ce_ure_pcie1_credits_sent;		/* 0x00B0A8 */
	uint64_t	ce_ure_pcie1_credits_used;		/* 0x00B0B0 */
	uint64_t	ce_ure_pcie1_credit_limit;		/* 0x00B0B8 */
	uint64_t	ce_ure_pcie2_credits_sent;		/* 0x00B0C0 */
	uint64_t	ce_ure_pcie2_credits_used;		/* 0x00B0C8 */
	uint64_t	ce_ure_pcie2_credit_limit;		/* 0x00B0D0 */
	uint64_t	ce_ure_pcie_force_credit;		/* 0x00B0D8 */
	uint64_t	ce_ure_rd_tnum_val;			/* 0x00B0E0 */
	uint64_t	ce_ure_rd_tnum_rsp_rcvd;		/* 0x00B0E8 */
	uint64_t	ce_ure_rd_tnum_esent_timer;		/* 0x00B0F0 */
	uint64_t	ce_ure_rd_tnum_error;			/* 0x00B0F8 */
	uint64_t	ce_ure_rd_tnum_first_cl;		/* 0x00B100 */
	uint64_t	ce_ure_rd_tnum_link_buf;		/* 0x00B108 */
	uint64_t	ce_ure_wr_tnum_val;			/* 0x00B110 */
	uint64_t	ce_ure_sram_err_addr0;			/* 0x00B118 */
	uint64_t	ce_ure_sram_err_addr1;			/* 0x00B120 */
	uint64_t	ce_ure_sram_err_addr2;			/* 0x00B128 */
	uint64_t	ce_ure_sram_rd_addr0;			/* 0x00B130 */
	uint64_t	ce_ure_sram_rd_addr1;			/* 0x00B138 */
	uint64_t	ce_ure_sram_rd_addr2;			/* 0x00B140 */
	uint64_t	ce_ure_sram_wr_addr0;			/* 0x00B148 */
	uint64_t	ce_ure_sram_wr_addr1;			/* 0x00B150 */
	uint64_t	ce_ure_sram_wr_addr2;			/* 0x00B158 */
	uint64_t	ce_ure_buf_flush10;			/* 0x00B160 */
	uint64_t	ce_ure_buf_flush11;			/* 0x00B168 */
	uint64_t	ce_ure_buf_flush12;			/* 0x00B170 */
	uint64_t	ce_ure_buf_flush13;			/* 0x00B178 */
	uint64_t	ce_ure_buf_flush20;			/* 0x00B180 */
	uint64_t	ce_ure_buf_flush21;			/* 0x00B188 */
	uint64_t	ce_ure_buf_flush22;			/* 0x00B190 */
	uint64_t	ce_ure_buf_flush23;			/* 0x00B198 */
	uint64_t	ce_ure_pcie_control1;			/* 0x00B1A0 */
	uint64_t	ce_ure_pcie_control2;			/* 0x00B1A8 */

	uint64_t	ce_pad_00B1B0[458];	    /* 0x00B1B0 -- 0x00BFF8 */

	/* Upstream Data Buffer, Port1 */
	struct ce_ure_maint_ups_dat1_data {
		uint64_t	data63_0[512];	    /* 0x00C000 -- 0x00CFF8 */
		uint64_t	data127_64[512];    /* 0x00D000 -- 0x00DFF8 */
		uint64_t	parity[512];	    /* 0x00E000 -- 0x00EFF8 */
	} ce_ure_maint_ups_dat1;

	/* Upstream Header Buffer, Port1 */
	struct ce_ure_maint_ups_hdr1_data {
		uint64_t	data63_0[512];	    /* 0x00F000 -- 0x00FFF8 */
		uint64_t	data127_64[512];    /* 0x010000 -- 0x010FF8 */
		uint64_t	parity[512];	    /* 0x011000 -- 0x011FF8 */
	} ce_ure_maint_ups_hdr1;

	/* Upstream Data Buffer, Port2 */
	struct ce_ure_maint_ups_dat2_data {
		uint64_t	data63_0[512];	    /* 0x012000 -- 0x012FF8 */
		uint64_t	data127_64[512];    /* 0x013000 -- 0x013FF8 */
		uint64_t	parity[512];	    /* 0x014000 -- 0x014FF8 */
	} ce_ure_maint_ups_dat2;

	/* Upstream Header Buffer, Port2 */
	struct ce_ure_maint_ups_hdr2_data {
		uint64_t	data63_0[512];	    /* 0x015000 -- 0x015FF8 */
		uint64_t	data127_64[512];    /* 0x016000 -- 0x016FF8 */
		uint64_t	parity[512];	    /* 0x017000 -- 0x017FF8 */
	} ce_ure_maint_ups_hdr2;

	/* Downstream Data Buffer */
	struct ce_ure_maint_dns_dat_data {
		uint64_t	data63_0[512];	    /* 0x018000 -- 0x018FF8 */
		uint64_t	data127_64[512];    /* 0x019000 -- 0x019FF8 */
		uint64_t	parity[512];	    /* 0x01A000 -- 0x01AFF8 */
	} ce_ure_maint_dns_dat;

	/* Downstream Header Buffer */
	struct	ce_ure_maint_dns_hdr_data {
		uint64_t	data31_0[64];	    /* 0x01B000 -- 0x01B1F8 */
		uint64_t	data95_32[64];	    /* 0x01B200 -- 0x01B3F8 */
		uint64_t	parity[64];	    /* 0x01B400 -- 0x01B5F8 */
	} ce_ure_maint_dns_hdr;

	/* RCI Buffer Data */
	struct	ce_ure_maint_rci_data {
		uint64_t	data41_0[64];	    /* 0x01B600 -- 0x01B7F8 */
		uint64_t	data69_42[64];	    /* 0x01B800 -- 0x01B9F8 */
	} ce_ure_maint_rci;

	/* Response Queue */
	uint64_t	ce_ure_maint_rspq[64];	    /* 0x01BA00 -- 0x01BBF8 */

	uint64_t	ce_pad_01C000[4224];	    /* 0x01BC00 -- 0x023FF8 */

	/* Admin Build-a-Packet Buffer */
	struct	ce_adm_maint_bap_buf_data {
		uint64_t	data63_0[258];	    /* 0x024000 -- 0x024808 */
		uint64_t	data127_64[258];    /* 0x024810 -- 0x025018 */
		uint64_t	parity[258];	    /* 0x025020 -- 0x025828 */
	} ce_adm_maint_bap_buf;

	uint64_t	ce_pad_025830[5370];	    /* 0x025830 -- 0x02FFF8 */

	/* URE: 40bit PMU ATE Buffer */		    /* 0x030000 -- 0x037FF8 */
	uint64_t	ce_ure_ate40[TIOCE_NUM_M40_ATES];

	/* URE: 32/40bit PMU ATE Buffer */	    /* 0x038000 -- 0x03BFF8 */
	uint64_t	ce_ure_ate3240[TIOCE_NUM_M3240_ATES];

	uint64_t	ce_pad_03C000[2050];	    /* 0x03C000 -- 0x040008 */

	/*
	 * DRE: Down Stream Request Engine
         */
	uint64_t	ce_dre_dyn_credit_status1;		/* 0x040010 */
	uint64_t	ce_dre_dyn_credit_status2;		/* 0x040018 */
	uint64_t	ce_dre_last_credit_status1;		/* 0x040020 */
	uint64_t	ce_dre_last_credit_status2;		/* 0x040028 */
	uint64_t	ce_dre_credit_limit1;			/* 0x040030 */
	uint64_t	ce_dre_credit_limit2;			/* 0x040038 */
	uint64_t	ce_dre_force_credit1;			/* 0x040040 */
	uint64_t	ce_dre_force_credit2;			/* 0x040048 */
	uint64_t	ce_dre_debug_mux1;			/* 0x040050 */
	uint64_t	ce_dre_debug_mux2;			/* 0x040058 */
	uint64_t	ce_dre_ssp_err_cmd_wrd;			/* 0x040060 */
	uint64_t	ce_dre_ssp_err_addr;			/* 0x040068 */
	uint64_t	ce_dre_comp_err_cmd_wrd;		/* 0x040070 */
	uint64_t	ce_dre_comp_err_addr;			/* 0x040078 */
	uint64_t	ce_dre_req_status;			/* 0x040080 */
	uint64_t	ce_dre_config1;				/* 0x040088 */
	uint64_t	ce_dre_config2;				/* 0x040090 */
	uint64_t	ce_dre_config_req_status;		/* 0x040098 */
	uint64_t	ce_pad_0400A0[12];	    /* 0x0400A0 -- 0x0400F8 */
	uint64_t	ce_dre_dyn_fifo;			/* 0x040100 */
	uint64_t	ce_pad_040108[3];	    /* 0x040108 -- 0x040118 */
	uint64_t	ce_dre_last_fifo;			/* 0x040120 */

	uint64_t	ce_pad_040128[27];	    /* 0x040128 -- 0x0401F8 */

	/* DRE Downstream Head Queue */
	struct	ce_dre_maint_ds_head_queue {
		uint64_t	data63_0[32];	    /* 0x040200 -- 0x0402F8 */
		uint64_t	data127_64[32];	    /* 0x040300 -- 0x0403F8 */
		uint64_t	parity[32];	    /* 0x040400 -- 0x0404F8 */
	} ce_dre_maint_ds_head_q;

	uint64_t	ce_pad_040500[352];	    /* 0x040500 -- 0x040FF8 */

	/* DRE Downstream Data Queue */
	struct	ce_dre_maint_ds_data_queue {
		uint64_t	data63_0[256];	    /* 0x041000 -- 0x0417F8 */
		uint64_t	ce_pad_041800[256]; /* 0x041800 -- 0x041FF8 */
		uint64_t	data127_64[256];    /* 0x042000 -- 0x0427F8 */
		uint64_t	ce_pad_042800[256]; /* 0x042800 -- 0x042FF8 */
		uint64_t	parity[256];	    /* 0x043000 -- 0x0437F8 */
		uint64_t	ce_pad_043800[256]; /* 0x043800 -- 0x043FF8 */
	} ce_dre_maint_ds_data_q;

	/* DRE URE Upstream Response Queue */
	struct	ce_dre_maint_ure_us_rsp_queue {
		uint64_t	data63_0[8];	    /* 0x044000 -- 0x044038 */
		uint64_t	ce_pad_044040[24];  /* 0x044040 -- 0x0440F8 */
		uint64_t	data127_64[8];      /* 0x044100 -- 0x044138 */
		uint64_t	ce_pad_044140[24];  /* 0x044140 -- 0x0441F8 */
		uint64_t	parity[8];	    /* 0x044200 -- 0x044238 */
		uint64_t	ce_pad_044240[24];  /* 0x044240 -- 0x0442F8 */
	} ce_dre_maint_ure_us_rsp_q;

	uint64_t 	ce_dre_maint_us_wrt_rsp[32];/* 0x044300 -- 0x0443F8 */

	uint64_t	ce_end_of_struct;			/* 0x044400 */
} tioce_t;


/* ce_adm_int_mask/ce_adm_int_status register bit defines */
#define CE_ADM_INT_CE_ERROR_SHFT		0
#define CE_ADM_INT_LSI1_IP_ERROR_SHFT		1
#define CE_ADM_INT_LSI2_IP_ERROR_SHFT		2
#define CE_ADM_INT_PCIE_ERROR_SHFT		3
#define CE_ADM_INT_PORT1_HOTPLUG_EVENT_SHFT	4
#define CE_ADM_INT_PORT2_HOTPLUG_EVENT_SHFT	5
#define CE_ADM_INT_PCIE_PORT1_DEV_A_SHFT	6
#define CE_ADM_INT_PCIE_PORT1_DEV_B_SHFT	7
#define CE_ADM_INT_PCIE_PORT1_DEV_C_SHFT	8
#define CE_ADM_INT_PCIE_PORT1_DEV_D_SHFT	9
#define CE_ADM_INT_PCIE_PORT2_DEV_A_SHFT	10
#define CE_ADM_INT_PCIE_PORT2_DEV_B_SHFT	11
#define CE_ADM_INT_PCIE_PORT2_DEV_C_SHFT	12
#define CE_ADM_INT_PCIE_PORT2_DEV_D_SHFT	13
#define CE_ADM_INT_PCIE_MSG_SHFT		14 /*see int_dest_14*/
#define CE_ADM_INT_PCIE_MSG_SLOT_0_SHFT		14
#define CE_ADM_INT_PCIE_MSG_SLOT_1_SHFT		15
#define CE_ADM_INT_PCIE_MSG_SLOT_2_SHFT		16
#define CE_ADM_INT_PCIE_MSG_SLOT_3_SHFT		17