tioce.h

linux-2.6.15.6

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (c) 2003-2005 Silicon Graphics, Inc. All rights reserved.
 */

#ifndef __ASM_IA64_SN_TIOCE_H__
#define __ASM_IA64_SN_TIOCE_H__

/* CE ASIC part & mfgr information  */
#define TIOCE_PART_NUM			0xCE00
#define TIOCE_MFGR_NUM			0x36
#define TIOCE_REV_A			0x1

/* CE Virtual PPB Vendor/Device IDs */
#define CE_VIRT_PPB_VENDOR_ID		0x10a9
#define CE_VIRT_PPB_DEVICE_ID		0x4002

/* CE Host Bridge Vendor/Device IDs */
#define CE_HOST_BRIDGE_VENDOR_ID	0x10a9
#define CE_HOST_BRIDGE_DEVICE_ID	0x4003


#define TIOCE_NUM_M40_ATES		4096
#define TIOCE_NUM_M3240_ATES		2048
#define TIOCE_NUM_PORTS			2

/*
 * Register layout for TIOCE.  MMR offsets are shown at the far right of the
 * structure definition.
 */
typedef volatile struct tioce {
	/*
	 * ADMIN : Administration Registers
	 */
	uint64_t	ce_adm_id;				/* 0x000000 */
	uint64_t	ce_pad_000008;				/* 0x000008 */
	uint64_t	ce_adm_dyn_credit_status;		/* 0x000010 */
	uint64_t	ce_adm_last_credit_status;		/* 0x000018 */
	uint64_t	ce_adm_credit_limit;			/* 0x000020 */
	uint64_t	ce_adm_force_credit;			/* 0x000028 */
	uint64_t	ce_adm_control;				/* 0x000030 */
	uint64_t	ce_adm_mmr_chn_timeout;			/* 0x000038 */
	uint64_t	ce_adm_ssp_ure_timeout;			/* 0x000040 */
	uint64_t	ce_adm_ssp_dre_timeout;			/* 0x000048 */
	uint64_t	ce_adm_ssp_debug_sel;			/* 0x000050 */
	uint64_t	ce_adm_int_status;			/* 0x000058 */
	uint64_t	ce_adm_int_status_alias;		/* 0x000060 */
	uint64_t	ce_adm_int_mask;			/* 0x000068 */
	uint64_t	ce_adm_int_pending;			/* 0x000070 */
	uint64_t	ce_adm_force_int;			/* 0x000078 */
	uint64_t	ce_adm_ure_ups_buf_barrier_flush;	/* 0x000080 */
	uint64_t	ce_adm_int_dest[15];	    /* 0x000088 -- 0x0000F8 */
	uint64_t	ce_adm_error_summary;			/* 0x000100 */
	uint64_t	ce_adm_error_summary_alias;		/* 0x000108 */
	uint64_t	ce_adm_error_mask;			/* 0x000110 */
	uint64_t	ce_adm_first_error;			/* 0x000118 */
	uint64_t	ce_adm_error_overflow;			/* 0x000120 */
	uint64_t	ce_adm_error_overflow_alias;		/* 0x000128 */
	uint64_t	ce_pad_000130[2];	    /* 0x000130 -- 0x000138 */
	uint64_t	ce_adm_tnum_error;			/* 0x000140 */
	uint64_t	ce_adm_mmr_err_detail;			/* 0x000148 */
	uint64_t	ce_adm_msg_sram_perr_detail;		/* 0x000150 */
	uint64_t	ce_adm_bap_sram_perr_detail;		/* 0x000158 */
	uint64_t	ce_adm_ce_sram_perr_detail;		/* 0x000160 */
	uint64_t	ce_adm_ce_credit_oflow_detail;		/* 0x000168 */
	uint64_t	ce_adm_tx_link_idle_max_timer;		/* 0x000170 */
	uint64_t	ce_adm_pcie_debug_sel;			/* 0x000178 */
	uint64_t	ce_pad_000180[16];	    /* 0x000180 -- 0x0001F8 */

	uint64_t	ce_adm_pcie_debug_sel_top;		/* 0x000200 */
	uint64_t	ce_adm_pcie_debug_lat_sel_lo_top;	/* 0x000208 */
	uint64_t	ce_adm_pcie_debug_lat_sel_hi_top;	/* 0x000210 */
	uint64_t	ce_adm_pcie_debug_trig_sel_top;		/* 0x000218 */
	uint64_t	ce_adm_pcie_debug_trig_lat_sel_lo_top;	/* 0x000220 */
	uint64_t	ce_adm_pcie_debug_trig_lat_sel_hi_top;	/* 0x000228 */
	uint64_t	ce_adm_pcie_trig_compare_top;		/* 0x000230 */
	uint64_t	ce_adm_pcie_trig_compare_en_top;	/* 0x000238 */
	uint64_t	ce_adm_ssp_debug_sel_top;		/* 0x000240 */
	uint64_t	ce_adm_ssp_debug_lat_sel_lo_top;	/* 0x000248 */
	uint64_t	ce_adm_ssp_debug_lat_sel_hi_top;	/* 0x000250 */
	uint64_t	ce_adm_ssp_debug_trig_sel_top;		/* 0x000258 */
	uint64_t	ce_adm_ssp_debug_trig_lat_sel_lo_top;	/* 0x000260 */
	uint64_t	ce_adm_ssp_debug_trig_lat_sel_hi_top;	/* 0x000268 */
	uint64_t	ce_adm_ssp_trig_compare_top;		/* 0x000270 */
	uint64_t	ce_adm_ssp_trig_compare_en_top;		/* 0x000278 */
	uint64_t	ce_pad_000280[48];	    /* 0x000280 -- 0x0003F8 */

	uint64_t	ce_adm_bap_ctrl;			/* 0x000400 */
	uint64_t	ce_pad_000408[127];	    /* 0x000408 -- 0x0007F8 */

	uint64_t	ce_msg_buf_data63_0[35];    /* 0x000800 -- 0x000918 */
	uint64_t	ce_pad_000920[29];	    /* 0x000920 -- 0x0009F8 */

	uint64_t	ce_msg_buf_data127_64[35];  /* 0x000A00 -- 0x000B18 */
	uint64_t	ce_pad_000B20[29];	    /* 0x000B20 -- 0x000BF8 */

	uint64_t	ce_msg_buf_parity[35];	    /* 0x000C00 -- 0x000D18 */
	uint64_t	ce_pad_000D20[29];	    /* 0x000D20 -- 0x000DF8 */

	uint64_t	ce_pad_000E00[576];	    /* 0x000E00 -- 0x001FF8 */

	/*
	 * LSI : LSI's PCI Express Link Registers (Link#1 and Link#2)
	 * Link#1 MMRs at start at 0x002000, Link#2 MMRs at 0x003000
	 * NOTE: the comment offsets at far right: let 'z' = {2 or 3}
	 */
	#define ce_lsi(link_num)	ce_lsi[link_num-1]
	struct ce_lsi_reg {
		uint64_t	ce_lsi_lpu_id;			/* 0x00z000 */
		uint64_t	ce_lsi_rst;			/* 0x00z008 */
		uint64_t	ce_lsi_dbg_stat;		/* 0x00z010 */
		uint64_t	ce_lsi_dbg_cfg;			/* 0x00z018 */
		uint64_t	ce_lsi_ltssm_ctrl;		/* 0x00z020 */
		uint64_t	ce_lsi_lk_stat;			/* 0x00z028 */
		uint64_t	ce_pad_00z030[2];   /* 0x00z030 -- 0x00z038 */
		uint64_t	ce_lsi_int_and_stat;		/* 0x00z040 */
		uint64_t	ce_lsi_int_mask;		/* 0x00z048 */
		uint64_t	ce_pad_00z050[22];  /* 0x00z050 -- 0x00z0F8 */
		uint64_t	ce_lsi_lk_perf_cnt_sel;		/* 0x00z100 */
		uint64_t	ce_pad_00z108;			/* 0x00z108 */
		uint64_t	ce_lsi_lk_perf_cnt_ctrl;	/* 0x00z110 */
		uint64_t	ce_pad_00z118;			/* 0x00z118 */
		uint64_t	ce_lsi_lk_perf_cnt1;		/* 0x00z120 */
		uint64_t	ce_lsi_lk_perf_cnt1_test;	/* 0x00z128 */
		uint64_t	ce_lsi_lk_perf_cnt2;		/* 0x00z130 */
		uint64_t	ce_lsi_lk_perf_cnt2_test;	/* 0x00z138 */
		uint64_t	ce_pad_00z140[24];  /* 0x00z140 -- 0x00z1F8 */
		uint64_t	ce_lsi_lk_lyr_cfg;		/* 0x00z200 */
		uint64_t	ce_lsi_lk_lyr_status;		/* 0x00z208 */
		uint64_t	ce_lsi_lk_lyr_int_stat;		/* 0x00z210 */
		uint64_t	ce_lsi_lk_ly_int_stat_test;	/* 0x00z218 */
		uint64_t	ce_lsi_lk_ly_int_stat_mask;	/* 0x00z220 */
		uint64_t	ce_pad_00z228[3];   /* 0x00z228 -- 0x00z238 */
		uint64_t	ce_lsi_fc_upd_ctl;		/* 0x00z240 */
		uint64_t	ce_pad_00z248[3];   /* 0x00z248 -- 0x00z258 */
		uint64_t	ce_lsi_flw_ctl_upd_to_timer;	/* 0x00z260 */
		uint64_t	ce_lsi_flw_ctl_upd_timer0;	/* 0x00z268 */
		uint64_t	ce_lsi_flw_ctl_upd_timer1;	/* 0x00z270 */
		uint64_t	ce_pad_00z278[49];  /* 0x00z278 -- 0x00z3F8 */
		uint64_t	ce_lsi_freq_nak_lat_thrsh;	/* 0x00z400 */
		uint64_t	ce_lsi_ack_nak_lat_tmr;		/* 0x00z408 */
		uint64_t	ce_lsi_rply_tmr_thr;		/* 0x00z410 */
		uint64_t	ce_lsi_rply_tmr;		/* 0x00z418 */
		uint64_t	ce_lsi_rply_num_stat;		/* 0x00z420 */
		uint64_t	ce_lsi_rty_buf_max_addr;	/* 0x00z428 */
		uint64_t	ce_lsi_rty_fifo_ptr;		/* 0x00z430 */
		uint64_t	ce_lsi_rty_fifo_rd_wr_ptr;	/* 0x00z438 */
		uint64_t	ce_lsi_rty_fifo_cred;		/* 0x00z440 */
		uint64_t	ce_lsi_seq_cnt;			/* 0x00z448 */
		uint64_t	ce_lsi_ack_sent_seq_num;	/* 0x00z450 */
		uint64_t	ce_lsi_seq_cnt_fifo_max_addr;	/* 0x00z458 */
		uint64_t	ce_lsi_seq_cnt_fifo_ptr;	/* 0x00z460 */
		uint64_t	ce_lsi_seq_cnt_rd_wr_ptr;	/* 0x00z468 */
		uint64_t	ce_lsi_tx_lk_ts_ctl;		/* 0x00z470 */
		uint64_t	ce_pad_00z478;			/* 0x00z478 */
		uint64_t	ce_lsi_mem_addr_ctl;		/* 0x00z480 */
		uint64_t	ce_lsi_mem_d_ld0;		/* 0x00z488 */
		uint64_t	ce_lsi_mem_d_ld1;		/* 0x00z490 */
		uint64_t	ce_lsi_mem_d_ld2;		/* 0x00z498 */
		uint64_t	ce_lsi_mem_d_ld3;		/* 0x00z4A0 */
		uint64_t	ce_lsi_mem_d_ld4;		/* 0x00z4A8 */
		uint64_t	ce_pad_00z4B0[2];   /* 0x00z4B0 -- 0x00z4B8 */
		uint64_t	ce_lsi_rty_d_cnt;		/* 0x00z4C0 */
		uint64_t	ce_lsi_seq_buf_cnt;		/* 0x00z4C8 */
		uint64_t	ce_lsi_seq_buf_bt_d;		/* 0x00z4D0 */
		uint64_t	ce_pad_00z4D8;			/* 0x00z4D8 */
		uint64_t	ce_lsi_ack_lat_thr;		/* 0x00z4E0 */
		uint64_t	ce_pad_00z4E8[3];   /* 0x00z4E8 -- 0x00z4F8 */
		uint64_t	ce_lsi_nxt_rcv_seq_1_cntr;	/* 0x00z500 */
		uint64_t	ce_lsi_unsp_dllp_rcvd;		/* 0x00z508 */
		uint64_t	ce_lsi_rcv_lk_ts_ctl;		/* 0x00z510 */
		uint64_t	ce_pad_00z518[29];  /* 0x00z518 -- 0x00z5F8 */
		uint64_t	ce_lsi_phy_lyr_cfg;		/* 0x00z600 */
		uint64_t	ce_pad_00z608;			/* 0x00z608 */
		uint64_t	ce_lsi_phy_lyr_int_stat;	/* 0x00z610 */
		uint64_t	ce_lsi_phy_lyr_int_stat_test;	/* 0x00z618 */
		uint64_t	ce_lsi_phy_lyr_int_mask;	/* 0x00z620 */
		uint64_t	ce_pad_00z628[11];  /* 0x00z628 -- 0x00z678 */
		uint64_t	ce_lsi_rcv_phy_cfg;		/* 0x00z680 */
		uint64_t	ce_lsi_rcv_phy_stat1;		/* 0x00z688 */
		uint64_t	ce_lsi_rcv_phy_stat2;		/* 0x00z690 */
		uint64_t	ce_lsi_rcv_phy_stat3;		/* 0x00z698 */
		uint64_t	ce_lsi_rcv_phy_int_stat;	/* 0x00z6A0 */
		uint64_t	ce_lsi_rcv_phy_int_stat_test;	/* 0x00z6A8 */
		uint64_t	ce_lsi_rcv_phy_int_mask;	/* 0x00z6B0 */
		uint64_t	ce_pad_00z6B8[9];   /* 0x00z6B8 -- 0x00z6F8 */
		uint64_t	ce_lsi_tx_phy_cfg;		/* 0x00z700 */
		uint64_t	ce_lsi_tx_phy_stat;		/* 0x00z708 */
		uint64_t	ce_lsi_tx_phy_int_stat;		/* 0x00z710 */
		uint64_t	ce_lsi_tx_phy_int_stat_test;	/* 0x00z718 */
		uint64_t	ce_lsi_tx_phy_int_mask;		/* 0x00z720 */
		uint64_t	ce_lsi_tx_phy_stat2;		/* 0x00z728 */
		uint64_t	ce_pad_00z730[10];  /* 0x00z730 -- 0x00z77F */
		uint64_t	ce_lsi_ltssm_cfg1;		/* 0x00z780 */
		uint64_t	ce_lsi_ltssm_cfg2;		/* 0x00z788 */
		uint64_t	ce_lsi_ltssm_cfg3;		/* 0x00z790 */
		uint64_t	ce_lsi_ltssm_cfg4;		/* 0x00z798 */
		uint64_t	ce_lsi_ltssm_cfg5;		/* 0x00z7A0 */
		uint64_t	ce_lsi_ltssm_stat1;		/* 0x00z7A8 */
		uint64_t	ce_lsi_ltssm_stat2;		/* 0x00z7B0 */
		uint64_t	ce_lsi_ltssm_int_stat;		/* 0x00z7B8 */
		uint64_t	ce_lsi_ltssm_int_stat_test;	/* 0x00z7C0 */
		uint64_t	ce_lsi_ltssm_int_mask;		/* 0x00z7C8 */
		uint64_t	ce_lsi_ltssm_stat_wr_en;	/* 0x00z7D0 */
		uint64_t	ce_pad_00z7D8[5];   /* 0x00z7D8 -- 0x00z7F8 */
		uint64_t	ce_lsi_gb_cfg1;			/* 0x00z800 */
		uint64_t	ce_lsi_gb_cfg2;			/* 0x00z808 */
		uint64_t	ce_lsi_gb_cfg3;			/* 0x00z810 */
		uint64_t	ce_lsi_gb_cfg4;			/* 0x00z818 */
		uint64_t	ce_lsi_gb_stat;			/* 0x00z820 */
		uint64_t	ce_lsi_gb_int_stat;		/* 0x00z828 */
		uint64_t	ce_lsi_gb_int_stat_test;	/* 0x00z830 */
		uint64_t	ce_lsi_gb_int_mask;		/* 0x00z838 */
		uint64_t	ce_lsi_gb_pwr_dn1;		/* 0x00z840 */
		uint64_t	ce_lsi_gb_pwr_dn2;		/* 0x00z848 */
		uint64_t	ce_pad_00z850[246]; /* 0x00z850 -- 0x00zFF8 */
	} ce_lsi[2];

	uint64_t	ce_pad_004000[10];	    /* 0x004000 -- 0x004048 */

	/*
	 * CRM: Coretalk Receive Module Registers
	 */
	uint64_t	ce_crm_debug_mux;			/* 0x004050 */
	uint64_t	ce_pad_004058;				/* 0x004058 */
	uint64_t	ce_crm_ssp_err_cmd_wrd;			/* 0x004060 */
	uint64_t	ce_crm_ssp_err_addr;			/* 0x004068 */
	uint64_t	ce_crm_ssp_err_syn;			/* 0x004070 */

	uint64_t	ce_pad_004078[499];	    /* 0x004078 -- 0x005008 */

	/*
         * CXM: Coretalk Xmit Module Registers
         */
	uint64_t	ce_cxm_dyn_credit_status;		/* 0x005010 */
	uint64_t	ce_cxm_last_credit_status;		/* 0x005018 */
	uint64_t	ce_cxm_credit_limit;			/* 0x005020 */
	uint64_t	ce_cxm_force_credit;			/* 0x005028 */
	uint64_t	ce_cxm_disable_bypass;			/* 0x005030 */
	uint64_t	ce_pad_005038[3];	    /* 0x005038 -- 0x005048 */