shubio.h

linux-2.6.15.6

 * PIO read or write request only if the bit for the requestor's        *
 * region is set; otherwise, the II will not perform the requested      *
 * operation and will return an error response. When a PIO read or      *
 * write request targets an external Crosstalk widget, then not only    *
 * must the bit for the requestor's region be set in the ILAPR, but     *
 * also the target widget's bit in the IOWA register must be set in     *
 * order for the II to perform the requested operation; otherwise,      *
 * the II will return an error response. Hence, the protection          *
 * provided by the IOWA register supplements the protection provided    *
 * by the ILAPR for requests that target external Crosstalk widgets.    *
 * This register itself can be accessed only by the nodes whose         *
 * region ID bits are enabled in this same register. It can also be     *
 * accessed through the IAlias space by the local processors.           *
 * The reset value of this register allows access by all nodes.         *
 *									*
 ************************************************************************/

typedef union ii_ilapr_u {
	uint64_t ii_ilapr_regval;
	struct {
		uint64_t i_region:64;
	} ii_ilapr_fld_s;
} ii_ilapr_u_t;

/************************************************************************
 *									*
 * Description:  A write to this register of the 64-bit value           *
 * "SGIrules" in ASCII, will cause the bit in the ILAPR register        *
 * corresponding to the region of the requestor to be set (allow        *
 * access). A write of any other value will be ignored. Access          *
 * protection for this register is "SGIrules".                          *
 * This register can also be accessed through the IAlias space.         *
 * However, this access will not change the access permissions in the   *
 * ILAPR.                                                               *
 *									*
 ************************************************************************/

typedef union ii_ilapo_u {
	uint64_t ii_ilapo_regval;
	struct {
		uint64_t i_io_ovrride:64;
	} ii_ilapo_fld_s;
} ii_ilapo_u_t;

/************************************************************************
 *									*
 *  This register qualifies all the PIO and Graphics writes launched    *
 * from the SHUB towards a widget.                                      *
 *									*
 ************************************************************************/

typedef union ii_iowa_u {
	uint64_t ii_iowa_regval;
	struct {
		uint64_t i_w0_oac:1;
		uint64_t i_rsvd_1:7;
		uint64_t i_wx_oac:8;
		uint64_t i_rsvd:48;
	} ii_iowa_fld_s;
} ii_iowa_u_t;

/************************************************************************
 *									*
 * Description:  This register qualifies all the requests launched      *
 * from a widget towards the Shub. This register is intended to be      *
 * used by software in case of misbehaving widgets.                     *
 *									*
 *									*
 ************************************************************************/

typedef union ii_iiwa_u {
	uint64_t ii_iiwa_regval;
	struct {
		uint64_t i_w0_iac:1;
		uint64_t i_rsvd_1:7;
		uint64_t i_wx_iac:8;
		uint64_t i_rsvd:48;
	} ii_iiwa_fld_s;
} ii_iiwa_u_t;

/************************************************************************
 *									*
 * Description:  This register qualifies all the operations launched    *
 * from a widget towards the SHub. It allows individual access          *
 * control for up to 8 devices per widget. A device refers to           *
 * individual DMA master hosted by a widget.                            *
 * The bits in each field of this register are cleared by the Shub      *
 * upon detection of an error which requires the device to be           *
 * disabled. These fields assume that 0=TNUM=7 (i.e., Bridge-centric    *
 * Crosstalk). Whether or not a device has access rights to this        *
 * Shub is determined by an AND of the device enable bit in the         *
 * appropriate field of this register and the corresponding bit in      *
 * the Wx_IAC field (for the widget which this device belongs to).      *
 * The bits in this field are set by writing a 1 to them. Incoming      *
 * replies from Crosstalk are not subject to this access control        *
 * mechanism.                                                           *
 *									*
 ************************************************************************/

typedef union ii_iidem_u {
	uint64_t ii_iidem_regval;
	struct {
		uint64_t i_w8_dxs:8;
		uint64_t i_w9_dxs:8;
		uint64_t i_wa_dxs:8;
		uint64_t i_wb_dxs:8;
		uint64_t i_wc_dxs:8;
		uint64_t i_wd_dxs:8;
		uint64_t i_we_dxs:8;
		uint64_t i_wf_dxs:8;
	} ii_iidem_fld_s;
} ii_iidem_u_t;

/************************************************************************
 *									*
 *  This register contains the various programmable fields necessary    *
 * for controlling and observing the LLP signals.                       *
 *									*
 ************************************************************************/

typedef union ii_ilcsr_u {
	uint64_t ii_ilcsr_regval;
	struct {
		uint64_t i_nullto:6;
		uint64_t i_rsvd_4:2;
		uint64_t i_wrmrst:1;
		uint64_t i_rsvd_3:1;
		uint64_t i_llp_en:1;
		uint64_t i_bm8:1;
		uint64_t i_llp_stat:2;
		uint64_t i_remote_power:1;
		uint64_t i_rsvd_2:1;
		uint64_t i_maxrtry:10;
		uint64_t i_d_avail_sel:2;
		uint64_t i_rsvd_1:4;
		uint64_t i_maxbrst:10;
		uint64_t i_rsvd:22;

	} ii_ilcsr_fld_s;
} ii_ilcsr_u_t;

/************************************************************************
 *									*
 *  This is simply a status registers that monitors the LLP error       *
 * rate.								*
 *									*
 ************************************************************************/

typedef union ii_illr_u {
	uint64_t ii_illr_regval;
	struct {
		uint64_t i_sn_cnt:16;
		uint64_t i_cb_cnt:16;
		uint64_t i_rsvd:32;
	} ii_illr_fld_s;
} ii_illr_u_t;

/************************************************************************
 *									*
 * Description:  All II-detected non-BTE error interrupts are           *
 * specified via this register.                                         *
 * NOTE: The PI interrupt register address is hardcoded in the II. If   *
 * PI_ID==0, then the II sends an interrupt request (Duplonet PWRI      *
 * packet) to address offset 0x0180_0090 within the local register      *
 * address space of PI0 on the node specified by the NODE field. If     *
 * PI_ID==1, then the II sends the interrupt request to address         *
 * offset 0x01A0_0090 within the local register address space of PI1    *
 * on the node specified by the NODE field.                             *
 *									*
 ************************************************************************/

typedef union ii_iidsr_u {
	uint64_t ii_iidsr_regval;
	struct {
		uint64_t i_level:8;
		uint64_t i_pi_id:1;
		uint64_t i_node:11;
		uint64_t i_rsvd_3:4;
		uint64_t i_enable:1;
		uint64_t i_rsvd_2:3;
		uint64_t i_int_sent:2;
		uint64_t i_rsvd_1:2;
		uint64_t i_pi0_forward_int:1;
		uint64_t i_pi1_forward_int:1;
		uint64_t i_rsvd:30;
	} ii_iidsr_fld_s;
} ii_iidsr_u_t;

/************************************************************************
 *									*
 *  There are two instances of this register. This register is used     *
 * for matching up the incoming responses from the graphics widget to   *
 * the processor that initiated the graphics operation. The             *
 * write-responses are converted to graphics credits and returned to    *
 * the processor so that the processor interface can manage the flow    *
 * control.                                                             *
 *									*
 ************************************************************************/

typedef union ii_igfx0_u {
	uint64_t ii_igfx0_regval;
	struct {
		uint64_t i_w_num:4;
		uint64_t i_pi_id:1;
		uint64_t i_n_num:12;
		uint64_t i_p_num:1;
		uint64_t i_rsvd:46;
	} ii_igfx0_fld_s;
} ii_igfx0_u_t;

/************************************************************************
 *									*
 *  There are two instances of this register. This register is used     *
 * for matching up the incoming responses from the graphics widget to   *
 * the processor that initiated the graphics operation. The             *
 * write-responses are converted to graphics credits and returned to    *
 * the processor so that the processor interface can manage the flow    *
 * control.                                                             *
 *									*
 ************************************************************************/

typedef union ii_igfx1_u {
	uint64_t ii_igfx1_regval;
	struct {
		uint64_t i_w_num:4;
		uint64_t i_pi_id:1;
		uint64_t i_n_num:12;
		uint64_t i_p_num:1;
		uint64_t i_rsvd:46;
	} ii_igfx1_fld_s;
} ii_igfx1_u_t;

/************************************************************************
 *									*
 *  There are two instances of this registers. These registers are      *
 * used as scratch registers for software use.                          *
 *									*
 ************************************************************************/

typedef union ii_iscr0_u {
	uint64_t ii_iscr0_regval;
	struct {
		uint64_t i_scratch:64;
	} ii_iscr0_fld_s;
} ii_iscr0_u_t;

/************************************************************************
 *									*
 *  There are two instances of this registers. These registers are      *
 * used as scratch registers for software use.                          *
 *									*
 ************************************************************************/

typedef union ii_iscr1_u {
	uint64_t ii_iscr1_regval;
	struct {
		uint64_t i_scratch:64;
	} ii_iscr1_fld_s;
} ii_iscr1_u_t;

/************************************************************************
 *									*
 * Description:  There are seven instances of translation table entry   *
 * registers. Each register maps a Shub Big Window to a 48-bit          *
 * address on Crosstalk.                                                *
 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *
 * number) are used to select one of these 7 registers. The Widget      *
 * number field is then derived from the W_NUM field for synthesizing   *
 * a Crosstalk packet. The 5 bits of OFFSET are concatenated with       *
 * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34]      *
 * are padded with zeros. Although the maximum Crosstalk space          *
 * addressable by the SHub is thus the lower 16 GBytes per widget       * 
 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this       *
 * space can be accessed.                                               *
 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *
 * Window number) are used to select one of these 7 registers. The      *
 * Widget number field is then derived from the W_NUM field for         *
 * synthesizing a Crosstalk packet. The 5 bits of OFFSET are            *
 * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP      *
 * field is used as Crosstalk[47], and remainder of the Crosstalk       *
 * address bits (Crosstalk[46:34]) are always zero. While the maximum   *
 * Crosstalk space addressable by the Shub is thus the lower            *
 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
 * of this space can be accessed.                                       *
 *									*
 ************************************************************************/

typedef union ii_itte1_u {
	uint64_t ii_itte1_regval;
	struct {
		uint64_t i_offset:5;
		uint64_t i_rsvd_1:3;
		uint64_t i_w_num:4;
		uint64_t i_iosp:1;