core.h

linux-2.6.15.6

					0	XCHAL_SEP \
					0	XCHAL_SEP \
					0	XCHAL_SEP \
					0	XCHAL_SEP \
					0	XCHAL_SEP \
					0	XCHAL_SEP \
					0	XCHAL_SEP \
					0

/*  Type of each interrupt:  */
#define XCHAL_INT0_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT1_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT2_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT3_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT4_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT5_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT6_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT7_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
#define XCHAL_INT8_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
#define XCHAL_INT9_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
#define XCHAL_INT10_TYPE 	XTHAL_INTTYPE_TIMER
#define XCHAL_INT11_TYPE 	XTHAL_INTTYPE_TIMER
#define XCHAL_INT12_TYPE 	XTHAL_INTTYPE_TIMER
#define XCHAL_INT13_TYPE 	XTHAL_INTTYPE_SOFTWARE
#define XCHAL_INT14_TYPE 	XTHAL_INTTYPE_SOFTWARE
#define XCHAL_INT15_TYPE 	XTHAL_INTTYPE_SOFTWARE
#define XCHAL_INT16_TYPE 	XTHAL_INTTYPE_SOFTWARE
#define XCHAL_INT17_TYPE 	XTHAL_INTTYPE_UNCONFIGURED
#define XCHAL_INT18_TYPE 	XTHAL_INTTYPE_UNCONFIGURED
#define XCHAL_INT19_TYPE 	XTHAL_INTTYPE_UNCONFIGURED
#define XCHAL_INT20_TYPE 	XTHAL_INTTYPE_UNCONFIGURED
#define XCHAL_INT21_TYPE 	XTHAL_INTTYPE_UNCONFIGURED
#define XCHAL_INT22_TYPE 	XTHAL_INTTYPE_UNCONFIGURED
#define XCHAL_INT23_TYPE 	XTHAL_INTTYPE_UNCONFIGURED
#define XCHAL_INT24_TYPE 	XTHAL_INTTYPE_UNCONFIGURED
#define XCHAL_INT25_TYPE 	XTHAL_INTTYPE_UNCONFIGURED
#define XCHAL_INT26_TYPE 	XTHAL_INTTYPE_UNCONFIGURED
#define XCHAL_INT27_TYPE 	XTHAL_INTTYPE_UNCONFIGURED
#define XCHAL_INT28_TYPE 	XTHAL_INTTYPE_UNCONFIGURED
#define XCHAL_INT29_TYPE 	XTHAL_INTTYPE_UNCONFIGURED
#define XCHAL_INT30_TYPE 	XTHAL_INTTYPE_UNCONFIGURED
#define XCHAL_INT31_TYPE 	XTHAL_INTTYPE_UNCONFIGURED
/*  As an array of entries (eg. for C constant arrays):  */
#define XCHAL_INT_TYPES		XTHAL_INTTYPE_EXTERN_LEVEL     	XCHAL_SEP \
				XTHAL_INTTYPE_EXTERN_LEVEL     	XCHAL_SEP \
				XTHAL_INTTYPE_EXTERN_LEVEL     	XCHAL_SEP \
				XTHAL_INTTYPE_EXTERN_LEVEL     	XCHAL_SEP \
				XTHAL_INTTYPE_EXTERN_LEVEL     	XCHAL_SEP \
				XTHAL_INTTYPE_EXTERN_LEVEL     	XCHAL_SEP \
				XTHAL_INTTYPE_EXTERN_LEVEL     	XCHAL_SEP \
				XTHAL_INTTYPE_EXTERN_EDGE     	XCHAL_SEP \
				XTHAL_INTTYPE_EXTERN_EDGE     	XCHAL_SEP \
				XTHAL_INTTYPE_EXTERN_EDGE     	XCHAL_SEP \
				XTHAL_INTTYPE_TIMER     	XCHAL_SEP \
				XTHAL_INTTYPE_TIMER     	XCHAL_SEP \
				XTHAL_INTTYPE_TIMER     	XCHAL_SEP \
				XTHAL_INTTYPE_SOFTWARE     	XCHAL_SEP \
				XTHAL_INTTYPE_SOFTWARE     	XCHAL_SEP \
				XTHAL_INTTYPE_SOFTWARE     	XCHAL_SEP \
				XTHAL_INTTYPE_SOFTWARE     	XCHAL_SEP \
				XTHAL_INTTYPE_UNCONFIGURED     	XCHAL_SEP \
				XTHAL_INTTYPE_UNCONFIGURED     	XCHAL_SEP \
				XTHAL_INTTYPE_UNCONFIGURED     	XCHAL_SEP \
				XTHAL_INTTYPE_UNCONFIGURED     	XCHAL_SEP \
				XTHAL_INTTYPE_UNCONFIGURED     	XCHAL_SEP \
				XTHAL_INTTYPE_UNCONFIGURED     	XCHAL_SEP \
				XTHAL_INTTYPE_UNCONFIGURED     	XCHAL_SEP \
				XTHAL_INTTYPE_UNCONFIGURED     	XCHAL_SEP \
				XTHAL_INTTYPE_UNCONFIGURED     	XCHAL_SEP \
				XTHAL_INTTYPE_UNCONFIGURED     	XCHAL_SEP \
				XTHAL_INTTYPE_UNCONFIGURED     	XCHAL_SEP \
				XTHAL_INTTYPE_UNCONFIGURED     	XCHAL_SEP \
				XTHAL_INTTYPE_UNCONFIGURED     	XCHAL_SEP \
				XTHAL_INTTYPE_UNCONFIGURED     	XCHAL_SEP \
				XTHAL_INTTYPE_UNCONFIGURED

/*  Masks of interrupts for each type of interrupt:  */
#define XCHAL_INTTYPE_MASK_UNCONFIGURED	0xFFFE0000
#define XCHAL_INTTYPE_MASK_SOFTWARE	0x0001E000
#define XCHAL_INTTYPE_MASK_EXTERN_EDGE	0x00000380
#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL	0x0000007F
#define XCHAL_INTTYPE_MASK_TIMER	0x00001C00
#define XCHAL_INTTYPE_MASK_NMI		0x00000000
/*  As an array of entries (eg. for C constant arrays):  */
#define XCHAL_INTTYPE_MASKS		0xFFFE0000	XCHAL_SEP \
					0x0001E000	XCHAL_SEP \
					0x00000380	XCHAL_SEP \
					0x0000007F	XCHAL_SEP \
					0x00001C00	XCHAL_SEP \
					0x00000000

/*  Interrupts assigned to each timer (CCOMPARE0 to CCOMPARE3), -1 if unassigned  */
#define XCHAL_TIMER0_INTERRUPT	10
#define XCHAL_TIMER1_INTERRUPT	11
#define XCHAL_TIMER2_INTERRUPT	12
#define XCHAL_TIMER3_INTERRUPT	XTHAL_TIMER_UNCONFIGURED
/*  As an array of entries (eg. for C constant arrays):  */
#define XCHAL_TIMER_INTERRUPTS	10	XCHAL_SEP \
				11	XCHAL_SEP \
				12	XCHAL_SEP \
				XTHAL_TIMER_UNCONFIGURED

/*  Indexing macros:  */
#define _XCHAL_INTLEVEL_MASK(n)		XCHAL_INTLEVEL ## n ## _MASK
#define XCHAL_INTLEVEL_MASK(n)		_XCHAL_INTLEVEL_MASK(n)		/* n = 0 .. 15 */
#define _XCHAL_INTLEVEL_ANDBELOWMASK(n)	XCHAL_INTLEVEL ## n ## _ANDBELOW_MASK
#define XCHAL_INTLEVEL_ANDBELOW_MASK(n)	_XCHAL_INTLEVEL_ANDBELOWMASK(n)	/* n = 0 .. 15 */
#define _XCHAL_INT_LEVEL(n)		XCHAL_INT ## n ## _LEVEL
#define XCHAL_INT_LEVEL(n)		_XCHAL_INT_LEVEL(n)		/* n = 0 .. 31 */
#define _XCHAL_INT_TYPE(n)		XCHAL_INT ## n ## _TYPE
#define XCHAL_INT_TYPE(n)		_XCHAL_INT_TYPE(n)		/* n = 0 .. 31 */
#define _XCHAL_TIMER_INTERRUPT(n)	XCHAL_TIMER ## n ## _INTERRUPT
#define XCHAL_TIMER_INTERRUPT(n)	_XCHAL_TIMER_INTERRUPT(n)	/* n = 0 .. 3 */



/*
 *  External interrupt vectors/levels.
 *  These macros describe how Xtensa processor interrupt numbers
 *  (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
 *  map to external BInterrupt<n> pins, for those interrupts
 *  configured as external (level-triggered, edge-triggered, or NMI).
 *  See the Xtensa processor databook for more details.
 */

/*  Core interrupt numbers mapped to each EXTERNAL interrupt number:  */
#define XCHAL_EXTINT0_NUM		0	/* (intlevel 1) */
#define XCHAL_EXTINT1_NUM		1	/* (intlevel 2) */
#define XCHAL_EXTINT2_NUM		2	/* (intlevel 3) */
#define XCHAL_EXTINT3_NUM		3	/* (intlevel 1) */
#define XCHAL_EXTINT4_NUM		4	/* (intlevel 1) */
#define XCHAL_EXTINT5_NUM		5	/* (intlevel 1) */
#define XCHAL_EXTINT6_NUM		6	/* (intlevel 1) */
#define XCHAL_EXTINT7_NUM		7	/* (intlevel 1) */
#define XCHAL_EXTINT8_NUM		8	/* (intlevel 2) */
#define XCHAL_EXTINT9_NUM		9	/* (intlevel 3) */

/*  Corresponding interrupt masks:  */
#define XCHAL_EXTINT0_MASK		0x00000001
#define XCHAL_EXTINT1_MASK		0x00000002
#define XCHAL_EXTINT2_MASK		0x00000004
#define XCHAL_EXTINT3_MASK		0x00000008
#define XCHAL_EXTINT4_MASK		0x00000010
#define XCHAL_EXTINT5_MASK		0x00000020
#define XCHAL_EXTINT6_MASK		0x00000040
#define XCHAL_EXTINT7_MASK		0x00000080
#define XCHAL_EXTINT8_MASK		0x00000100
#define XCHAL_EXTINT9_MASK		0x00000200

/*  Core config interrupt levels mapped to each external interrupt:  */
#define XCHAL_EXTINT0_LEVEL		1	/* (int number 0) */
#define XCHAL_EXTINT1_LEVEL		2	/* (int number 1) */
#define XCHAL_EXTINT2_LEVEL		3	/* (int number 2) */
#define XCHAL_EXTINT3_LEVEL		1	/* (int number 3) */
#define XCHAL_EXTINT4_LEVEL		1	/* (int number 4) */
#define XCHAL_EXTINT5_LEVEL		1	/* (int number 5) */
#define XCHAL_EXTINT6_LEVEL		1	/* (int number 6) */
#define XCHAL_EXTINT7_LEVEL		1	/* (int number 7) */
#define XCHAL_EXTINT8_LEVEL		2	/* (int number 8) */
#define XCHAL_EXTINT9_LEVEL		3	/* (int number 9) */


/*----------------------------------------------------------------------
			EXCEPTIONS and VECTORS
  ----------------------------------------------------------------------*/

#define XCHAL_HAVE_EXCEPTIONS		1	/* 1 if exception option configured, 0 otherwise */

#define XCHAL_XEA_VERSION		2	/* Xtensa Exception Architecture number: 1 for XEA1 (old), 2 for XEA2 (new) */
#define XCHAL_HAVE_XEA1			0	/* 1 if XEA1, 0 otherwise */
#define XCHAL_HAVE_XEA2			1	/* 1 if XEA2, 0 otherwise */
/*  For backward compatibility ONLY -- DO NOT USE (will be removed in future release):  */
#define XCHAL_HAVE_OLD_EXC_ARCH		XCHAL_HAVE_XEA1	/* (DEPRECATED) 1 if old exception architecture (XEA1), 0 otherwise (eg. XEA2) */
#define XCHAL_HAVE_EXCM			XCHAL_HAVE_XEA2	/* (DEPRECATED) 1 if PS.EXCM bit exists (currently equals XCHAL_HAVE_TLBS) */

#define XCHAL_RESET_VECTOR_VADDR	0xFE000020
#define XCHAL_RESET_VECTOR_PADDR	0xFE000020
#define XCHAL_USER_VECTOR_VADDR		0xD0000220
#define XCHAL_PROGRAMEXC_VECTOR_VADDR	XCHAL_USER_VECTOR_VADDR		/* for backward compatibility */
#define XCHAL_USEREXC_VECTOR_VADDR	XCHAL_USER_VECTOR_VADDR		/* for backward compatibility */
#define XCHAL_USER_VECTOR_PADDR		0x00000220
#define XCHAL_PROGRAMEXC_VECTOR_PADDR	XCHAL_USER_VECTOR_PADDR		/* for backward compatibility */
#define XCHAL_USEREXC_VECTOR_PADDR	XCHAL_USER_VECTOR_PADDR		/* for backward compatibility */
#define XCHAL_KERNEL_VECTOR_VADDR	0xD0000200
#define XCHAL_STACKEDEXC_VECTOR_VADDR	XCHAL_KERNEL_VECTOR_VADDR	/* for backward compatibility */
#define XCHAL_KERNELEXC_VECTOR_VADDR	XCHAL_KERNEL_VECTOR_VADDR	/* for backward compatibility */
#define XCHAL_KERNEL_VECTOR_PADDR	0x00000200
#define XCHAL_STACKEDEXC_VECTOR_PADDR	XCHAL_KERNEL_VECTOR_PADDR	/* for backward compatibility */
#define XCHAL_KERNELEXC_VECTOR_PADDR	XCHAL_KERNEL_VECTOR_PADDR	/* for backward compatibility */
#define XCHAL_DOUBLEEXC_VECTOR_VADDR	0xD0000290
#define XCHAL_DOUBLEEXC_VECTOR_PADDR	0x00000290
#define XCHAL_WINDOW_VECTORS_VADDR	0xD0000000
#define XCHAL_WINDOW_VECTORS_PADDR	0x00000000
#define XCHAL_INTLEVEL2_VECTOR_VADDR	0xD0000240
#define XCHAL_INTLEVEL2_VECTOR_PADDR	0x00000240
#define XCHAL_INTLEVEL3_VECTOR_VADDR	0xD0000250
#define XCHAL_INTLEVEL3_VECTOR_PADDR	0x00000250
#define XCHAL_INTLEVEL4_VECTOR_VADDR	0xFE000520
#define XCHAL_INTLEVEL4_VECTOR_PADDR	0xFE000520
#define XCHAL_DEBUG_VECTOR_VADDR	XCHAL_INTLEVEL4_VECTOR_VADDR
#define XCHAL_DEBUG_VECTOR_PADDR	XCHAL_INTLEVEL4_VECTOR_PADDR

/*  Indexing macros:  */
#define _XCHAL_INTLEVEL_VECTOR_VADDR(n)		XCHAL_INTLEVEL ## n ## _VECTOR_VADDR
#define XCHAL_INTLEVEL_VECTOR_VADDR(n)		_XCHAL_INTLEVEL_VECTOR_VADDR(n)		/* n = 0 .. 15 */

/*
 *  General Exception Causes
 *  (values of EXCCAUSE special register set by general exceptions,
 *   which vector to the user, kernel, or double-exception vectors):
 */
#define XCHAL_EXCCAUSE_ILLEGAL_INSTRUCTION		0	/* Illegal Instruction (IllegalInstruction) */
#define XCHAL_EXCCAUSE_SYSTEM_CALL			1	/* System Call (SystemCall) */
#define XCHAL_EXCCAUSE_INSTRUCTION_FETCH_ERROR		2	/* Instruction Fetch Error (InstructionFetchError) */
#define XCHAL_EXCCAUSE_LOAD_STORE_ERROR			3	/* Load Store Error (LoadStoreError) */
#define XCHAL_EXCCAUSE_LEVEL1_INTERRUPT			4	/* Level 1 Interrupt (Level1Interrupt) */
#define XCHAL_EXCCAUSE_ALLOCA				5	/* Stack Extension Assist (Alloca) */
#define XCHAL_EXCCAUSE_INTEGER_DIVIDE_BY_ZERO		6	/* Integer Divide by Zero (IntegerDivideByZero) */
#define XCHAL_EXCCAUSE_SPECULATION			7	/* Speculation (Speculation) */
#define XCHAL_EXCCAUSE_PRIVILEGED			8	/* Privileged Instruction (Privileged) */
#define XCHAL_EXCCAUSE_UNALIGNED			9	/* Unaligned Load Store (Unaligned) */
#define XCHAL_EXCCAUSE_ITLB_MISS			16	/* ITlb Miss Exception (ITlbMiss) */
#define XCHAL_EXCCAUSE_ITLB_MULTIHIT			17	/* ITlb Mutltihit Exception (ITlbMultihit) */
#define XCHAL_EXCCAUSE_ITLB_PRIVILEGE			18	/* ITlb Privilege Exception (ITlbPrivilege) */
#define XCHAL_EXCCAUSE_ITLB_SIZE_RESTRICTION		19	/* ITlb Size Restriction Exception (ITlbSizeRestriction) */
#define XCHAL_EXCCAUSE_FETCH_CACHE_ATTRIBUTE		20	/* Fetch Cache Attribute Exception (FetchCacheAttribute) */
#define XCHAL_EXCCAUSE_DTLB_MISS			24	/* DTlb Miss Exception (DTlbMiss) */
#define XCHAL_EXCCAUSE_DTLB_MULTIHIT			25	/* DTlb Multihit Exception (DTlbMultihit) */
#define XCHAL_EXCCAUSE_DTLB_PRIVILEGE			26	/* DTlb Privilege Exception (DTlbPrivilege) */
#define XCHAL_EXCCAUSE_DTLB_SIZE_RESTRICTION		27	/* DTlb Size Restriction Exception (DTlbSizeRestriction) */
#define XCHAL_EXCCAUSE_LOAD_CACHE_ATTRIBUTE		28	/* Load Cache Attribute Exception (LoadCacheAttribute) */
#define XCHAL_EXCCAUSE_STORE_CACHE_ATTRIBUTE		29	/* Store Cache Attribute Exception (StoreCacheAttribute) */
#define XCHAL_EXCCAUSE_FLOATING_POINT			40	/* Floating Point Exception (FloatingPoint) */



/*----------------------------------------------------------------------
				TIMERS
  ----------------------------------------------------------------------*/

#define XCHAL_HAVE_CCOUNT		1	/* 1 if have CCOUNT, 0 otherwise */
/*#define XCHAL_HAVE_TIMERS		XCHAL_HAVE_CCOUNT*/
#define XCHAL_NUM_TIMERS		3	/* number of CCOMPAREn regs */