core.h

linux-2.6.15.6

/*
 * xtensa/config/core.h -- HAL definitions that are dependent on CORE configuration
 *
 *  This header file is sometimes referred to as the "compile-time HAL" or CHAL.
 *  It was generated for a specific Xtensa processor configuration.
 *
 *  Source for configuration-independent binaries (which link in a
 *  configuration-specific HAL library) must NEVER include this file.
 *  It is perfectly normal, however, for the HAL source itself to include this file.
 */

/*
 * Copyright (c) 2003 Tensilica, Inc.  All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2.1 of the GNU Lesser General Public
 * License as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it would be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 *
 * Further, this software is distributed without any warranty that it is
 * free of the rightful claim of any third person regarding infringement
 * or the like.  Any license provided herein, whether implied or
 * otherwise, applies only to this software file.  Patent licenses, if
 * any, provided herein do not apply to combinations of this program with
 * other software, or any other product whatsoever.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this program; if not, write the Free Software
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
 * USA.
 */


#ifndef XTENSA_CONFIG_CORE_H
#define XTENSA_CONFIG_CORE_H

#include <xtensa/hal.h>


/*----------------------------------------------------------------------
				GENERAL
  ----------------------------------------------------------------------*/

/*
 *  Separators for macros that expand into arrays.
 *  These can be predefined by files that #include this one,
 *  when different separators are required.
 */
/*  Element separator for macros that expand into 1-dimensional arrays:  */
#ifndef XCHAL_SEP
#define XCHAL_SEP			,
#endif
/*  Array separator for macros that expand into 2-dimensional arrays:  */
#ifndef XCHAL_SEP2
#define XCHAL_SEP2			},{
#endif


/*----------------------------------------------------------------------
				ENDIANNESS
  ----------------------------------------------------------------------*/

#define XCHAL_HAVE_BE			1
#define XCHAL_HAVE_LE			0
#define XCHAL_MEMORY_ORDER		XTHAL_BIGENDIAN


/*----------------------------------------------------------------------
				REGISTER WINDOWS
  ----------------------------------------------------------------------*/

#define XCHAL_HAVE_WINDOWED		1	/* 1 if windowed registers option configured, 0 otherwise */
#define XCHAL_NUM_AREGS			64	/* number of physical address regs */
#define XCHAL_NUM_AREGS_LOG2		6	/* log2(XCHAL_NUM_AREGS) */


/*----------------------------------------------------------------------
				ADDRESS ALIGNMENT
  ----------------------------------------------------------------------*/

/*  These apply to a selected set of core load and store instructions only (see ISA):  */
#define XCHAL_UNALIGNED_LOAD_EXCEPTION	1	/* 1 if unaligned loads cause an exception, 0 otherwise */
#define XCHAL_UNALIGNED_STORE_EXCEPTION	1	/* 1 if unaligned stores cause an exception, 0 otherwise */


/*----------------------------------------------------------------------
				INTERRUPTS
  ----------------------------------------------------------------------*/

#define XCHAL_HAVE_INTERRUPTS		1	/* 1 if interrupt option configured, 0 otherwise */
#define XCHAL_HAVE_HIGHPRI_INTERRUPTS	1	/* 1 if high-priority interrupt option configured, 0 otherwise */
#define XCHAL_HAVE_HIGHLEVEL_INTERRUPTS	XCHAL_HAVE_HIGHPRI_INTERRUPTS
#define XCHAL_HAVE_NMI			0	/* 1 if NMI option configured, 0 otherwise */
#define XCHAL_NUM_INTERRUPTS		17	/* number of interrupts */
#define XCHAL_NUM_INTERRUPTS_LOG2	5	/* number of bits to hold an interrupt number: roundup(log2(number of interrupts)) */
#define XCHAL_NUM_EXTINTERRUPTS		10	/* number of external interrupts */
#define XCHAL_NUM_INTLEVELS		4	/* number of interrupt levels (not including level zero!) */
#define XCHAL_NUM_LOWPRI_LEVELS		1			/* number of low-priority interrupt levels (always 1) */
#define XCHAL_FIRST_HIGHPRI_LEVEL	(XCHAL_NUM_LOWPRI_LEVELS+1)	/* level of first high-priority interrupt (always 2) */
#define XCHAL_EXCM_LEVEL		1			/* level of interrupts masked by PS.EXCM (XEA2 only; always 1 in T10xx);
								   for XEA1, where there is no PS.EXCM, this is always 1;
								   interrupts at levels FIRST_HIGHPRI <= n <= EXCM_LEVEL, if any,
								   are termed "medium priority" interrupts (post T10xx only) */
/*  Note:  1 <= LOWPRI_LEVELS <= EXCM_LEVEL < DEBUGLEVEL <= NUM_INTLEVELS < NMILEVEL <= 15  */

/*  Masks of interrupts at each interrupt level:  */
#define XCHAL_INTLEVEL0_MASK		0x00000000
#define XCHAL_INTLEVEL1_MASK		0x000064F9
#define XCHAL_INTLEVEL2_MASK		0x00008902
#define XCHAL_INTLEVEL3_MASK		0x00011204
#define XCHAL_INTLEVEL4_MASK		0x00000000
#define XCHAL_INTLEVEL5_MASK		0x00000000
#define XCHAL_INTLEVEL6_MASK		0x00000000
#define XCHAL_INTLEVEL7_MASK		0x00000000
#define XCHAL_INTLEVEL8_MASK		0x00000000
#define XCHAL_INTLEVEL9_MASK		0x00000000
#define XCHAL_INTLEVEL10_MASK		0x00000000
#define XCHAL_INTLEVEL11_MASK		0x00000000
#define XCHAL_INTLEVEL12_MASK		0x00000000
#define XCHAL_INTLEVEL13_MASK		0x00000000
#define XCHAL_INTLEVEL14_MASK		0x00000000
#define XCHAL_INTLEVEL15_MASK		0x00000000
/*  As an array of entries (eg. for C constant arrays):  */
#define XCHAL_INTLEVEL_MASKS		0x00000000	XCHAL_SEP \
					0x000064F9	XCHAL_SEP \
					0x00008902	XCHAL_SEP \
					0x00011204	XCHAL_SEP \
					0x00000000	XCHAL_SEP \
					0x00000000	XCHAL_SEP \
					0x00000000	XCHAL_SEP \
					0x00000000	XCHAL_SEP \
					0x00000000	XCHAL_SEP \
					0x00000000	XCHAL_SEP \
					0x00000000	XCHAL_SEP \
					0x00000000	XCHAL_SEP \
					0x00000000	XCHAL_SEP \
					0x00000000	XCHAL_SEP \
					0x00000000	XCHAL_SEP \
					0x00000000

/*  Masks of interrupts at each range 1..n of interrupt levels:  */
#define XCHAL_INTLEVEL0_ANDBELOW_MASK	0x00000000
#define XCHAL_INTLEVEL1_ANDBELOW_MASK	0x000064F9
#define XCHAL_INTLEVEL2_ANDBELOW_MASK	0x0000EDFB
#define XCHAL_INTLEVEL3_ANDBELOW_MASK	0x0001FFFF
#define XCHAL_INTLEVEL4_ANDBELOW_MASK	0x0001FFFF
#define XCHAL_INTLEVEL5_ANDBELOW_MASK	0x0001FFFF
#define XCHAL_INTLEVEL6_ANDBELOW_MASK	0x0001FFFF
#define XCHAL_INTLEVEL7_ANDBELOW_MASK	0x0001FFFF
#define XCHAL_INTLEVEL8_ANDBELOW_MASK	0x0001FFFF
#define XCHAL_INTLEVEL9_ANDBELOW_MASK	0x0001FFFF
#define XCHAL_INTLEVEL10_ANDBELOW_MASK	0x0001FFFF
#define XCHAL_INTLEVEL11_ANDBELOW_MASK	0x0001FFFF
#define XCHAL_INTLEVEL12_ANDBELOW_MASK	0x0001FFFF
#define XCHAL_INTLEVEL13_ANDBELOW_MASK	0x0001FFFF
#define XCHAL_INTLEVEL14_ANDBELOW_MASK	0x0001FFFF
#define XCHAL_INTLEVEL15_ANDBELOW_MASK	0x0001FFFF
#define XCHAL_LOWPRI_MASK		XCHAL_INTLEVEL1_ANDBELOW_MASK	/* mask of all low-priority interrupts */
#define XCHAL_EXCM_MASK			XCHAL_INTLEVEL1_ANDBELOW_MASK	/* mask of all interrupts masked by PS.EXCM (or CEXCM) */
/*  As an array of entries (eg. for C constant arrays):  */
#define XCHAL_INTLEVEL_ANDBELOW_MASKS	0x00000000	XCHAL_SEP \
					0x000064F9	XCHAL_SEP \
					0x0000EDFB	XCHAL_SEP \
					0x0001FFFF	XCHAL_SEP \
					0x0001FFFF	XCHAL_SEP \
					0x0001FFFF	XCHAL_SEP \
					0x0001FFFF	XCHAL_SEP \
					0x0001FFFF	XCHAL_SEP \
					0x0001FFFF	XCHAL_SEP \
					0x0001FFFF	XCHAL_SEP \
					0x0001FFFF	XCHAL_SEP \
					0x0001FFFF	XCHAL_SEP \
					0x0001FFFF	XCHAL_SEP \
					0x0001FFFF	XCHAL_SEP \
					0x0001FFFF	XCHAL_SEP \
					0x0001FFFF

/*  Interrupt numbers for each interrupt level at which only one interrupt was configured:  */
/*#define XCHAL_INTLEVEL1_NUM		...more than one interrupt at this level...*/
/*#define XCHAL_INTLEVEL2_NUM		...more than one interrupt at this level...*/
/*#define XCHAL_INTLEVEL3_NUM		...more than one interrupt at this level...*/

/*  Level of each interrupt:  */
#define XCHAL_INT0_LEVEL		1
#define XCHAL_INT1_LEVEL		2
#define XCHAL_INT2_LEVEL		3
#define XCHAL_INT3_LEVEL		1
#define XCHAL_INT4_LEVEL		1
#define XCHAL_INT5_LEVEL		1
#define XCHAL_INT6_LEVEL		1
#define XCHAL_INT7_LEVEL		1
#define XCHAL_INT8_LEVEL		2
#define XCHAL_INT9_LEVEL		3
#define XCHAL_INT10_LEVEL		1
#define XCHAL_INT11_LEVEL		2
#define XCHAL_INT12_LEVEL		3
#define XCHAL_INT13_LEVEL		1
#define XCHAL_INT14_LEVEL		1
#define XCHAL_INT15_LEVEL		2
#define XCHAL_INT16_LEVEL		3
#define XCHAL_INT17_LEVEL		0
#define XCHAL_INT18_LEVEL		0
#define XCHAL_INT19_LEVEL		0
#define XCHAL_INT20_LEVEL		0
#define XCHAL_INT21_LEVEL		0
#define XCHAL_INT22_LEVEL		0
#define XCHAL_INT23_LEVEL		0
#define XCHAL_INT24_LEVEL		0
#define XCHAL_INT25_LEVEL		0
#define XCHAL_INT26_LEVEL		0
#define XCHAL_INT27_LEVEL		0
#define XCHAL_INT28_LEVEL		0
#define XCHAL_INT29_LEVEL		0
#define XCHAL_INT30_LEVEL		0
#define XCHAL_INT31_LEVEL		0
/*  As an array of entries (eg. for C constant arrays):  */
#define XCHAL_INT_LEVELS		1	XCHAL_SEP \
					2	XCHAL_SEP \
					3	XCHAL_SEP \
					1	XCHAL_SEP \
					1	XCHAL_SEP \
					1	XCHAL_SEP \
					1	XCHAL_SEP \
					1	XCHAL_SEP \
					2	XCHAL_SEP \
					3	XCHAL_SEP \
					1	XCHAL_SEP \
					2	XCHAL_SEP \
					3	XCHAL_SEP \
					1	XCHAL_SEP \
					1	XCHAL_SEP \
					2	XCHAL_SEP \
					3	XCHAL_SEP \
					0	XCHAL_SEP \
					0	XCHAL_SEP \
					0	XCHAL_SEP \
					0	XCHAL_SEP \
					0	XCHAL_SEP \
					0	XCHAL_SEP \
					0	XCHAL_SEP \