📄 tx4938.h
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/* * linux/include/asm-mips/tx4938/tx4938.h * Definitions for TX4937/TX4938 * Copyright (C) 2000-2001 Toshiba Corporation * * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the * terms of the GNU General Public License version 2. This program is * licensed "as is" without any warranty of any kind, whether express * or implied. * * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) */#ifndef __ASM_TX_BOARDS_TX4938_H#define __ASM_TX_BOARDS_TX4938_H#include <asm/tx4938/tx4938_mips.h>#define tx4938_read_nfmc(addr) (*(volatile unsigned int *)(addr))#define tx4938_write_nfmc(b,addr) (*(volatile unsigned int *)(addr)) = (b)#define TX4938_NR_IRQ_LOCAL TX4938_IRQ_PIC_BEG#define TX4938_IRQ_IRC_PCIC (TX4938_NR_IRQ_LOCAL + TX4938_IR_PCIC)#define TX4938_IRQ_IRC_PCIERR (TX4938_NR_IRQ_LOCAL + TX4938_IR_PCIERR)#define TX4938_PCIIO_0 0x10000000#define TX4938_PCIIO_1 0x01010000#define TX4938_PCIMEM_0 0x08000000#define TX4938_PCIMEM_1 0x11000000#define TX4938_PCIIO_SIZE_0 0x01000000#define TX4938_PCIIO_SIZE_1 0x00010000#define TX4938_PCIMEM_SIZE_0 0x08000000#define TX4938_PCIMEM_SIZE_1 0x00010000#define TX4938_REG_BASE 0xff1f0000 /* == TX4937_REG_BASE */#define TX4938_REG_SIZE 0x00010000 /* == TX4937_REG_SIZE *//* NDFMC, SRAMC, PCIC1, SPIC: TX4938 only */#define TX4938_NDFMC_REG (TX4938_REG_BASE + 0x5000)#define TX4938_SRAMC_REG (TX4938_REG_BASE + 0x6000)#define TX4938_PCIC1_REG (TX4938_REG_BASE + 0x7000)#define TX4938_SDRAMC_REG (TX4938_REG_BASE + 0x8000)#define TX4938_EBUSC_REG (TX4938_REG_BASE + 0x9000)#define TX4938_DMA_REG(ch) (TX4938_REG_BASE + 0xb000 + (ch) * 0x800)#define TX4938_PCIC_REG (TX4938_REG_BASE + 0xd000)#define TX4938_CCFG_REG (TX4938_REG_BASE + 0xe000)#define TX4938_NR_TMR 3#define TX4938_TMR_REG(ch) ((TX4938_REG_BASE + 0xf000) + (ch) * 0x100)#define TX4938_NR_SIO 2#define TX4938_SIO_REG(ch) ((TX4938_REG_BASE + 0xf300) + (ch) * 0x100)#define TX4938_PIO_REG (TX4938_REG_BASE + 0xf500)#define TX4938_IRC_REG (TX4938_REG_BASE + 0xf600)#define TX4938_ACLC_REG (TX4938_REG_BASE + 0xf700)#define TX4938_SPI_REG (TX4938_REG_BASE + 0xf800)#ifndef _LANGUAGE_ASSEMBLY#include <asm/byteorder.h>#define TX4938_MKA(x) ((u32)( ((u32)(TX4938_REG_BASE)) | ((u32)(x)) ))#define TX4938_RD08( reg ) (*(vu08*)(reg))#define TX4938_WR08( reg, val ) ((*(vu08*)(reg))=(val))#define TX4938_RD16( reg ) (*(vu16*)(reg))#define TX4938_WR16( reg, val ) ((*(vu16*)(reg))=(val))#define TX4938_RD32( reg ) (*(vu32*)(reg))#define TX4938_WR32( reg, val ) ((*(vu32*)(reg))=(val))#define TX4938_RD64( reg ) (*(vu64*)(reg))#define TX4938_WR64( reg, val ) ((*(vu64*)(reg))=(val))#define TX4938_RD( reg ) TX4938_RD32( reg )#define TX4938_WR( reg, val ) TX4938_WR32( reg, val )#endif /* !__ASSEMBLY__ */#ifdef __ASSEMBLY__#define _CONST64(c) c#else#define _CONST64(c) c##ull#include <asm/byteorder.h>#ifdef __BIG_ENDIAN#define endian_def_l2(e1,e2) \ volatile unsigned long e1,e2#define endian_def_s2(e1,e2) \ volatile unsigned short e1,e2#define endian_def_sb2(e1,e2,e3) \ volatile unsigned short e1;volatile unsigned char e2,e3#define endian_def_b2s(e1,e2,e3) \ volatile unsigned char e1,e2;volatile unsigned short e3#define endian_def_b4(e1,e2,e3,e4) \ volatile unsigned char e1,e2,e3,e4#else#define endian_def_l2(e1,e2) \ volatile unsigned long e2,e1#define endian_def_s2(e1,e2) \ volatile unsigned short e2,e1#define endian_def_sb2(e1,e2,e3) \ volatile unsigned char e3,e2;volatile unsigned short e1#define endian_def_b2s(e1,e2,e3) \ volatile unsigned short e3;volatile unsigned char e2,e1#define endian_def_b4(e1,e2,e3,e4) \ volatile unsigned char e4,e3,e2,e1#endifstruct tx4938_sdramc_reg { volatile unsigned long long cr[4]; volatile unsigned long long unused0[4]; volatile unsigned long long tr; volatile unsigned long long unused1[2]; volatile unsigned long long cmd; volatile unsigned long long sfcmd;};struct tx4938_ebusc_reg { volatile unsigned long long cr[8];};struct tx4938_dma_reg { struct tx4938_dma_ch_reg { volatile unsigned long long cha; volatile unsigned long long sar; volatile unsigned long long dar; endian_def_l2(unused0, cntr); endian_def_l2(unused1, sair); endian_def_l2(unused2, dair); endian_def_l2(unused3, ccr); endian_def_l2(unused4, csr); } ch[4]; volatile unsigned long long dbr[8]; volatile unsigned long long tdhr; volatile unsigned long long midr; endian_def_l2(unused0, mcr);};struct tx4938_pcic_reg { volatile unsigned long pciid; volatile unsigned long pcistatus; volatile unsigned long pciccrev; volatile unsigned long pcicfg1; volatile unsigned long p2gm0plbase; /* +10 */ volatile unsigned long p2gm0pubase; volatile unsigned long p2gm1plbase; volatile unsigned long p2gm1pubase; volatile unsigned long p2gm2pbase; /* +20 */ volatile unsigned long p2giopbase; volatile unsigned long unused0; volatile unsigned long pcisid; volatile unsigned long unused1; /* +30 */ volatile unsigned long pcicapptr; volatile unsigned long unused2; volatile unsigned long pcicfg2; volatile unsigned long g2ptocnt; /* +40 */ volatile unsigned long unused3[15]; volatile unsigned long g2pstatus; /* +80 */ volatile unsigned long g2pmask; volatile unsigned long pcisstatus; volatile unsigned long pcimask; volatile unsigned long p2gcfg; /* +90 */ volatile unsigned long p2gstatus; volatile unsigned long p2gmask; volatile unsigned long p2gccmd; volatile unsigned long unused4[24]; /* +a0 */ volatile unsigned long pbareqport; /* +100 */ volatile unsigned long pbacfg; volatile unsigned long pbastatus; volatile unsigned long pbamask; volatile unsigned long pbabm; /* +110 */ volatile unsigned long pbacreq; volatile unsigned long pbacgnt; volatile unsigned long pbacstate; volatile unsigned long long g2pmgbase[3]; /* +120 */ volatile unsigned long long g2piogbase; volatile unsigned long g2pmmask[3]; /* +140 */ volatile unsigned long g2piomask; volatile unsigned long long g2pmpbase[3]; /* +150 */ volatile unsigned long long g2piopbase; volatile unsigned long pciccfg; /* +170 */ volatile unsigned long pcicstatus; volatile unsigned long pcicmask; volatile unsigned long unused5; volatile unsigned long long p2gmgbase[3]; /* +180 */ volatile unsigned long long p2giogbase; volatile unsigned long g2pcfgadrs; /* +1a0 */ volatile unsigned long g2pcfgdata; volatile unsigned long unused6[8]; volatile unsigned long g2pintack; volatile unsigned long g2pspc; volatile unsigned long unused7[12]; /* +1d0 */ volatile unsigned long long pdmca; /* +200 */ volatile unsigned long long pdmga; volatile unsigned long long pdmpa; volatile unsigned long long pdmctr; volatile unsigned long long pdmcfg; /* +220 */ volatile unsigned long long pdmsts;};struct tx4938_aclc_reg { volatile unsigned long acctlen; volatile unsigned long acctldis; volatile unsigned long acregacc; volatile unsigned long unused0; volatile unsigned long acintsts; volatile unsigned long acintmsts; volatile unsigned long acinten; volatile unsigned long acintdis; volatile unsigned long acsemaph; volatile unsigned long unused1[7]; volatile unsigned long acgpidat; volatile unsigned long acgpodat; volatile unsigned long acslten; volatile unsigned long acsltdis; volatile unsigned long acfifosts; volatile unsigned long unused2[11]; volatile unsigned long acdmasts; volatile unsigned long acdmasel; volatile unsigned long unused3[6]; volatile unsigned long acaudodat; volatile unsigned long acsurrdat; volatile unsigned long accentdat; volatile unsigned long aclfedat; volatile unsigned long acaudiat; volatile unsigned long unused4; volatile unsigned long acmodoat; volatile unsigned long acmodidat; volatile unsigned long unused5[15]; volatile unsigned long acrevid;};struct tx4938_tmr_reg { volatile unsigned long tcr; volatile unsigned long tisr; volatile unsigned long cpra; volatile unsigned long cprb; volatile unsigned long itmr; volatile unsigned long unused0[3]; volatile unsigned long ccdr; volatile unsigned long unused1[3]; volatile unsigned long pgmr; volatile unsigned long unused2[3]; volatile unsigned long wtmr; volatile unsigned long unused3[43]; volatile unsigned long trr;};struct tx4938_sio_reg { volatile unsigned long lcr; volatile unsigned long dicr; volatile unsigned long disr; volatile unsigned long cisr; volatile unsigned long fcr; volatile unsigned long flcr; volatile unsigned long bgr; volatile unsigned long tfifo; volatile unsigned long rfifo;};struct tx4938_pio_reg { volatile unsigned long dout; volatile unsigned long din; volatile unsigned long dir; volatile unsigned long od; volatile unsigned long flag[2]; volatile unsigned long pol; volatile unsigned long intc; volatile unsigned long maskcpu; volatile unsigned long maskext;};struct tx4938_irc_reg { volatile unsigned long cer; volatile unsigned long cr[2]; volatile unsigned long unused0; volatile unsigned long ilr[8]; volatile unsigned long unused1[4]; volatile unsigned long imr; volatile unsigned long unused2[7]; volatile unsigned long scr; volatile unsigned long unused3[7]; volatile unsigned long ssr; volatile unsigned long unused4[7]; volatile unsigned long csr;};struct tx4938_ndfmc_reg { endian_def_l2(unused0, dtr); endian_def_l2(unused1, mcr); endian_def_l2(unused2, sr); endian_def_l2(unused3, isr); endian_def_l2(unused4, imr); endian_def_l2(unused5, spr); endian_def_l2(unused6, rstr);};struct tx4938_spi_reg { volatile unsigned long mcr; volatile unsigned long cr0; volatile unsigned long cr1; volatile unsigned long fs; volatile unsigned long unused1; volatile unsigned long sr; volatile unsigned long dr; volatile unsigned long unused2;};struct tx4938_sramc_reg { volatile unsigned long long cr;};struct tx4938_ccfg_reg { volatile unsigned long long ccfg; volatile unsigned long long crir; volatile unsigned long long pcfg; volatile unsigned long long tear; volatile unsigned long long clkctr; volatile unsigned long long unused0; volatile unsigned long long garbc; volatile unsigned long long unused1; volatile unsigned long long unused2; volatile unsigned long long ramp; volatile unsigned long long unused3; volatile unsigned long long jmpadr;};#undef endian_def_l2#undef endian_def_s2#undef endian_def_sb2#undef endian_def_b2s#undef endian_def_b4#endif /* __ASSEMBLY__ *//* * NDFMC *//* NDFMCR : NDFMC Mode Control */#define TX4938_NDFMCR_WE 0x80#define TX4938_NDFMCR_ECC_ALL 0x60#define TX4938_NDFMCR_ECC_RESET 0x60#define TX4938_NDFMCR_ECC_READ 0x40#define TX4938_NDFMCR_ECC_ON 0x20#define TX4938_NDFMCR_ECC_OFF 0x00#define TX4938_NDFMCR_CE 0x10#define TX4938_NDFMCR_BSPRT 0x04#define TX4938_NDFMCR_ALE 0x02#define TX4938_NDFMCR_CLE 0x01/* NDFMCR : NDFMC Status */
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