📄 au1xxx_psc.h
字号:
PSC_I2SMSK_RU | PSC_I2SMSK_TR | \ PSC_I2SMSK_TO | PSC_I2SMSK_TU | \ PSC_I2SMSK_RD | PSC_I2SMSK_TD)/* I2S Protocol Control Register.*/#define PSC_I2SPCR_RC (1 << 6)#define PSC_I2SPCR_RP (1 << 5)#define PSC_I2SPCR_RS (1 << 4)#define PSC_I2SPCR_TC (1 << 2)#define PSC_I2SPCR_TP (1 << 1)#define PSC_I2SPCR_TS (1 << 0)/* I2S Status register (read only).*/#define PSC_I2SSTAT_RF (1 << 13)#define PSC_I2SSTAT_RE (1 << 12)#define PSC_I2SSTAT_RR (1 << 11)#define PSC_I2SSTAT_TF (1 << 10)#define PSC_I2SSTAT_TE (1 << 9)#define PSC_I2SSTAT_TR (1 << 8)#define PSC_I2SSTAT_RB (1 << 5)#define PSC_I2SSTAT_TB (1 << 4)#define PSC_I2SSTAT_DI (1 << 2)#define PSC_I2SSTAT_DR (1 << 1)#define PSC_I2SSTAT_SR (1 << 0)/* I2S Event Register.*/#define PSC_I2SEVNT_RR (1 << 13)#define PSC_I2SEVNT_RO (1 << 12)#define PSC_I2SEVNT_RU (1 << 11)#define PSC_I2SEVNT_TR (1 << 10)#define PSC_I2SEVNT_TO (1 << 9)#define PSC_I2SEVNT_TU (1 << 8)#define PSC_I2SEVNT_RD (1 << 5)#define PSC_I2SEVNT_TD (1 << 4)/* PSC in SPI Mode.*/typedef struct psc_spi { u32 psc_sel; u32 psc_ctrl; u32 psc_spicfg; u32 psc_spimsk; u32 psc_spipcr; u32 psc_spistat; u32 psc_spievent; u32 psc_spitxrx;} psc_spi_t;/* SPI Config Register.*/#define PSC_SPICFG_RT_MASK (3 << 30)#define PSC_SPICFG_RT_FIFO1 (0 << 30)#define PSC_SPICFG_RT_FIFO2 (1 << 30)#define PSC_SPICFG_RT_FIFO4 (2 << 30)#define PSC_SPICFG_RT_FIFO8 (3 << 30)#define PSC_SPICFG_TT_MASK (3 << 28)#define PSC_SPICFG_TT_FIFO1 (0 << 28)#define PSC_SPICFG_TT_FIFO2 (1 << 28)#define PSC_SPICFG_TT_FIFO4 (2 << 28)#define PSC_SPICFG_TT_FIFO8 (3 << 28)#define PSC_SPICFG_DD_DISABLE (1 << 27)#define PSC_SPICFG_DE_ENABLE (1 << 26)#define PSC_SPICFG_CLR_BAUD(x) ((x) & ~((0x3f) << 15))#define PSC_SPICFG_SET_BAUD(x) (((x) & 0x3f) << 15)#define PSC_SPICFG_SET_DIV(x) (((x) & 0x03) << 13)#define PSC_SPICFG_DIV2 0#define PSC_SPICFG_DIV4 1#define PSC_SPICFG_DIV8 2#define PSC_SPICFG_DIV16 3#define PSC_SPICFG_BI (1 << 12)#define PSC_SPICFG_PSE (1 << 11)#define PSC_SPICFG_CGE (1 << 10)#define PSC_SPICFG_CDE (1 << 9)#define PSC_SPICFG_CLR_LEN(x) ((x) & ~((0x1f) << 4))#define PSC_SPICFG_SET_LEN(x) (((x-1) & 0x1f) << 4)#define PSC_SPICFG_LB (1 << 3)#define PSC_SPICFG_MLF (1 << 1)#define PSC_SPICFG_MO (1 << 0)/* SPI Mask Register.*/#define PSC_SPIMSK_MM (1 << 16)#define PSC_SPIMSK_RR (1 << 13)#define PSC_SPIMSK_RO (1 << 12)#define PSC_SPIMSK_RU (1 << 11)#define PSC_SPIMSK_TR (1 << 10)#define PSC_SPIMSK_TO (1 << 9)#define PSC_SPIMSK_TU (1 << 8)#define PSC_SPIMSK_SD (1 << 5)#define PSC_SPIMSK_MD (1 << 4)#define PSC_SPIMSK_ALLMASK (PSC_SPIMSK_MM | PSC_SPIMSK_RR | \ PSC_SPIMSK_RO | PSC_SPIMSK_TO | \ PSC_SPIMSK_TU | PSC_SPIMSK_SD | \ PSC_SPIMSK_MD)/* SPI Protocol Control Register.*/#define PSC_SPIPCR_RC (1 << 6)#define PSC_SPIPCR_SP (1 << 5)#define PSC_SPIPCR_SS (1 << 4)#define PSC_SPIPCR_TC (1 << 2)#define PSC_SPIPCR_MS (1 << 0)/* SPI Status register (read only).*/#define PSC_SPISTAT_RF (1 << 13)#define PSC_SPISTAT_RE (1 << 12)#define PSC_SPISTAT_RR (1 << 11)#define PSC_SPISTAT_TF (1 << 10)#define PSC_SPISTAT_TE (1 << 9)#define PSC_SPISTAT_TR (1 << 8)#define PSC_SPISTAT_SB (1 << 5)#define PSC_SPISTAT_MB (1 << 4)#define PSC_SPISTAT_DI (1 << 2)#define PSC_SPISTAT_DR (1 << 1)#define PSC_SPISTAT_SR (1 << 0)/* SPI Event Register.*/#define PSC_SPIEVNT_MM (1 << 16)#define PSC_SPIEVNT_RR (1 << 13)#define PSC_SPIEVNT_RO (1 << 12)#define PSC_SPIEVNT_RU (1 << 11)#define PSC_SPIEVNT_TR (1 << 10)#define PSC_SPIEVNT_TO (1 << 9)#define PSC_SPIEVNT_TU (1 << 8)#define PSC_SPIEVNT_SD (1 << 5)#define PSC_SPIEVNT_MD (1 << 4)/* Transmit register control.*/#define PSC_SPITXRX_LC (1 << 29)#define PSC_SPITXRX_SR (1 << 28)/* PSC in SMBus (I2C) Mode.*/typedef struct psc_smb { u32 psc_sel; u32 psc_ctrl; u32 psc_smbcfg; u32 psc_smbmsk; u32 psc_smbpcr; u32 psc_smbstat; u32 psc_smbevnt; u32 psc_smbtxrx; u32 psc_smbtmr;} psc_smb_t;/* SMBus Config Register.*/#define PSC_SMBCFG_RT_MASK (3 << 30)#define PSC_SMBCFG_RT_FIFO1 (0 << 30)#define PSC_SMBCFG_RT_FIFO2 (1 << 30)#define PSC_SMBCFG_RT_FIFO4 (2 << 30)#define PSC_SMBCFG_RT_FIFO8 (3 << 30)#define PSC_SMBCFG_TT_MASK (3 << 28)#define PSC_SMBCFG_TT_FIFO1 (0 << 28)#define PSC_SMBCFG_TT_FIFO2 (1 << 28)#define PSC_SMBCFG_TT_FIFO4 (2 << 28)#define PSC_SMBCFG_TT_FIFO8 (3 << 28)#define PSC_SMBCFG_DD_DISABLE (1 << 27)#define PSC_SMBCFG_DE_ENABLE (1 << 26)#define PSC_SMBCFG_SET_DIV(x) (((x) & 0x03) << 13)#define PSC_SMBCFG_DIV2 0#define PSC_SMBCFG_DIV4 1#define PSC_SMBCFG_DIV8 2#define PSC_SMBCFG_DIV16 3#define PSC_SMBCFG_GCE (1 << 9)#define PSC_SMBCFG_SFM (1 << 8)#define PSC_SMBCFG_SET_SLV(x) (((x) & 0x7f) << 1)/* SMBus Mask Register.*/#define PSC_SMBMSK_DN (1 << 30)#define PSC_SMBMSK_AN (1 << 29)#define PSC_SMBMSK_AL (1 << 28)#define PSC_SMBMSK_RR (1 << 13)#define PSC_SMBMSK_RO (1 << 12)#define PSC_SMBMSK_RU (1 << 11)#define PSC_SMBMSK_TR (1 << 10)#define PSC_SMBMSK_TO (1 << 9)#define PSC_SMBMSK_TU (1 << 8)#define PSC_SMBMSK_SD (1 << 5)#define PSC_SMBMSK_MD (1 << 4)#define PSC_SMBMSK_ALLMASK (PSC_SMBMSK_DN | PSC_SMBMSK_AN | \ PSC_SMBMSK_AL | PSC_SMBMSK_RR | \ PSC_SMBMSK_RO | PSC_SMBMSK_TO | \ PSC_SMBMSK_TU | PSC_SMBMSK_SD | \ PSC_SMBMSK_MD)/* SMBus Protocol Control Register.*/#define PSC_SMBPCR_DC (1 << 2)#define PSC_SMBPCR_MS (1 << 0)/* SMBus Status register (read only).*/#define PSC_SMBSTAT_BB (1 << 28)#define PSC_SMBSTAT_RF (1 << 13)#define PSC_SMBSTAT_RE (1 << 12)#define PSC_SMBSTAT_RR (1 << 11)#define PSC_SMBSTAT_TF (1 << 10)#define PSC_SMBSTAT_TE (1 << 9)#define PSC_SMBSTAT_TR (1 << 8)#define PSC_SMBSTAT_SB (1 << 5)#define PSC_SMBSTAT_MB (1 << 4)#define PSC_SMBSTAT_DI (1 << 2)#define PSC_SMBSTAT_DR (1 << 1)#define PSC_SMBSTAT_SR (1 << 0)/* SMBus Event Register.*/#define PSC_SMBEVNT_DN (1 << 30)#define PSC_SMBEVNT_AN (1 << 29)#define PSC_SMBEVNT_AL (1 << 28)#define PSC_SMBEVNT_RR (1 << 13)#define PSC_SMBEVNT_RO (1 << 12)#define PSC_SMBEVNT_RU (1 << 11)#define PSC_SMBEVNT_TR (1 << 10)#define PSC_SMBEVNT_TO (1 << 9)#define PSC_SMBEVNT_TU (1 << 8)#define PSC_SMBEVNT_SD (1 << 5)#define PSC_SMBEVNT_MD (1 << 4)#define PSC_SMBEVNT_ALLCLR (PSC_SMBEVNT_DN | PSC_SMBEVNT_AN | \ PSC_SMBEVNT_AL | PSC_SMBEVNT_RR | \ PSC_SMBEVNT_RO | PSC_SMBEVNT_TO | \ PSC_SMBEVNT_TU | PSC_SMBEVNT_SD | \ PSC_SMBEVNT_MD)/* Transmit register control.*/#define PSC_SMBTXRX_RSR (1 << 30)#define PSC_SMBTXRX_STP (1 << 29)#define PSC_SMBTXRX_DATAMASK (0xff)/* SMBus protocol timers register.*/#define PSC_SMBTMR_SET_TH(x) (((x) & 0x3) << 30)#define PSC_SMBTMR_SET_PS(x) (((x) & 0x1f) << 25)#define PSC_SMBTMR_SET_PU(x) (((x) & 0x1f) << 20)#define PSC_SMBTMR_SET_SH(x) (((x) & 0x1f) << 15)#define PSC_SMBTMR_SET_SU(x) (((x) & 0x1f) << 10)#define PSC_SMBTMR_SET_CL(x) (((x) & 0x1f) << 5)#define PSC_SMBTMR_SET_CH(x) (((x) & 0x1f) << 0)#endif /* _AU1000_PSC_H_ */⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -