📄 au1000.h
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#define SYS_PF_U3 (1<<14) /* GPIO23/U3TXD */ #define SYS_PF_U2 (1<<13) /* GPIO22/U2TXD */ #define SYS_PF_U1 (1<<12) /* GPIO21/U1TXD */ #define SYS_PF_SRC (1<<11) /* GPIO6/SROMCKE */ #define SYS_PF_CK5 (1<<10) /* GPIO3/CLK5 */ #define SYS_PF_CK4 (1<<9) /* GPIO2/CLK4 */ #define SYS_PF_IRF (1<<8) /* GPIO15/IRFIRSEL */ #define SYS_PF_UR3 (1<<7) /* GPIO[14:9]/UART3 */ #define SYS_PF_I2D (1<<6) /* GPIO8/I2SDI */ #define SYS_PF_I2S (1<<5) /* I2S/GPIO[29:31] */ #define SYS_PF_NI2 (1<<4) /* NI2/GPIO[24:28] */ #define SYS_PF_U0 (1<<3) /* U0TXD/GPIO20 */ #define SYS_PF_RD (1<<2) /* IRTXD/GPIO19 */ #define SYS_PF_A97 (1<<1) /* AC97/SSL1 */ #define SYS_PF_S0 (1<<0) /* SSI_0/GPIO[16:18] *//* Au1100 Only */ #define SYS_PF_PC (1<<18) /* PCMCIA/GPIO[207:204] */ #define SYS_PF_LCD (1<<17) /* extern lcd/GPIO[203:200] */ #define SYS_PF_CS (1<<16) /* EXTCLK0/32khz to gpio2 */ #define SYS_PF_EX0 (1<<9) /* gpio2/clock *//* Au1550 Only. Redefines lots of pins */ #define SYS_PF_PSC2_MASK (7 << 17) #define SYS_PF_PSC2_AC97 (0) #define SYS_PF_PSC2_SPI (0) #define SYS_PF_PSC2_I2S (1 << 17) #define SYS_PF_PSC2_SMBUS (3 << 17) #define SYS_PF_PSC2_GPIO (7 << 17) #define SYS_PF_PSC3_MASK (7 << 20) #define SYS_PF_PSC3_AC97 (0) #define SYS_PF_PSC3_SPI (0) #define SYS_PF_PSC3_I2S (1 << 20) #define SYS_PF_PSC3_SMBUS (3 << 20) #define SYS_PF_PSC3_GPIO (7 << 20) #define SYS_PF_PSC1_S1 (1 << 1) #define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2))/* Au1200 Only */#ifdef CONFIG_SOC_AU1200#define SYS_PINFUNC_DMA (1<<31)#define SYS_PINFUNC_S0A (1<<30)#define SYS_PINFUNC_S1A (1<<29)#define SYS_PINFUNC_LP0 (1<<28)#define SYS_PINFUNC_LP1 (1<<27)#define SYS_PINFUNC_LD16 (1<<26)#define SYS_PINFUNC_LD8 (1<<25)#define SYS_PINFUNC_LD1 (1<<24)#define SYS_PINFUNC_LD0 (1<<23)#define SYS_PINFUNC_P1A (3<<21)#define SYS_PINFUNC_P1B (1<<20)#define SYS_PINFUNC_FS3 (1<<19)#define SYS_PINFUNC_P0A (3<<17)#define SYS_PINFUNC_CS (1<<16)#define SYS_PINFUNC_CIM (1<<15)#define SYS_PINFUNC_P1C (1<<14)#define SYS_PINFUNC_U1T (1<<12)#define SYS_PINFUNC_U1R (1<<11)#define SYS_PINFUNC_EX1 (1<<10)#define SYS_PINFUNC_EX0 (1<<9)#define SYS_PINFUNC_U0R (1<<8)#define SYS_PINFUNC_MC (1<<7)#define SYS_PINFUNC_S0B (1<<6)#define SYS_PINFUNC_S0C (1<<5)#define SYS_PINFUNC_P0B (1<<4)#define SYS_PINFUNC_U0T (1<<3)#define SYS_PINFUNC_S1B (1<<2)#endif#define SYS_TRIOUTRD 0xB1900100#define SYS_TRIOUTCLR 0xB1900100#define SYS_OUTPUTRD 0xB1900108#define SYS_OUTPUTSET 0xB1900108#define SYS_OUTPUTCLR 0xB190010C#define SYS_PINSTATERD 0xB1900110#define SYS_PININPUTEN 0xB1900110/* GPIO2, Au1500, Au1550 only */#define GPIO2_BASE 0xB1700000#define GPIO2_DIR (GPIO2_BASE + 0)#define GPIO2_OUTPUT (GPIO2_BASE + 8)#define GPIO2_PINSTATE (GPIO2_BASE + 0xC)#define GPIO2_INTENABLE (GPIO2_BASE + 0x10)#define GPIO2_ENABLE (GPIO2_BASE + 0x14)/* Power Management */#define SYS_SCRATCH0 0xB1900018#define SYS_SCRATCH1 0xB190001C#define SYS_WAKEMSK 0xB1900034#define SYS_ENDIAN 0xB1900038#define SYS_POWERCTRL 0xB190003C#define SYS_WAKESRC 0xB190005C#define SYS_SLPPWR 0xB1900078#define SYS_SLEEP 0xB190007C/* Clock Controller */#define SYS_FREQCTRL0 0xB1900020 #define SYS_FC_FRDIV2_BIT 22 #define SYS_FC_FRDIV2_MASK (0xff << SYS_FC_FRDIV2_BIT) #define SYS_FC_FE2 (1<<21) #define SYS_FC_FS2 (1<<20) #define SYS_FC_FRDIV1_BIT 12 #define SYS_FC_FRDIV1_MASK (0xff << SYS_FC_FRDIV1_BIT) #define SYS_FC_FE1 (1<<11) #define SYS_FC_FS1 (1<<10) #define SYS_FC_FRDIV0_BIT 2 #define SYS_FC_FRDIV0_MASK (0xff << SYS_FC_FRDIV0_BIT) #define SYS_FC_FE0 (1<<1) #define SYS_FC_FS0 (1<<0)#define SYS_FREQCTRL1 0xB1900024 #define SYS_FC_FRDIV5_BIT 22 #define SYS_FC_FRDIV5_MASK (0xff << SYS_FC_FRDIV5_BIT) #define SYS_FC_FE5 (1<<21) #define SYS_FC_FS5 (1<<20) #define SYS_FC_FRDIV4_BIT 12 #define SYS_FC_FRDIV4_MASK (0xff << SYS_FC_FRDIV4_BIT) #define SYS_FC_FE4 (1<<11) #define SYS_FC_FS4 (1<<10) #define SYS_FC_FRDIV3_BIT 2 #define SYS_FC_FRDIV3_MASK (0xff << SYS_FC_FRDIV3_BIT) #define SYS_FC_FE3 (1<<1) #define SYS_FC_FS3 (1<<0)#define SYS_CLKSRC 0xB1900028 #define SYS_CS_ME1_BIT 27 #define SYS_CS_ME1_MASK (0x7<<SYS_CS_ME1_BIT) #define SYS_CS_DE1 (1<<26) #define SYS_CS_CE1 (1<<25) #define SYS_CS_ME0_BIT 22 #define SYS_CS_ME0_MASK (0x7<<SYS_CS_ME0_BIT) #define SYS_CS_DE0 (1<<21) #define SYS_CS_CE0 (1<<20) #define SYS_CS_MI2_BIT 17 #define SYS_CS_MI2_MASK (0x7<<SYS_CS_MI2_BIT) #define SYS_CS_DI2 (1<<16) #define SYS_CS_CI2 (1<<15)#ifdef CONFIG_SOC_AU1100 #define SYS_CS_ML_BIT 7 #define SYS_CS_ML_MASK (0x7<<SYS_CS_ML_BIT) #define SYS_CS_DL (1<<6) #define SYS_CS_CL (1<<5)#else #define SYS_CS_MUH_BIT 12 #define SYS_CS_MUH_MASK (0x7<<SYS_CS_MUH_BIT) #define SYS_CS_DUH (1<<11) #define SYS_CS_CUH (1<<10) #define SYS_CS_MUD_BIT 7 #define SYS_CS_MUD_MASK (0x7<<SYS_CS_MUD_BIT) #define SYS_CS_DUD (1<<6) #define SYS_CS_CUD (1<<5)#endif #define SYS_CS_MIR_BIT 2 #define SYS_CS_MIR_MASK (0x7<<SYS_CS_MIR_BIT) #define SYS_CS_DIR (1<<1) #define SYS_CS_CIR (1<<0) #define SYS_CS_MUX_AUX 0x1 #define SYS_CS_MUX_FQ0 0x2 #define SYS_CS_MUX_FQ1 0x3 #define SYS_CS_MUX_FQ2 0x4 #define SYS_CS_MUX_FQ3 0x5 #define SYS_CS_MUX_FQ4 0x6 #define SYS_CS_MUX_FQ5 0x7#define SYS_CPUPLL 0xB1900060#define SYS_AUXPLL 0xB1900064/* AC97 Controller */#define AC97C_CONFIG 0xB0000000 #define AC97C_RECV_SLOTS_BIT 13 #define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT) #define AC97C_XMIT_SLOTS_BIT 3 #define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT) #define AC97C_SG (1<<2) #define AC97C_SYNC (1<<1) #define AC97C_RESET (1<<0)#define AC97C_STATUS 0xB0000004 #define AC97C_XU (1<<11) #define AC97C_XO (1<<10) #define AC97C_RU (1<<9) #define AC97C_RO (1<<8) #define AC97C_READY (1<<7) #define AC97C_CP (1<<6) #define AC97C_TR (1<<5) #define AC97C_TE (1<<4) #define AC97C_TF (1<<3) #define AC97C_RR (1<<2) #define AC97C_RE (1<<1) #define AC97C_RF (1<<0)#define AC97C_DATA 0xB0000008#define AC97C_CMD 0xB000000C #define AC97C_WD_BIT 16 #define AC97C_READ (1<<7) #define AC97C_INDEX_MASK 0x7f#define AC97C_CNTRL 0xB0000010 #define AC97C_RS (1<<1) #define AC97C_CE (1<<0)/* Secure Digital (SD) Controller */#define SD0_XMIT_FIFO 0xB0600000#define SD0_RECV_FIFO 0xB0600004#define SD1_XMIT_FIFO 0xB0680000#define SD1_RECV_FIFO 0xB0680004#if defined (CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)/* Au1500 PCI Controller */#define Au1500_CFG_BASE 0xB4005000 // virtual, kseg0 addr#define Au1500_PCI_CMEM (Au1500_CFG_BASE + 0)#define Au1500_PCI_CFG (Au1500_CFG_BASE + 4) #define PCI_ERROR ((1<<22) | (1<<23) | (1<<24) | (1<<25) | (1<<26) | (1<<27))#define Au1500_PCI_B2BMASK_CCH (Au1500_CFG_BASE + 8)#define Au1500_PCI_B2B0_VID (Au1500_CFG_BASE + 0xC)#define Au1500_PCI_B2B1_ID (Au1500_CFG_BASE + 0x10)#define Au1500_PCI_MWMASK_DEV (Au1500_CFG_BASE + 0x14)#define Au1500_PCI_MWBASE_REV_CCL (Au1500_CFG_BASE + 0x18)#define Au1500_PCI_ERR_ADDR (Au1500_CFG_BASE + 0x1C)#define Au1500_PCI_SPEC_INTACK (Au1500_CFG_BASE + 0x20)#define Au1500_PCI_ID (Au1500_CFG_BASE + 0x100)#define Au1500_PCI_STATCMD (Au1500_CFG_BASE + 0x104)#define Au1500_PCI_CLASSREV (Au1500_CFG_BASE + 0x108)#define Au1500_PCI_HDRTYPE (Au1500_CFG_BASE + 0x10C)#define Au1500_PCI_MBAR (Au1500_CFG_BASE + 0x110)#define Au1500_PCI_HDR 0xB4005100 // virtual, kseg0 addr/* All of our structures, like pci resource, have 32 bit members. * Drivers are expected to do an ioremap on the PCI MEM resource, but it's * hard to store 0x4 0000 0000 in a 32 bit type. We require a small patch * to __ioremap to check for addresses between (u32)Au1500_PCI_MEM_START and * (u32)Au1500_PCI_MEM_END and change those to the full 36 bit PCI MEM * addresses. For PCI IO, it's simpler because we get to do the ioremap * ourselves and then adjust the device's resources. */#define Au1500_EXT_CFG 0x600000000ULL#define Au1500_EXT_CFG_TYPE1 0x680000000ULL#define Au1500_PCI_IO_START 0x500000000ULL#define Au1500_PCI_IO_END 0x5000FFFFFULL#define Au1500_PCI_MEM_START 0x440000000ULL#define Au1500_PCI_MEM_END 0x44FFFFFFFULL#define PCI_IO_START (Au1500_PCI_IO_START + 0x1000)#define PCI_IO_END (Au1500_PCI_IO_END)#define PCI_MEM_START (Au1500_PCI_MEM_START)#define PCI_MEM_END (Au1500_PCI_MEM_END)#define PCI_FIRST_DEVFN (0<<3)#define PCI_LAST_DEVFN (19<<3)#define IOPORT_RESOURCE_START 0x00001000 /* skip legacy probing */#define IOPORT_RESOURCE_END 0xffffffff#define IOMEM_RESOURCE_START 0x10000000#define IOMEM_RESOURCE_END 0xffffffff /* * Borrowed from the PPC arch: * The following macro is used to lookup irqs in a standard table * format for those PPC systems that do not already have PCI * interrupts properly routed. */ /* FIXME - double check this from asm-ppc/pci-bridge.h */#define PCI_IRQ_TABLE_LOOKUP \ ({ long _ctl_ = -1; \ if (idsel >= min_idsel && idsel <= max_idsel && pin <= irqs_per_slot) \ _ctl_ = pci_irq_table[idsel - min_idsel][pin-1]; \ _ctl_; })#else /* Au1000 and Au1100 and Au1200 *//* don't allow any legacy ports probing */#define IOPORT_RESOURCE_START 0x10000000#define IOPORT_RESOURCE_END 0xffffffff#define IOMEM_RESOURCE_START 0x10000000#define IOMEM_RESOURCE_END 0xffffffff#define PCI_IO_START 0#define PCI_IO_END 0#define PCI_MEM_START 0#define PCI_MEM_END 0#define PCI_FIRST_DEVFN 0#define PCI_LAST_DEVFN 0#endif#ifndef _LANGUAGE_ASSEMBLYtypedef volatile struct{ /* 0x0000 */ u32 toytrim; /* 0x0004 */ u32 toywrite; /* 0x0008 */ u32 toymatch0; /* 0x000C */ u32 toymatch1; /* 0x0010 */ u32 toymatch2; /* 0x0014 */ u32 cntrctrl; /* 0x0018 */ u32 scratch0; /* 0x001C */ u32 scratch1; /* 0x0020 */ u32 freqctrl0; /* 0x0024 */ u32 freqctrl1; /* 0x0028 */ u32 clksrc; /* 0x002C */ u32 pinfunc; /* 0x0030 */ u32 reserved0; /* 0x0034 */ u32 wakemsk; /* 0x0038 */ u32 endian; /* 0x003C */ u32 powerctrl; /* 0x0040 */ u32 toyread; /* 0x0044 */ u32 rtctrim; /* 0x0048 */ u32 rtcwrite; /* 0x004C */ u32 rtcmatch0; /* 0x0050 */ u32 rtcmatch1; /* 0x0054 */ u32 rtcmatch2; /* 0x0058 */ u32 rtcread; /* 0x005C */ u32 wakesrc; /* 0x0060 */ u32 cpupll; /* 0x0064 */ u32 auxpll; /* 0x0068 */ u32 reserved1; /* 0x006C */ u32 reserved2; /* 0x0070 */ u32 reserved3; /* 0x0074 */ u32 reserved4; /* 0x0078 */ u32 slppwr; /* 0x007C */ u32 sleep; /* 0x0080 */ u32 reserved5[32]; /* 0x0100 */ u32 trioutrd;#define trioutclr trioutrd /* 0x0104 */ u32 reserved6; /* 0x0108 */ u32 outputrd;#define outputset outputrd /* 0x010C */ u32 outputclr; /* 0x0110 */ u32 pinstaterd;#define pininputen pinstaterd} AU1X00_SYS;static AU1X00_SYS* const sys = (AU1X00_SYS *)SYS_BASE;#endif/* Processor information base on prid. * Copied from PowerPC. */#ifndef _LANGUAGE_ASSEMBLYstruct cpu_spec { /* CPU is matched via (PRID & prid_mask) == prid_value */ unsigned int prid_mask; unsigned int prid_value; char *cpu_name; unsigned char cpu_od; /* Set Config[OD] */ unsigned char cpu_bclk; /* Enable BCLK switching */};extern struct cpu_spec cpu_specs[];extern struct cpu_spec *cur_cpu_spec[];#endif#endif⌨️ 快捷键说明
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