📄 hubpi.h
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PI_ERR_SYSCMD_ADDR_B | \ PI_ERR_SYSCMD_DATA_B | \ PI_ERR_SYSAD_ADDR_B | \ PI_ERR_SYSAD_DATA_B | \ PI_ERR_SYSSTATE_B)#define PI_MISC_ERR_CPU_B (PI_ERR_UNCAC_UNCORR_B | \ PI_ERR_WRB_WERR_B | \ PI_ERR_WRB_TERR_B | \ PI_ERR_SPUR_MSG_B | \ PI_ERR_SPOOL_CMP_B)#define PI_ERR_GENERIC (PI_ERR_MD_UNCORR)/* * Error types for PI_ERR_STATUS0_[AB] and error stack: * Use the write types if WRBRRB is 1 else use the read types *//* Fields in PI_ERR_STATUS0_[AB] */#define PI_ERR_ST0_TYPE_MASK 0x0000000000000007#define PI_ERR_ST0_TYPE_SHFT 0#define PI_ERR_ST0_REQNUM_MASK 0x0000000000000038#define PI_ERR_ST0_REQNUM_SHFT 3#define PI_ERR_ST0_SUPPL_MASK 0x000000000001ffc0#define PI_ERR_ST0_SUPPL_SHFT 6#define PI_ERR_ST0_CMD_MASK 0x0000000001fe0000#define PI_ERR_ST0_CMD_SHFT 17#define PI_ERR_ST0_ADDR_MASK 0x3ffffffffe000000#define PI_ERR_ST0_ADDR_SHFT 25#define PI_ERR_ST0_OVERRUN_MASK 0x4000000000000000#define PI_ERR_ST0_OVERRUN_SHFT 62#define PI_ERR_ST0_VALID_MASK 0x8000000000000000#define PI_ERR_ST0_VALID_SHFT 63/* Fields in PI_ERR_STATUS1_[AB] */#define PI_ERR_ST1_SPOOL_MASK 0x00000000001fffff#define PI_ERR_ST1_SPOOL_SHFT 0#define PI_ERR_ST1_TOUTCNT_MASK 0x000000001fe00000#define PI_ERR_ST1_TOUTCNT_SHFT 21#define PI_ERR_ST1_INVCNT_MASK 0x0000007fe0000000#define PI_ERR_ST1_INVCNT_SHFT 29#define PI_ERR_ST1_CRBNUM_MASK 0x0000038000000000#define PI_ERR_ST1_CRBNUM_SHFT 39#define PI_ERR_ST1_WRBRRB_MASK 0x0000040000000000#define PI_ERR_ST1_WRBRRB_SHFT 42#define PI_ERR_ST1_CRBSTAT_MASK 0x001ff80000000000#define PI_ERR_ST1_CRBSTAT_SHFT 43#define PI_ERR_ST1_MSGSRC_MASK 0xffe0000000000000#define PI_ERR_ST1_MSGSRC_SHFT 53/* Fields in the error stack */#define PI_ERR_STK_TYPE_MASK 0x0000000000000003#define PI_ERR_STK_TYPE_SHFT 0#define PI_ERR_STK_SUPPL_MASK 0x0000000000000038#define PI_ERR_STK_SUPPL_SHFT 3#define PI_ERR_STK_REQNUM_MASK 0x00000000000001c0#define PI_ERR_STK_REQNUM_SHFT 6#define PI_ERR_STK_CRBNUM_MASK 0x0000000000000e00#define PI_ERR_STK_CRBNUM_SHFT 9#define PI_ERR_STK_WRBRRB_MASK 0x0000000000001000#define PI_ERR_STK_WRBRRB_SHFT 12#define PI_ERR_STK_CRBSTAT_MASK 0x00000000007fe000#define PI_ERR_STK_CRBSTAT_SHFT 13#define PI_ERR_STK_CMD_MASK 0x000000007f800000#define PI_ERR_STK_CMD_SHFT 23#define PI_ERR_STK_ADDR_MASK 0xffffffff80000000#define PI_ERR_STK_ADDR_SHFT 31/* Error type in the error status or stack on Read CRBs */#define PI_ERR_RD_PRERR 1#define PI_ERR_RD_DERR 2#define PI_ERR_RD_TERR 3/* Error type in the error status or stack on Write CRBs */#define PI_ERR_WR_WERR 0#define PI_ERR_WR_PWERR 1#define PI_ERR_WR_TERR 3/* Read or Write CRB in error status or stack */#define PI_ERR_RRB 0#define PI_ERR_WRB 1#define PI_ERR_ANY_CRB 2/* Address masks in the error status and error stack are not the same */#define ERR_STK_ADDR_SHFT 7#define ERR_STAT0_ADDR_SHFT 3#define PI_MIN_STACK_SIZE 4096 /* For figuring out the size to set */#define PI_STACK_SIZE_SHFT 12 /* 4k */#define ERR_STACK_SIZE_BYTES(_sz) \ ((_sz) ? (PI_MIN_STACK_SIZE << ((_sz) - 1)) : 0)#ifndef __ASSEMBLY__/* * format of error stack and error status registers. */struct err_stack_format { u64 sk_addr : 33, /* address */ sk_cmd : 8, /* message command */ sk_crb_sts : 10, /* status from RRB or WRB */ sk_rw_rb : 1, /* RRB == 0, WRB == 1 */ sk_crb_num : 3, /* WRB (0 to 7) or RRB (0 to 4) */ sk_t5_req : 3, /* RRB T5 request number */ sk_suppl : 3, /* lowest 3 bit of supplemental */ sk_err_type: 3; /* error type */};typedef union pi_err_stack { u64 pi_stk_word; struct err_stack_format pi_stk_fmt;} pi_err_stack_t;struct err_status0_format { u64 s0_valid : 1, /* Valid */ s0_ovr_run : 1, /* Overrun, spooled to memory */ s0_addr : 37, /* address */ s0_cmd : 8, /* message command */ s0_supl : 11, /* message supplemental field */ s0_t5_req : 3, /* RRB T5 request number */ s0_err_type: 3; /* error type */};typedef union pi_err_stat0 { u64 pi_stat0_word; struct err_status0_format pi_stat0_fmt;} pi_err_stat0_t;struct err_status1_format { u64 s1_src : 11, /* message source */ s1_crb_sts : 10, /* status from RRB or WRB */ s1_rw_rb : 1, /* RRB == 0, WRB == 1 */ s1_crb_num : 3, /* WRB (0 to 7) or RRB (0 to 4) */ s1_inval_cnt:10, /* signed invalidate counter RRB */ s1_to_cnt : 8, /* crb timeout counter */ s1_spl_cnt : 21; /* number spooled to memory */};typedef union pi_err_stat1 { u64 pi_stat1_word; struct err_status1_format pi_stat1_fmt;} pi_err_stat1_t;typedef u64 rtc_time_t;#endif /* !__ASSEMBLY__ *//* Bits in PI_SYSAD_ERRCHK_EN */#define PI_SYSAD_ERRCHK_ECCGEN 0x01 /* Enable ECC generation */#define PI_SYSAD_ERRCHK_QUALGEN 0x02 /* Enable data quality signal gen. */#define PI_SYSAD_ERRCHK_SADP 0x04 /* Enable SysAD parity checking */#define PI_SYSAD_ERRCHK_CMDP 0x08 /* Enable SysCmd parity checking */#define PI_SYSAD_ERRCHK_STATE 0x10 /* Enable SysState parity checking */#define PI_SYSAD_ERRCHK_QUAL 0x20 /* Enable data quality checking */#define PI_SYSAD_CHECK_ALL 0x3f /* Generate and check all signals. *//* Interrupt pending bits on R10000 */#define HUB_IP_PEND0 0x0400#define HUB_IP_PEND1_CC 0x0800#define HUB_IP_RT 0x1000#define HUB_IP_PROF 0x2000#define HUB_IP_ERROR 0x4000#define HUB_IP_MASK 0x7c00/* PI_RT_LOCAL_CTRL mask and shift definitions */#define PRLC_USE_INT_SHFT 16#define PRLC_USE_INT_MASK (UINT64_CAST 1 << 16)#define PRLC_USE_INT (UINT64_CAST 1 << 16)#define PRLC_GCLK_SHFT 15#define PRLC_GCLK_MASK (UINT64_CAST 1 << 15)#define PRLC_GCLK (UINT64_CAST 1 << 15)#define PRLC_GCLK_COUNT_SHFT 8#define PRLC_GCLK_COUNT_MASK (UINT64_CAST 0x7f << 8)#define PRLC_MAX_COUNT_SHFT 1#define PRLC_MAX_COUNT_MASK (UINT64_CAST 0x7f << 1)#define PRLC_GCLK_EN_SHFT 0#define PRLC_GCLK_EN_MASK (UINT64_CAST 1)#define PRLC_GCLK_EN (UINT64_CAST 1)/* PI_RT_FILTER_CTRL mask and shift definitions */#if 0/* * XXX - This register's definition has changed, but it's only implemented * in Hub 2. */#define PRFC_DROP_COUNT_SHFT 27#define PRFC_DROP_COUNT_MASK (UINT64_CAST 0x3ff << 27)#define PRFC_DROP_CTR_SHFT 18#define PRFC_DROP_CTR_MASK (UINT64_CAST 0x1ff << 18)#define PRFC_MASK_ENABLE_SHFT 10#define PRFC_MASK_ENABLE_MASK (UINT64_CAST 0x7f << 10)#define PRFC_MASK_CTR_SHFT 2#define PRFC_MASK_CTR_MASK (UINT64_CAST 0xff << 2)#define PRFC_OFFSET_SHFT 0#define PRFC_OFFSET_MASK (UINT64_CAST 3)#endif /* 0 *//* * Bits for NACK_CNT_A/B and NACK_CMP */#define PI_NACK_CNT_EN_SHFT 20#define PI_NACK_CNT_EN_MASK 0x100000#define PI_NACK_CNT_MASK 0x0fffff#define PI_NACK_CNT_MAX 0x0fffff#endif /* _ASM_SN_SN0_HUBPI_H */
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