bcm1480_regs.h

linux-2.6.15.6

#define R_BCM1480_PM_BASE_SIZE              0x0000000000
#define R_BCM1480_PM_CNT                    0x0000000008
#define R_BCM1480_PM_PFCNT                  0x0000000010
#define R_BCM1480_PM_LAST                   0x0000000018
#define R_BCM1480_PM_PFINDX                 0x0000000020
#define R_BCM1480_PM_INT_WMK                0x0000000028
#define R_BCM1480_PM_CONFIG0                0x0000000030
#define R_BCM1480_PM_LOCALDEBUG             0x0000000078
#define R_BCM1480_PM_CACHEABILITY           0x0000000080   /* PMI only */
#define R_BCM1480_PM_INT_CNFG               0x0000000088
#define R_BCM1480_PM_DESC_MERGE_TIMER       0x0000000090
#define R_BCM1480_PM_LOCALDEBUG_PIB         0x00000000F8   /* PMI only */
#define R_BCM1480_PM_LOCALDEBUG_POB         0x00000000F8   /* PMO only */

/*
 * Global Registers (Not Channelized)
 */

#define A_BCM1480_PMI_GLB_0                 0x0010056000
#define A_BCM1480_PMO_GLB_0                 0x0010057000

/*
 * PM to TX Mapping Register relative to A_BCM1480_PMI_GLB_0 and A_BCM1480_PMO_GLB_0
 */

#define R_BCM1480_PM_PMO_MAPPING            0x00000008C8   /* PMO only */

#define A_BCM1480_PM_PMO_MAPPING	(A_BCM1480_PMO_GLB_0 + R_BCM1480_PM_PMO_MAPPING)

/*
 * Interrupt mapping registers
 */


#define A_BCM1480_PMI_INT_0                 0x0010056800
#define A_BCM1480_PMI_INT(q)                (A_BCM1480_PMI_INT_0 + ((q>>8)<<8))
#define A_BCM1480_PMI_INT_OFFSET_0          (A_BCM1480_PMI_INT_0 - A_BCM1480_PM_BASE)
#define A_BCM1480_PMO_INT_0                 0x0010057800
#define A_BCM1480_PMO_INT(q)                (A_BCM1480_PMO_INT_0 + ((q>>8)<<8))
#define A_BCM1480_PMO_INT_OFFSET_0          (A_BCM1480_PMO_INT_0 - A_BCM1480_PM_BASE)

/*
 * Interrupt registers relative to A_BCM1480_PMI_INT_0 and A_BCM1480_PMO_INT_0
 */

#define R_BCM1480_PM_INT_ST                 0x0000000000
#define R_BCM1480_PM_INT_MSK                0x0000000040
#define R_BCM1480_PM_INT_CLR                0x0000000080
#define R_BCM1480_PM_MRGD_INT               0x00000000C0

/*
 * Debug registers (global)
 */

#define A_BCM1480_PM_GLOBALDEBUGMODE_PMI    0x0010056000
#define A_BCM1480_PM_GLOBALDEBUG_PID        0x00100567F8
#define A_BCM1480_PM_GLOBALDEBUG_PIB        0x0010056FF8
#define A_BCM1480_PM_GLOBALDEBUGMODE_PMO    0x0010057000
#define A_BCM1480_PM_GLOBALDEBUG_POD        0x00100577F8
#define A_BCM1480_PM_GLOBALDEBUG_POB        0x0010057FF8

/*  *********************************************************************
    *  Switch performance counters
    ********************************************************************* */

#define A_BCM1480_SWPERF_CFG	0xdfb91800
#define A_BCM1480_SWPERF_CNT0	0xdfb91880
#define A_BCM1480_SWPERF_CNT1	0xdfb91888
#define A_BCM1480_SWPERF_CNT2	0xdfb91890
#define A_BCM1480_SWPERF_CNT3	0xdfb91898


/*  *********************************************************************
    *  Switch Trace Unit
    ********************************************************************* */

#define A_BCM1480_SWTRC_MATCH_CONTROL_0		0xDFB91000
#define A_BCM1480_SWTRC_MATCH_DATA_VALUE_0	0xDFB91100
#define A_BCM1480_SWTRC_MATCH_DATA_MASK_0	0xDFB91108
#define A_BCM1480_SWTRC_MATCH_TAG_VALUE_0	0xDFB91200
#define A_BCM1480_SWTRC_MATCH_TAG_MAKS_0	0xDFB91208
#define A_BCM1480_SWTRC_EVENT_0			0xDFB91300
#define A_BCM1480_SWTRC_SEQUENCE_0		0xDFB91400

#define A_BCM1480_SWTRC_CFG			0xDFB91500
#define A_BCM1480_SWTRC_READ			0xDFB91508

#define A_BCM1480_SWDEBUG_SCHEDSTOP		0xDFB92000

#define A_BCM1480_SWTRC_MATCH_CONTROL(x) (A_BCM1480_SWTRC_MATCH_CONTROL_0 + ((x)*8))
#define A_BCM1480_SWTRC_EVENT(x) (A_BCM1480_SWTRC_EVENT_0 + ((x)*8))
#define A_BCM1480_SWTRC_SEQUENCE(x) (A_BCM1480_SWTRC_SEQUENCE_0 + ((x)*8))

#define A_BCM1480_SWTRC_MATCH_DATA_VALUE(x) (A_BCM1480_SWTRC_MATCH_DATA_VALUE_0 + ((x)*16))
#define A_BCM1480_SWTRC_MATCH_DATA_MASK(x) (A_BCM1480_SWTRC_MATCH_DATA_MASK_0 + ((x)*16))
#define A_BCM1480_SWTRC_MATCH_TAG_VALUE(x) (A_BCM1480_SWTRC_MATCH_TAG_VALUE_0 + ((x)*16))
#define A_BCM1480_SWTRC_MATCH_TAG_MASK(x) (A_BCM1480_SWTRC_MATCH_TAG_MASK_0 + ((x)*16))



/*  *********************************************************************
    *  High-Speed Port Registers (Section 13)
    ********************************************************************* */

#define A_BCM1480_HSP_BASE_0                0x00DF810000
#define A_BCM1480_HSP_BASE_1                0x00DF890000
#define A_BCM1480_HSP_BASE_2                0x00DF910000
#define BCM1480_HSP_REGISTER_SPACING        0x80000

#define A_BCM1480_HSP_BASE(idx)             (A_BCM1480_HSP_BASE_0 + ((idx)*BCM1480_HSP_REGISTER_SPACING))
#define A_BCM1480_HSP_REGISTER(idx,reg)     (A_BCM1480_HSP_BASE(idx) + (reg))

#define R_BCM1480_HSP_RX_SPI4_CFG_0           0x0000000000
#define R_BCM1480_HSP_RX_SPI4_CFG_1           0x0000000008
#define R_BCM1480_HSP_RX_SPI4_DESKEW_OVERRIDE 0x0000000010
#define R_BCM1480_HSP_RX_SPI4_DESKEW_DATAPATH 0x0000000018
#define R_BCM1480_HSP_RX_SPI4_PORT_INT_EN     0x0000000020
#define R_BCM1480_HSP_RX_SPI4_PORT_INT_STATUS 0x0000000028

#define R_BCM1480_HSP_RX_SPI4_CALENDAR_0      0x0000000200
#define R_BCM1480_HSP_RX_SPI4_CALENDAR_1      0x0000000208

#define R_BCM1480_HSP_RX_PLL_CNFG             0x0000000800
#define R_BCM1480_HSP_RX_CALIBRATION          0x0000000808
#define R_BCM1480_HSP_RX_TEST                 0x0000000810
#define R_BCM1480_HSP_RX_DIAG_DETAILS         0x0000000818
#define R_BCM1480_HSP_RX_DIAG_CRC_0           0x0000000820
#define R_BCM1480_HSP_RX_DIAG_CRC_1           0x0000000828
#define R_BCM1480_HSP_RX_DIAG_HTCMD           0x0000000830
#define R_BCM1480_HSP_RX_DIAG_PKTCTL          0x0000000838

#define R_BCM1480_HSP_RX_VIS_FLCTRL_COUNTER   0x0000000870

#define R_BCM1480_HSP_RX_PKT_RAMALLOC_0       0x0000020020
#define R_BCM1480_HSP_RX_PKT_RAMALLOC_1       0x0000020028
#define R_BCM1480_HSP_RX_PKT_RAMALLOC_2       0x0000020030
#define R_BCM1480_HSP_RX_PKT_RAMALLOC_3       0x0000020038
#define R_BCM1480_HSP_RX_PKT_RAMALLOC_4       0x0000020040
#define R_BCM1480_HSP_RX_PKT_RAMALLOC_5       0x0000020048
#define R_BCM1480_HSP_RX_PKT_RAMALLOC_6       0x0000020050
#define R_BCM1480_HSP_RX_PKT_RAMALLOC_7       0x0000020058
#define R_BCM1480_HSP_RX_PKT_RAMALLOC(idx)    (R_BCM1480_HSP_RX_PKT_RAMALLOC_0 + 8*(idx))

/* XXX Following registers were shuffled.  Renamed/renumbered per errata. */
#define R_BCM1480_HSP_RX_HT_RAMALLOC_0      0x0000020078
#define R_BCM1480_HSP_RX_HT_RAMALLOC_1      0x0000020080
#define R_BCM1480_HSP_RX_HT_RAMALLOC_2      0x0000020088
#define R_BCM1480_HSP_RX_HT_RAMALLOC_3      0x0000020090
#define R_BCM1480_HSP_RX_HT_RAMALLOC_4      0x0000020098
#define R_BCM1480_HSP_RX_HT_RAMALLOC_5      0x00000200A0

#define R_BCM1480_HSP_RX_SPI_WATERMARK_0      0x00000200B0
#define R_BCM1480_HSP_RX_SPI_WATERMARK_1      0x00000200B8
#define R_BCM1480_HSP_RX_SPI_WATERMARK_2      0x00000200C0
#define R_BCM1480_HSP_RX_SPI_WATERMARK_3      0x00000200C8
#define R_BCM1480_HSP_RX_SPI_WATERMARK_4      0x00000200D0
#define R_BCM1480_HSP_RX_SPI_WATERMARK_5      0x00000200D8
#define R_BCM1480_HSP_RX_SPI_WATERMARK_6      0x00000200E0
#define R_BCM1480_HSP_RX_SPI_WATERMARK_7      0x00000200E8
#define R_BCM1480_HSP_RX_SPI_WATERMARK(idx)   (R_BCM1480_HSP_RX_SPI_WATERMARK_0 + 8*(idx))

#define R_BCM1480_HSP_RX_VIS_CMDQ_0           0x00000200F0
#define R_BCM1480_HSP_RX_VIS_CMDQ_1           0x00000200F8
#define R_BCM1480_HSP_RX_VIS_CMDQ_2           0x0000020100
#define R_BCM1480_HSP_RX_RAM_READCTL          0x0000020108
#define R_BCM1480_HSP_RX_RAM_READWINDOW       0x0000020110
#define R_BCM1480_HSP_RX_RF_READCTL           0x0000020118
#define R_BCM1480_HSP_RX_RF_READWINDOW        0x0000020120

#define R_BCM1480_HSP_TX_SPI4_CFG_0           0x0000040000
#define R_BCM1480_HSP_TX_SPI4_CFG_1           0x0000040008
#define R_BCM1480_HSP_TX_SPI4_TRAINING_FMT    0x0000040010

#define R_BCM1480_HSP_TX_PKT_RAMALLOC_0       0x0000040020
#define R_BCM1480_HSP_TX_PKT_RAMALLOC_1       0x0000040028
#define R_BCM1480_HSP_TX_PKT_RAMALLOC_2       0x0000040030
#define R_BCM1480_HSP_TX_PKT_RAMALLOC_3       0x0000040038
#define R_BCM1480_HSP_TX_PKT_RAMALLOC_4       0x0000040040
#define R_BCM1480_HSP_TX_PKT_RAMALLOC_5       0x0000040048
#define R_BCM1480_HSP_TX_PKT_RAMALLOC_6       0x0000040050
#define R_BCM1480_HSP_TX_PKT_RAMALLOC_7       0x0000040058
#define R_BCM1480_HSP_TX_PKT_RAMALLOC(idx)    (R_BCM1480_HSP_TX_PKT_RAMALLOC_0 + 8*(idx))
#define R_BCM1480_HSP_TX_NPC_RAMALLOC         0x0000040078
#define R_BCM1480_HSP_TX_RSP_RAMALLOC         0x0000040080
#define R_BCM1480_HSP_TX_PC_RAMALLOC          0x0000040088
#define R_BCM1480_HSP_TX_HTCC_RAMALLOC_0      0x0000040090
#define R_BCM1480_HSP_TX_HTCC_RAMALLOC_1      0x0000040098
#define R_BCM1480_HSP_TX_HTCC_RAMALLOC_2      0x00000400A0

#define R_BCM1480_HSP_TX_PKT_RXPHITCNT_0      0x00000400B0
#define R_BCM1480_HSP_TX_PKT_RXPHITCNT_1      0x00000400B8
#define R_BCM1480_HSP_TX_PKT_RXPHITCNT_2      0x00000400C0
#define R_BCM1480_HSP_TX_PKT_RXPHITCNT_3      0x00000400C8
#define R_BCM1480_HSP_TX_PKT_RXPHITCNT(idx)   (R_BCM1480_HSP_TX_PKT_RXPHITCNT_0 + 8*(idx))
#define R_BCM1480_HSP_TX_HTIO_RXPHITCNT       0x00000400D0
#define R_BCM1480_HSP_TX_HTCC_RXPHITCNT       0x00000400D8

#define R_BCM1480_HSP_TX_PKT_TXPHITCNT_0      0x00000400E0
#define R_BCM1480_HSP_TX_PKT_TXPHITCNT_1      0x00000400E8
#define R_BCM1480_HSP_TX_PKT_TXPHITCNT_2      0x00000400F0
#define R_BCM1480_HSP_TX_PKT_TXPHITCNT_3      0x00000400F8
#define R_BCM1480_HSP_TX_PKT_TXPHITCNT(idx)   (R_BCM1480_HSP_TX_PKT_TXPHITCNT_0 + 8*(idx))
#define R_BCM1480_HSP_TX_HTIO_TXPHITCNT       0x0000040100
#define R_BCM1480_HSP_TX_HTCC_TXPHITCNT       0x0000040108

#define R_BCM1480_HSP_TX_SPI4_CALENDAR_0      0x0000040200
#define R_BCM1480_HSP_TX_SPI4_CALENDAR_1      0x0000040208

#define R_BCM1480_HSP_TX_PLL_CNFG             0x0000040800
#define R_BCM1480_HSP_TX_CALIBRATION          0x0000040808
#define R_BCM1480_HSP_TX_TEST                 0x0000040810

#define R_BCM1480_HSP_TX_VIS_CMDQ_0           0x0000040840
#define R_BCM1480_HSP_TX_VIS_CMDQ_1           0x0000040848
#define R_BCM1480_HSP_TX_VIS_CMDQ_2           0x0000040850
#define R_BCM1480_HSP_TX_RAM_READCTL          0x0000040860
#define R_BCM1480_HSP_TX_RAM_READWINDOW       0x0000040868
#define R_BCM1480_HSP_TX_RF_READCTL           0x0000040870
#define R_BCM1480_HSP_TX_RF_READWINDOW        0x0000040878

#define R_BCM1480_HSP_TX_SPI4_PORT_INT_STATUS 0x0000040880
#define R_BCM1480_HSP_TX_SPI4_PORT_INT_EN     0x0000040888

#define R_BCM1480_HSP_TX_NEXT_ADDR_BASE 0x000040400
#define R_BCM1480_HSP_TX_NEXT_ADDR_REGISTER(x)  (R_BCM1480_HSP_TX_NEXT_ADDR_BASE+ 8*(x))



/*  *********************************************************************
    *  Physical Address Map (Table 10 and Figure 7)
    ********************************************************************* */

#define A_BCM1480_PHYS_MEMORY_0                 _SB_MAKE64(0x0000000000)
#define A_BCM1480_PHYS_MEMORY_SIZE              _SB_MAKE64((256*1024*1024))
#define A_BCM1480_PHYS_SYSTEM_CTL               _SB_MAKE64(0x0010000000)
#define A_BCM1480_PHYS_IO_SYSTEM                _SB_MAKE64(0x0010060000)
#define A_BCM1480_PHYS_GENBUS                   _SB_MAKE64(0x0010090000)
#define A_BCM1480_PHYS_GENBUS_END               _SB_MAKE64(0x0028000000)
#define A_BCM1480_PHYS_PCI_MISC_MATCH_BYTES     _SB_MAKE64(0x0028000000)
#define A_BCM1480_PHYS_PCI_IACK_MATCH_BYTES     _SB_MAKE64(0x0029000000)
#define A_BCM1480_PHYS_PCI_IO_MATCH_BYTES       _SB_MAKE64(0x002C000000)
#define A_BCM1480_PHYS_PCI_CFG_MATCH_BYTES      _SB_MAKE64(0x002E000000)
#define A_BCM1480_PHYS_PCI_OMAP_MATCH_BYTES     _SB_MAKE64(0x002F000000)
#define A_BCM1480_PHYS_PCI_MEM_MATCH_BYTES      _SB_MAKE64(0x0030000000)
#define A_BCM1480_PHYS_HT_MEM_MATCH_BYTES       _SB_MAKE64(0x0040000000)
#define A_BCM1480_PHYS_HT_MEM_MATCH_BITS        _SB_MAKE64(0x0060000000)
#define A_BCM1480_PHYS_MEMORY_1                 _SB_MAKE64(0x0080000000)
#define A_BCM1480_PHYS_MEMORY_2                 _SB_MAKE64(0x0090000000)
#define A_BCM1480_PHYS_PCI_MISC_MATCH_BITS      _SB_MAKE64(0x00A8000000)
#define A_BCM1480_PHYS_PCI_IACK_MATCH_BITS      _SB_MAKE64(0x00A9000000)
#define A_BCM1480_PHYS_PCI_IO_MATCH_BITS        _SB_MAKE64(0x00AC000000)
#define A_BCM1480_PHYS_PCI_CFG_MATCH_BITS       _SB_MAKE64(0x00AE000000)
#define A_BCM1480_PHYS_PCI_OMAP_MATCH_BITS      _SB_MAKE64(0x00AF000000)
#define A_BCM1480_PHYS_PCI_MEM_MATCH_BITS       _SB_MAKE64(0x00B0000000)
#define A_BCM1480_PHYS_MEMORY_3                 _SB_MAKE64(0x00C0000000)
#define A_BCM1480_PHYS_L2_CACHE_TEST            _SB_MAKE64(0x00D0000000)
#define A_BCM1480_PHYS_HT_SPECIAL_MATCH_BYTES   _SB_MAKE64(0x00D8000000)
#define A_BCM1480_PHYS_HT_IO_MATCH_BYTES        _SB_MAKE64(0x00DC000000)
#define A_BCM1480_PHYS_HT_CFG_MATCH_BYTES       _SB_MAKE64(0x00DE000000)
#define A_BCM1480_PHYS_HS_SUBSYS                _SB_MAKE64(0x00DF000000)
#define A_BCM1480_PHYS_HT_SPECIAL_MATCH_BITS    _SB_MAKE64(0x00F8000000)
#define A_BCM1480_PHYS_HT_IO_MATCH_BITS         _SB_MAKE64(0x00FC000000)
#define A_BCM1480_PHYS_HT_CFG_MATCH_BITS        _SB_MAKE64(0x00FE000000)
#define A_BCM1480_PHYS_MEMORY_EXP               _SB_MAKE64(0x0100000000)
#define A_BCM1480_PHYS_MEMORY_EXP_SIZE          _SB_MAKE64((508*1024*1024*1024))
#define A_BCM1480_PHYS_PCI_UPPER                _SB_MAKE64(0x1000000000)
#define A_BCM1480_PHYS_HT_UPPER_MATCH_BYTES     _SB_MAKE64(0x2000000000)
#define A_BCM1480_PHYS_HT_UPPER_MATCH_BITS      _SB_MAKE64(0x3000000000)
#define A_BCM1480_PHYS_HT_NODE_ALIAS            _SB_MAKE64(0x4000000000)
#define A_BCM1480_PHYS_HT_FULLACCESS            _SB_MAKE64(0xF000000000)


/*  *********************************************************************
    *  L2 Cache as RAM (Table 54)
    ********************************************************************* */

#define A_BCM1480_PHYS_L2CACHE_WAY_SIZE         _SB_MAKE64(0x0000020000)
#define BCM1480_PHYS_L2CACHE_NUM_WAYS           8
#define A_BCM1480_PHYS_L2CACHE_TOTAL_SIZE       _SB_MAKE64(0x0000100000)
#define A_BCM1480_PHYS_L2CACHE_WAY0             _SB_MAKE64(0x00D0300000)
#define A_BCM1480_PHYS_L2CACHE_WAY1             _SB_MAKE64(0x00D0320000)
#define A_BCM1480_PHYS_L2CACHE_WAY2             _SB_MAKE64(0x00D0340000)
#define A_BCM1480_PHYS_L2CACHE_WAY3             _SB_MAKE64(0x00D0360000)
#define A_BCM1480_PHYS_L2CACHE_WAY4             _SB_MAKE64(0x00D0380000)
#define A_BCM1480_PHYS_L2CACHE_WAY5             _SB_MAKE64(0x00D03A0000)
#define A_BCM1480_PHYS_L2CACHE_WAY6             _SB_MAKE64(0x00D03C0000)
#define A_BCM1480_PHYS_L2CACHE_WAY7             _SB_MAKE64(0x00D03E0000)

#endif /* _BCM1480_REGS_H */