bcm1480_regs.h

linux-2.6.15.6

#define R_BCM1480_GPIO_INT_ADD_TYPE         (-8)

#define A_GPIO_INT_ADD_TYPE	A_BCM1480_GPIO_INT_ADD_TYPE
#define R_GPIO_INT_ADD_TYPE	R_BCM1480_GPIO_INT_ADD_TYPE

/*  *********************************************************************
    * SMBus Registers (Section 18)
    ********************************************************************* */

/* No changes from BCM1250 */

/*  *********************************************************************
    * Timer Registers (Sections 4.6)
    ********************************************************************* */

/* BCM1480 has two additional watchdogs */

/* Watchdog timers */

#define A_BCM1480_SCD_WDOG_2                0x0010022050
#define A_BCM1480_SCD_WDOG_3                0x0010022150

#define BCM1480_SCD_NUM_WDOGS               4

#define A_BCM1480_SCD_WDOG_BASE(w)       (A_BCM1480_SCD_WDOG_0+((w)&2)*0x1000 + ((w)&1)*0x100)
#define A_BCM1480_SCD_WDOG_REGISTER(w,r) (A_BCM1480_SCD_WDOG_BASE(w) + (r))

#define A_BCM1480_SCD_WDOG_INIT_2       0x0010022050
#define A_BCM1480_SCD_WDOG_CNT_2        0x0010022058
#define A_BCM1480_SCD_WDOG_CFG_2        0x0010022060

#define A_BCM1480_SCD_WDOG_INIT_3       0x0010022150
#define A_BCM1480_SCD_WDOG_CNT_3        0x0010022158
#define A_BCM1480_SCD_WDOG_CFG_3        0x0010022160

/* BCM1480 has two additional compare registers */

#define A_BCM1480_SCD_ZBBUS_CYCLE_COUNT		A_SCD_ZBBUS_CYCLE_COUNT
#define A_BCM1480_SCD_ZBBUS_CYCLE_CP_BASE       0x0010020C00
#define A_BCM1480_SCD_ZBBUS_CYCLE_CP0           A_SCD_ZBBUS_CYCLE_CP0
#define A_BCM1480_SCD_ZBBUS_CYCLE_CP1           A_SCD_ZBBUS_CYCLE_CP1
#define A_BCM1480_SCD_ZBBUS_CYCLE_CP2           0x0010020C10
#define A_BCM1480_SCD_ZBBUS_CYCLE_CP3           0x0010020C18

/*  *********************************************************************
    * System Control Registers (Section 4.2)
    ********************************************************************* */

/* Scratch register in different place */

#define A_BCM1480_SCD_SCRATCH	 	0x100200A0

/*  *********************************************************************
    * System Address Trap Registers (Section 4.9)
    ********************************************************************* */

/* No changes from BCM1250 */

/*  *********************************************************************
    * System Interrupt Mapper Registers (Sections 4.3-4.5)
    ********************************************************************* */

#define A_BCM1480_IMR_CPU0_BASE             0x0010020000
#define A_BCM1480_IMR_CPU1_BASE             0x0010022000
#define A_BCM1480_IMR_CPU2_BASE             0x0010024000
#define A_BCM1480_IMR_CPU3_BASE             0x0010026000
#define BCM1480_IMR_REGISTER_SPACING        0x2000
#define BCM1480_IMR_REGISTER_SPACING_SHIFT  13

#define A_BCM1480_IMR_MAPPER(cpu)       (A_BCM1480_IMR_CPU0_BASE+(cpu)*BCM1480_IMR_REGISTER_SPACING)
#define A_BCM1480_IMR_REGISTER(cpu,reg) (A_BCM1480_IMR_MAPPER(cpu)+(reg))

/* Most IMR registers are 128 bits, implemented as non-contiguous
   64-bit registers high (_H) and low (_L) */
#define BCM1480_IMR_HL_SPACING                  0x1000

#define R_BCM1480_IMR_INTERRUPT_DIAG_H          0x0010
#define R_BCM1480_IMR_LDT_INTERRUPT_H           0x0018
#define R_BCM1480_IMR_LDT_INTERRUPT_CLR_H       0x0020
#define R_BCM1480_IMR_INTERRUPT_MASK_H          0x0028
#define R_BCM1480_IMR_INTERRUPT_TRACE_H         0x0038
#define R_BCM1480_IMR_INTERRUPT_SOURCE_STATUS_H 0x0040
#define R_BCM1480_IMR_LDT_INTERRUPT_SET         0x0048
#define R_BCM1480_IMR_MAILBOX_0_CPU             0x00C0
#define R_BCM1480_IMR_MAILBOX_0_SET_CPU         0x00C8
#define R_BCM1480_IMR_MAILBOX_0_CLR_CPU         0x00D0
#define R_BCM1480_IMR_MAILBOX_1_CPU             0x00E0
#define R_BCM1480_IMR_MAILBOX_1_SET_CPU         0x00E8
#define R_BCM1480_IMR_MAILBOX_1_CLR_CPU         0x00F0
#define R_BCM1480_IMR_INTERRUPT_STATUS_BASE_H   0x0100
#define BCM1480_IMR_INTERRUPT_STATUS_COUNT      8
#define R_BCM1480_IMR_INTERRUPT_MAP_BASE_H      0x0200
#define BCM1480_IMR_INTERRUPT_MAP_COUNT         64

#define R_BCM1480_IMR_INTERRUPT_DIAG_L          0x1010
#define R_BCM1480_IMR_LDT_INTERRUPT_L           0x1018
#define R_BCM1480_IMR_LDT_INTERRUPT_CLR_L       0x1020
#define R_BCM1480_IMR_INTERRUPT_MASK_L          0x1028
#define R_BCM1480_IMR_INTERRUPT_TRACE_L         0x1038
#define R_BCM1480_IMR_INTERRUPT_SOURCE_STATUS_L 0x1040
#define R_BCM1480_IMR_INTERRUPT_STATUS_BASE_L   0x1100
#define R_BCM1480_IMR_INTERRUPT_MAP_BASE_L      0x1200

#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU0_BASE   0x0010028000
#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU1_BASE   0x0010028100
#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU2_BASE   0x0010028200
#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU3_BASE   0x0010028300
#define BCM1480_IMR_ALIAS_MAILBOX_SPACING       0100

#define A_BCM1480_IMR_ALIAS_MAILBOX(cpu)     (A_BCM1480_IMR_ALIAS_MAILBOX_CPU0_BASE + \
                                        (cpu)*BCM1480_IMR_ALIAS_MAILBOX_SPACING)
#define A_BCM1480_IMR_ALIAS_MAILBOX_REGISTER(cpu,reg) (A_BCM1480_IMR_ALIAS_MAILBOX(cpu)+(reg))

#define R_BCM1480_IMR_ALIAS_MAILBOX_0           0x0000		/* 0x0x0 */
#define R_BCM1480_IMR_ALIAS_MAILBOX_0_SET       0x0008		/* 0x0x8 */

/*  *********************************************************************
    * System Performance Counter Registers (Section 4.7)
    ********************************************************************* */

/* BCM1480 has four more performance counter registers, and two control
   registers. */

#define A_BCM1480_SCD_PERF_CNT_BASE         0x00100204C0

#define A_BCM1480_SCD_PERF_CNT_CFG0         0x00100204C0
#define A_BCM1480_SCD_PERF_CNT_CFG_0        A_BCM1480_SCD_PERF_CNT_CFG0
#define A_BCM1480_SCD_PERF_CNT_CFG1         0x00100204C8
#define A_BCM1480_SCD_PERF_CNT_CFG_1        A_BCM1480_SCD_PERF_CNT_CFG1

#define A_BCM1480_SCD_PERF_CNT_0            A_SCD_PERF_CNT_0
#define A_BCM1480_SCD_PERF_CNT_1            A_SCD_PERF_CNT_1
#define A_BCM1480_SCD_PERF_CNT_2            A_SCD_PERF_CNT_2
#define A_BCM1480_SCD_PERF_CNT_3            A_SCD_PERF_CNT_3

#define A_BCM1480_SCD_PERF_CNT_4            0x00100204F0
#define A_BCM1480_SCD_PERF_CNT_5            0x00100204F8
#define A_BCM1480_SCD_PERF_CNT_6            0x0010020500
#define A_BCM1480_SCD_PERF_CNT_7            0x0010020508

/*  *********************************************************************
    * System Bus Watcher Registers (Section 4.8)
    ********************************************************************* */


/* Same as 1250 except BUS_ERR_STATUS_DEBUG is in a different place. */

#define A_BCM1480_BUS_ERR_STATUS_DEBUG      0x00100208D8

/*  *********************************************************************
    * System Debug Controller Registers (Section 19)
    ********************************************************************* */

/* Same as 1250 */

/*  *********************************************************************
    * System Trace Unit Registers (Sections 4.10)
    ********************************************************************* */

/* Same as 1250 */

/*  *********************************************************************
    * Data Mover DMA Registers (Section 10.7)
    ********************************************************************* */

/* Same as 1250 */


/*  *********************************************************************
    * HyperTransport Interface Registers (Section 8)
    ********************************************************************* */

#define BCM1480_HT_NUM_PORTS		   3
#define BCM1480_HT_PORT_SPACING		   0x800
#define A_BCM1480_HT_PORT_HEADER(x)	   (A_BCM1480_HT_PORT0_HEADER + ((x)*BCM1480_HT_PORT_SPACING))

#define A_BCM1480_HT_PORT0_HEADER          0x00FE000000
#define A_BCM1480_HT_PORT1_HEADER          0x00FE000800
#define A_BCM1480_HT_PORT2_HEADER          0x00FE001000
#define A_BCM1480_HT_TYPE00_HEADER         0x00FE002000


/*  *********************************************************************
    * Node Controller Registers (Section 9)
    ********************************************************************* */

#define A_BCM1480_NC_BASE                   0x00DFBD0000

#define A_BCM1480_NC_RLD_FIELD              0x00DFBD0000
#define A_BCM1480_NC_RLD_TRIGGER            0x00DFBD0020
#define A_BCM1480_NC_RLD_BAD_ERROR          0x00DFBD0040
#define A_BCM1480_NC_RLD_COR_ERROR          0x00DFBD0060
#define A_BCM1480_NC_RLD_ECC_STATUS         0x00DFBD0080
#define A_BCM1480_NC_RLD_WAY_ENABLE         0x00DFBD00A0
#define A_BCM1480_NC_RLD_RANDOM_LFSR        0x00DFBD00C0

#define A_BCM1480_NC_INTERRUPT_STATUS       0x00DFBD00E0
#define A_BCM1480_NC_INTERRUPT_ENABLE       0x00DFBD0100
#define A_BCM1480_NC_TIMEOUT_COUNTER        0x00DFBD0120
#define A_BCM1480_NC_TIMEOUT_COUNTER_SEL    0x00DFBD0140

#define A_BCM1480_NC_CREDIT_STATUS_REG0     0x00DFBD0200
#define A_BCM1480_NC_CREDIT_STATUS_REG1     0x00DFBD0220
#define A_BCM1480_NC_CREDIT_STATUS_REG2     0x00DFBD0240
#define A_BCM1480_NC_CREDIT_STATUS_REG3     0x00DFBD0260
#define A_BCM1480_NC_CREDIT_STATUS_REG4     0x00DFBD0280
#define A_BCM1480_NC_CREDIT_STATUS_REG5     0x00DFBD02A0
#define A_BCM1480_NC_CREDIT_STATUS_REG6     0x00DFBD02C0
#define A_BCM1480_NC_CREDIT_STATUS_REG7     0x00DFBD02E0
#define A_BCM1480_NC_CREDIT_STATUS_REG8     0x00DFBD0300
#define A_BCM1480_NC_CREDIT_STATUS_REG9     0x00DFBD0320
#define A_BCM1480_NC_CREDIT_STATUS_REG10    0x00DFBE0000
#define A_BCM1480_NC_CREDIT_STATUS_REG11    0x00DFBE0020
#define A_BCM1480_NC_CREDIT_STATUS_REG12    0x00DFBE0040

#define A_BCM1480_NC_SR_TIMEOUT_COUNTER     0x00DFBE0060
#define A_BCM1480_NC_SR_TIMEOUT_COUNTER_SEL 0x00DFBE0080


/*  *********************************************************************
    * H&R Block Configuration Registers (Section 12.4)
    ********************************************************************* */

#define A_BCM1480_HR_BASE_0                 0x00DF820000
#define A_BCM1480_HR_BASE_1                 0x00DF8A0000
#define A_BCM1480_HR_BASE_2                 0x00DF920000
#define BCM1480_HR_REGISTER_SPACING         0x80000

#define A_BCM1480_HR_BASE(idx)              (A_BCM1480_HR_BASE_0 + ((idx)*BCM1480_HR_REGISTER_SPACING))
#define A_BCM1480_HR_REGISTER(idx,reg)      (A_BCM1480_HR_BASE(idx) + (reg))

#define R_BCM1480_HR_CFG                    0x0000000000

#define R_BCM1480_HR_MAPPING		    0x0000010010

#define BCM1480_HR_RULE_SPACING             0x0000000010
#define BCM1480_HR_NUM_RULES                16
#define BCM1480_HR_OP_OFFSET                0x0000000100
#define BCM1480_HR_TYPE_OFFSET              0x0000000108
#define R_BCM1480_HR_RULE_OP(idx)           (BCM1480_HR_OP_OFFSET + ((idx)*BCM1480_HR_RULE_SPACING))
#define R_BCM1480_HR_RULE_TYPE(idx)         (BCM1480_HR_TYPE_OFFSET + ((idx)*BCM1480_HR_RULE_SPACING))

#define BCM1480_HR_LEAF_SPACING             0x0000000010
#define BCM1480_HR_NUM_LEAVES               10
#define BCM1480_HR_LEAF_OFFSET              0x0000000300
#define R_BCM1480_HR_HA_LEAF0(idx)          (BCM1480_HR_LEAF_OFFSET + ((idx)*BCM1480_HR_LEAF_SPACING))

#define R_BCM1480_HR_EX_LEAF0               0x00000003A0

#define BCM1480_HR_PATH_SPACING             0x0000000010
#define BCM1480_HR_NUM_PATHS                16
#define BCM1480_HR_PATH_OFFSET              0x0000000600
#define R_BCM1480_HR_PATH(idx)              (BCM1480_HR_PATH_OFFSET + ((idx)*BCM1480_HR_PATH_SPACING))

#define R_BCM1480_HR_PATH_DEFAULT           0x0000000700

#define BCM1480_HR_ROUTE_SPACING            8
#define BCM1480_HR_NUM_ROUTES               512
#define BCM1480_HR_ROUTE_OFFSET             0x0000001000
#define R_BCM1480_HR_RT_WORD(idx)           (BCM1480_HR_ROUTE_OFFSET + ((idx)*BCM1480_HR_ROUTE_SPACING))


/* checked to here - ehs */
/*  *********************************************************************
    * Packet Manager DMA Registers (Section 12.5)
    ********************************************************************* */

#define A_BCM1480_PM_BASE                   0x0010056000

#define A_BCM1480_PMI_LCL_0                 0x0010058000
#define A_BCM1480_PMO_LCL_0                 0x001005C000
#define A_BCM1480_PMI_OFFSET_0              (A_BCM1480_PMI_LCL_0 - A_BCM1480_PM_BASE)
#define A_BCM1480_PMO_OFFSET_0              (A_BCM1480_PMO_LCL_0 - A_BCM1480_PM_BASE)

#define BCM1480_PM_LCL_REGISTER_SPACING     0x100
#define BCM1480_PM_NUM_CHANNELS             32

#define A_BCM1480_PMI_LCL_BASE(idx)             (A_BCM1480_PMI_LCL_0 + ((idx)*BCM1480_PM_LCL_REGISTER_SPACING))
#define A_BCM1480_PMI_LCL_REGISTER(idx,reg)     (A_BCM1480_PMI_LCL_BASE(idx) + (reg))
#define A_BCM1480_PMO_LCL_BASE(idx)             (A_BCM1480_PMO_LCL_0 + ((idx)*BCM1480_PM_LCL_REGISTER_SPACING))
#define A_BCM1480_PMO_LCL_REGISTER(idx,reg)     (A_BCM1480_PMO_LCL_BASE(idx) + (reg))

#define BCM1480_PM_INT_PACKING              8
#define BCM1480_PM_INT_FUNCTION_SPACING     0x40
#define BCM1480_PM_INT_NUM_FUNCTIONS        3

/*
 * DMA channel registers relative to A_BCM1480_PMI_LCL_BASE(n) and A_BCM1480_PMO_LCL_BASE(n)
 */