sb1250_mc.h

linux-2.6.15.6

#define V_MC_MODE(x)                _SB_MAKEVALUE(x,S_MC_MODE)
#define G_MC_MODE(x)                _SB_GETVALUE(x,S_MC_MODE,M_MC_MODE)
#define V_MC_MODE_DEFAULT           V_MC_MODE(0x22)

#define S_MC_DRAM_TYPE              32
#define M_MC_DRAM_TYPE              _SB_MAKEMASK(3,S_MC_DRAM_TYPE)
#define V_MC_DRAM_TYPE(x)           _SB_MAKEVALUE(x,S_MC_DRAM_TYPE)
#define G_MC_DRAM_TYPE(x)           _SB_GETVALUE(x,S_MC_DRAM_TYPE,M_MC_DRAM_TYPE)

#define K_MC_DRAM_TYPE_JEDEC        0
#define K_MC_DRAM_TYPE_FCRAM        1
#define K_MC_DRAM_TYPE_SGRAM	    2

#define V_MC_DRAM_TYPE_JEDEC        V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_JEDEC)
#define V_MC_DRAM_TYPE_FCRAM        V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_FCRAM)
#define V_MC_DRAM_TYPE_SGRAM        V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_SGRAM)

#define M_MC_EXTERNALDECODE	    _SB_MAKEMASK1(35)

#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define M_MC_PRE_ON_A8              _SB_MAKEMASK1(36)
#define M_MC_RAM_WITH_A13           _SB_MAKEMASK1(38)
#endif /* 1250 PASS3 || 112x PASS1 */



/*
 * SDRAM Timing Register  (Table 6-15)
 */

#define M_MC_w2rIDLE_TWOCYCLES	  _SB_MAKEMASK1(60)
#define M_MC_r2wIDLE_TWOCYCLES	  _SB_MAKEMASK1(61)
#define M_MC_r2rIDLE_TWOCYCLES	  _SB_MAKEMASK1(62)

#define S_MC_tFIFO                56
#define M_MC_tFIFO                _SB_MAKEMASK(4,S_MC_tFIFO)
#define V_MC_tFIFO(x)             _SB_MAKEVALUE(x,S_MC_tFIFO)
#define G_MC_tFIFO(x)             _SB_GETVALUE(x,S_MC_tFIFO,M_MC_tFIFO)
#define K_MC_tFIFO_DEFAULT        1
#define V_MC_tFIFO_DEFAULT        V_MC_tFIFO(K_MC_tFIFO_DEFAULT)

#define S_MC_tRFC                 52
#define M_MC_tRFC                 _SB_MAKEMASK(4,S_MC_tRFC)
#define V_MC_tRFC(x)              _SB_MAKEVALUE(x,S_MC_tRFC)
#define G_MC_tRFC(x)              _SB_GETVALUE(x,S_MC_tRFC,M_MC_tRFC)
#define K_MC_tRFC_DEFAULT         12
#define V_MC_tRFC_DEFAULT         V_MC_tRFC(K_MC_tRFC_DEFAULT)

#if SIBYTE_HDR_FEATURE(1250, PASS3)
#define M_MC_tRFC_PLUS16          _SB_MAKEMASK1(51)	/* 1250C3 and later.  */
#endif

#define S_MC_tCwCr                40
#define M_MC_tCwCr                _SB_MAKEMASK(4,S_MC_tCwCr)
#define V_MC_tCwCr(x)             _SB_MAKEVALUE(x,S_MC_tCwCr)
#define G_MC_tCwCr(x)             _SB_GETVALUE(x,S_MC_tCwCr,M_MC_tCwCr)
#define K_MC_tCwCr_DEFAULT        4
#define V_MC_tCwCr_DEFAULT        V_MC_tCwCr(K_MC_tCwCr_DEFAULT)

#define S_MC_tRCr                 28
#define M_MC_tRCr                 _SB_MAKEMASK(4,S_MC_tRCr)
#define V_MC_tRCr(x)              _SB_MAKEVALUE(x,S_MC_tRCr)
#define G_MC_tRCr(x)              _SB_GETVALUE(x,S_MC_tRCr,M_MC_tRCr)
#define K_MC_tRCr_DEFAULT         9
#define V_MC_tRCr_DEFAULT         V_MC_tRCr(K_MC_tRCr_DEFAULT)

#define S_MC_tRCw                 24
#define M_MC_tRCw                 _SB_MAKEMASK(4,S_MC_tRCw)
#define V_MC_tRCw(x)              _SB_MAKEVALUE(x,S_MC_tRCw)
#define G_MC_tRCw(x)              _SB_GETVALUE(x,S_MC_tRCw,M_MC_tRCw)
#define K_MC_tRCw_DEFAULT         10
#define V_MC_tRCw_DEFAULT         V_MC_tRCw(K_MC_tRCw_DEFAULT)

#define S_MC_tRRD                 20
#define M_MC_tRRD                 _SB_MAKEMASK(4,S_MC_tRRD)
#define V_MC_tRRD(x)              _SB_MAKEVALUE(x,S_MC_tRRD)
#define G_MC_tRRD(x)              _SB_GETVALUE(x,S_MC_tRRD,M_MC_tRRD)
#define K_MC_tRRD_DEFAULT         2
#define V_MC_tRRD_DEFAULT         V_MC_tRRD(K_MC_tRRD_DEFAULT)

#define S_MC_tRP                  16
#define M_MC_tRP                  _SB_MAKEMASK(4,S_MC_tRP)
#define V_MC_tRP(x)               _SB_MAKEVALUE(x,S_MC_tRP)
#define G_MC_tRP(x)               _SB_GETVALUE(x,S_MC_tRP,M_MC_tRP)
#define K_MC_tRP_DEFAULT          4
#define V_MC_tRP_DEFAULT          V_MC_tRP(K_MC_tRP_DEFAULT)

#define S_MC_tCwD                 8
#define M_MC_tCwD                 _SB_MAKEMASK(4,S_MC_tCwD)
#define V_MC_tCwD(x)              _SB_MAKEVALUE(x,S_MC_tCwD)
#define G_MC_tCwD(x)              _SB_GETVALUE(x,S_MC_tCwD,M_MC_tCwD)
#define K_MC_tCwD_DEFAULT         1
#define V_MC_tCwD_DEFAULT         V_MC_tCwD(K_MC_tCwD_DEFAULT)

#define M_tCrDh                   _SB_MAKEMASK1(7)
#define M_MC_tCrDh		  M_tCrDh

#define S_MC_tCrD                 4
#define M_MC_tCrD                 _SB_MAKEMASK(3,S_MC_tCrD)
#define V_MC_tCrD(x)              _SB_MAKEVALUE(x,S_MC_tCrD)
#define G_MC_tCrD(x)              _SB_GETVALUE(x,S_MC_tCrD,M_MC_tCrD)
#define K_MC_tCrD_DEFAULT         2
#define V_MC_tCrD_DEFAULT         V_MC_tCrD(K_MC_tCrD_DEFAULT)

#define S_MC_tRCD                 0
#define M_MC_tRCD                 _SB_MAKEMASK(4,S_MC_tRCD)
#define V_MC_tRCD(x)              _SB_MAKEVALUE(x,S_MC_tRCD)
#define G_MC_tRCD(x)              _SB_GETVALUE(x,S_MC_tRCD,M_MC_tRCD)
#define K_MC_tRCD_DEFAULT         3
#define V_MC_tRCD_DEFAULT         V_MC_tRCD(K_MC_tRCD_DEFAULT)

#define V_MC_TIMING_DEFAULT     V_MC_tFIFO(K_MC_tFIFO_DEFAULT) | \
                                V_MC_tRFC(K_MC_tRFC_DEFAULT) | \
                                V_MC_tCwCr(K_MC_tCwCr_DEFAULT) | \
                                V_MC_tRCr(K_MC_tRCr_DEFAULT) | \
                                V_MC_tRCw(K_MC_tRCw_DEFAULT) | \
                                V_MC_tRRD(K_MC_tRRD_DEFAULT) | \
                                V_MC_tRP(K_MC_tRP_DEFAULT) | \
                                V_MC_tCwD(K_MC_tCwD_DEFAULT) | \
                                V_MC_tCrD(K_MC_tCrD_DEFAULT) | \
                                V_MC_tRCD(K_MC_tRCD_DEFAULT) | \
                                M_MC_r2rIDLE_TWOCYCLES

/*
 * Errata says these are not the default
 *                               M_MC_w2rIDLE_TWOCYCLES | \
 *                               M_MC_r2wIDLE_TWOCYCLES | \
 */


/*
 * Chip Select Start Address Register (Table 6-17)
 */

#define S_MC_CS0_START              0
#define M_MC_CS0_START              _SB_MAKEMASK(16,S_MC_CS0_START)
#define V_MC_CS0_START(x)           _SB_MAKEVALUE(x,S_MC_CS0_START)
#define G_MC_CS0_START(x)           _SB_GETVALUE(x,S_MC_CS0_START,M_MC_CS0_START)

#define S_MC_CS1_START              16
#define M_MC_CS1_START              _SB_MAKEMASK(16,S_MC_CS1_START)
#define V_MC_CS1_START(x)           _SB_MAKEVALUE(x,S_MC_CS1_START)
#define G_MC_CS1_START(x)           _SB_GETVALUE(x,S_MC_CS1_START,M_MC_CS1_START)

#define S_MC_CS2_START              32
#define M_MC_CS2_START              _SB_MAKEMASK(16,S_MC_CS2_START)
#define V_MC_CS2_START(x)           _SB_MAKEVALUE(x,S_MC_CS2_START)
#define G_MC_CS2_START(x)           _SB_GETVALUE(x,S_MC_CS2_START,M_MC_CS2_START)

#define S_MC_CS3_START              48
#define M_MC_CS3_START              _SB_MAKEMASK(16,S_MC_CS3_START)
#define V_MC_CS3_START(x)           _SB_MAKEVALUE(x,S_MC_CS3_START)
#define G_MC_CS3_START(x)           _SB_GETVALUE(x,S_MC_CS3_START,M_MC_CS3_START)

/*
 * Chip Select End Address Register (Table 6-18)
 */

#define S_MC_CS0_END                0
#define M_MC_CS0_END                _SB_MAKEMASK(16,S_MC_CS0_END)
#define V_MC_CS0_END(x)             _SB_MAKEVALUE(x,S_MC_CS0_END)
#define G_MC_CS0_END(x)             _SB_GETVALUE(x,S_MC_CS0_END,M_MC_CS0_END)

#define S_MC_CS1_END                16
#define M_MC_CS1_END                _SB_MAKEMASK(16,S_MC_CS1_END)
#define V_MC_CS1_END(x)             _SB_MAKEVALUE(x,S_MC_CS1_END)
#define G_MC_CS1_END(x)             _SB_GETVALUE(x,S_MC_CS1_END,M_MC_CS1_END)

#define S_MC_CS2_END                32
#define M_MC_CS2_END                _SB_MAKEMASK(16,S_MC_CS2_END)
#define V_MC_CS2_END(x)             _SB_MAKEVALUE(x,S_MC_CS2_END)
#define G_MC_CS2_END(x)             _SB_GETVALUE(x,S_MC_CS2_END,M_MC_CS2_END)

#define S_MC_CS3_END                48
#define M_MC_CS3_END                _SB_MAKEMASK(16,S_MC_CS3_END)
#define V_MC_CS3_END(x)             _SB_MAKEVALUE(x,S_MC_CS3_END)
#define G_MC_CS3_END(x)             _SB_GETVALUE(x,S_MC_CS3_END,M_MC_CS3_END)

/*
 * Chip Select Interleave Register (Table 6-19)
 */

#define S_MC_INTLV_RESERVED         0
#define M_MC_INTLV_RESERVED         _SB_MAKEMASK(5,S_MC_INTLV_RESERVED)

#define S_MC_INTERLEAVE             7
#define M_MC_INTERLEAVE             _SB_MAKEMASK(18,S_MC_INTERLEAVE)
#define V_MC_INTERLEAVE(x)          _SB_MAKEVALUE(x,S_MC_INTERLEAVE)

#define S_MC_INTLV_MBZ              25
#define M_MC_INTLV_MBZ              _SB_MAKEMASK(39,S_MC_INTLV_MBZ)

/*
 * Row Address Bits Register (Table 6-20)
 */

#define S_MC_RAS_RESERVED           0
#define M_MC_RAS_RESERVED           _SB_MAKEMASK(5,S_MC_RAS_RESERVED)

#define S_MC_RAS_SELECT             12
#define M_MC_RAS_SELECT             _SB_MAKEMASK(25,S_MC_RAS_SELECT)
#define V_MC_RAS_SELECT(x)          _SB_MAKEVALUE(x,S_MC_RAS_SELECT)

#define S_MC_RAS_MBZ                37
#define M_MC_RAS_MBZ                _SB_MAKEMASK(27,S_MC_RAS_MBZ)


/*
 * Column Address Bits Register (Table 6-21)
 */

#define S_MC_CAS_RESERVED           0
#define M_MC_CAS_RESERVED           _SB_MAKEMASK(5,S_MC_CAS_RESERVED)

#define S_MC_CAS_SELECT             5
#define M_MC_CAS_SELECT             _SB_MAKEMASK(18,S_MC_CAS_SELECT)
#define V_MC_CAS_SELECT(x)          _SB_MAKEVALUE(x,S_MC_CAS_SELECT)

#define S_MC_CAS_MBZ                23
#define M_MC_CAS_MBZ                _SB_MAKEMASK(41,S_MC_CAS_MBZ)


/*
 * Bank Address Address Bits Register (Table 6-22)
 */

#define S_MC_BA_RESERVED            0
#define M_MC_BA_RESERVED            _SB_MAKEMASK(5,S_MC_BA_RESERVED)

#define S_MC_BA_SELECT              5
#define M_MC_BA_SELECT              _SB_MAKEMASK(20,S_MC_BA_SELECT)
#define V_MC_BA_SELECT(x)           _SB_MAKEVALUE(x,S_MC_BA_SELECT)

#define S_MC_BA_MBZ                 25
#define M_MC_BA_MBZ                 _SB_MAKEMASK(39,S_MC_BA_MBZ)

/*
 * Chip Select Attribute Register (Table 6-23)
 */

#define K_MC_CS_ATTR_CLOSED         0
#define K_MC_CS_ATTR_CASCHECK       1
#define K_MC_CS_ATTR_HINT           2
#define K_MC_CS_ATTR_OPEN           3

#define S_MC_CS0_PAGE               0
#define M_MC_CS0_PAGE               _SB_MAKEMASK(2,S_MC_CS0_PAGE)
#define V_MC_CS0_PAGE(x)            _SB_MAKEVALUE(x,S_MC_CS0_PAGE)
#define G_MC_CS0_PAGE(x)            _SB_GETVALUE(x,S_MC_CS0_PAGE,M_MC_CS0_PAGE)

#define S_MC_CS1_PAGE               16
#define M_MC_CS1_PAGE               _SB_MAKEMASK(2,S_MC_CS1_PAGE)
#define V_MC_CS1_PAGE(x)            _SB_MAKEVALUE(x,S_MC_CS1_PAGE)
#define G_MC_CS1_PAGE(x)            _SB_GETVALUE(x,S_MC_CS1_PAGE,M_MC_CS1_PAGE)

#define S_MC_CS2_PAGE               32
#define M_MC_CS2_PAGE               _SB_MAKEMASK(2,S_MC_CS2_PAGE)
#define V_MC_CS2_PAGE(x)            _SB_MAKEVALUE(x,S_MC_CS2_PAGE)
#define G_MC_CS2_PAGE(x)            _SB_GETVALUE(x,S_MC_CS2_PAGE,M_MC_CS2_PAGE)

#define S_MC_CS3_PAGE               48
#define M_MC_CS3_PAGE               _SB_MAKEMASK(2,S_MC_CS3_PAGE)
#define V_MC_CS3_PAGE(x)            _SB_MAKEVALUE(x,S_MC_CS3_PAGE)
#define G_MC_CS3_PAGE(x)            _SB_GETVALUE(x,S_MC_CS3_PAGE,M_MC_CS3_PAGE)

/*
 * ECC Test ECC Register (Table 6-25)
 */

#define S_MC_ECC_INVERT             0
#define M_MC_ECC_INVERT             _SB_MAKEMASK(8,S_MC_ECC_INVERT)


#endif