📄 bcm1480_mc.h
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#define M_BCM1480_MC_COL05 _SB_MAKEMASK(6,S_BCM1480_MC_COL05)#define V_BCM1480_MC_COL05(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL05)#define G_BCM1480_MC_COL05(x) _SB_GETVALUE(x,S_BCM1480_MC_COL05,M_BCM1480_MC_COL05)#define S_BCM1480_MC_COL06 48#define M_BCM1480_MC_COL06 _SB_MAKEMASK(6,S_BCM1480_MC_COL06)#define V_BCM1480_MC_COL06(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL06)#define G_BCM1480_MC_COL06(x) _SB_GETVALUE(x,S_BCM1480_MC_COL06,M_BCM1480_MC_COL06)#define S_BCM1480_MC_COL07 56#define M_BCM1480_MC_COL07 _SB_MAKEMASK(6,S_BCM1480_MC_COL07)#define V_BCM1480_MC_COL07(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL07)#define G_BCM1480_MC_COL07(x) _SB_GETVALUE(x,S_BCM1480_MC_COL07,M_BCM1480_MC_COL07)/* * Column Address Bit Select Register 1 (Table 87) */#define S_BCM1480_MC_COL08 0#define M_BCM1480_MC_COL08 _SB_MAKEMASK(6,S_BCM1480_MC_COL08)#define V_BCM1480_MC_COL08(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL08)#define G_BCM1480_MC_COL08(x) _SB_GETVALUE(x,S_BCM1480_MC_COL08,M_BCM1480_MC_COL08)#define S_BCM1480_MC_COL09 8#define M_BCM1480_MC_COL09 _SB_MAKEMASK(6,S_BCM1480_MC_COL09)#define V_BCM1480_MC_COL09(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL09)#define G_BCM1480_MC_COL09(x) _SB_GETVALUE(x,S_BCM1480_MC_COL09,M_BCM1480_MC_COL09)#define S_BCM1480_MC_COL10 16 /* not a valid position, must be prog as 0 */#define S_BCM1480_MC_COL11 24#define M_BCM1480_MC_COL11 _SB_MAKEMASK(6,S_BCM1480_MC_COL11)#define V_BCM1480_MC_COL11(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL11)#define G_BCM1480_MC_COL11(x) _SB_GETVALUE(x,S_BCM1480_MC_COL11,M_BCM1480_MC_COL11)#define S_BCM1480_MC_COL12 32#define M_BCM1480_MC_COL12 _SB_MAKEMASK(6,S_BCM1480_MC_COL12)#define V_BCM1480_MC_COL12(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL12)#define G_BCM1480_MC_COL12(x) _SB_GETVALUE(x,S_BCM1480_MC_COL12,M_BCM1480_MC_COL12)#define S_BCM1480_MC_COL13 40#define M_BCM1480_MC_COL13 _SB_MAKEMASK(6,S_BCM1480_MC_COL13)#define V_BCM1480_MC_COL13(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL13)#define G_BCM1480_MC_COL13(x) _SB_GETVALUE(x,S_BCM1480_MC_COL13,M_BCM1480_MC_COL13)#define S_BCM1480_MC_COL14 48#define M_BCM1480_MC_COL14 _SB_MAKEMASK(6,S_BCM1480_MC_COL14)#define V_BCM1480_MC_COL14(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL14)#define G_BCM1480_MC_COL14(x) _SB_GETVALUE(x,S_BCM1480_MC_COL14,M_BCM1480_MC_COL14)#define K_BCM1480_MC_COLX_BIT_SPACING 8/* * CS0 and CS1 Bank Address Bit Select Register (Table 88) */#define S_BCM1480_MC_CS01_BANK0 0#define M_BCM1480_MC_CS01_BANK0 _SB_MAKEMASK(6,S_BCM1480_MC_CS01_BANK0)#define V_BCM1480_MC_CS01_BANK0(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS01_BANK0)#define G_BCM1480_MC_CS01_BANK0(x) _SB_GETVALUE(x,S_BCM1480_MC_CS01_BANK0,M_BCM1480_MC_CS01_BANK0)#define S_BCM1480_MC_CS01_BANK1 8#define M_BCM1480_MC_CS01_BANK1 _SB_MAKEMASK(6,S_BCM1480_MC_CS01_BANK1)#define V_BCM1480_MC_CS01_BANK1(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS01_BANK1)#define G_BCM1480_MC_CS01_BANK1(x) _SB_GETVALUE(x,S_BCM1480_MC_CS01_BANK1,M_BCM1480_MC_CS01_BANK1)#define S_BCM1480_MC_CS01_BANK2 16#define M_BCM1480_MC_CS01_BANK2 _SB_MAKEMASK(6,S_BCM1480_MC_CS01_BANK2)#define V_BCM1480_MC_CS01_BANK2(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS01_BANK2)#define G_BCM1480_MC_CS01_BANK2(x) _SB_GETVALUE(x,S_BCM1480_MC_CS01_BANK2,M_BCM1480_MC_CS01_BANK2)/* * CS2 and CS3 Bank Address Bit Select Register (Table 89) */#define S_BCM1480_MC_CS23_BANK0 0#define M_BCM1480_MC_CS23_BANK0 _SB_MAKEMASK(6,S_BCM1480_MC_CS23_BANK0)#define V_BCM1480_MC_CS23_BANK0(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS23_BANK0)#define G_BCM1480_MC_CS23_BANK0(x) _SB_GETVALUE(x,S_BCM1480_MC_CS23_BANK0,M_BCM1480_MC_CS23_BANK0)#define S_BCM1480_MC_CS23_BANK1 8#define M_BCM1480_MC_CS23_BANK1 _SB_MAKEMASK(6,S_BCM1480_MC_CS23_BANK1)#define V_BCM1480_MC_CS23_BANK1(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS23_BANK1)#define G_BCM1480_MC_CS23_BANK1(x) _SB_GETVALUE(x,S_BCM1480_MC_CS23_BANK1,M_BCM1480_MC_CS23_BANK1)#define S_BCM1480_MC_CS23_BANK2 16#define M_BCM1480_MC_CS23_BANK2 _SB_MAKEMASK(6,S_BCM1480_MC_CS23_BANK2)#define V_BCM1480_MC_CS23_BANK2(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS23_BANK2)#define G_BCM1480_MC_CS23_BANK2(x) _SB_GETVALUE(x,S_BCM1480_MC_CS23_BANK2,M_BCM1480_MC_CS23_BANK2)#define K_BCM1480_MC_CSXX_BANKX_BIT_SPACING 8/* * DRAM Command Register (Table 90) */#define S_BCM1480_MC_COMMAND 0#define M_BCM1480_MC_COMMAND _SB_MAKEMASK(4,S_BCM1480_MC_COMMAND)#define V_BCM1480_MC_COMMAND(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COMMAND)#define G_BCM1480_MC_COMMAND(x) _SB_GETVALUE(x,S_BCM1480_MC_COMMAND,M_BCM1480_MC_COMMAND)#define K_BCM1480_MC_COMMAND_EMRS 0#define K_BCM1480_MC_COMMAND_MRS 1#define K_BCM1480_MC_COMMAND_PRE 2#define K_BCM1480_MC_COMMAND_AR 3#define K_BCM1480_MC_COMMAND_SETRFSH 4#define K_BCM1480_MC_COMMAND_CLRRFSH 5#define K_BCM1480_MC_COMMAND_SETPWRDN 6#define K_BCM1480_MC_COMMAND_CLRPWRDN 7#if SIBYTE_HDR_FEATURE(1480, PASS2)#define K_BCM1480_MC_COMMAND_EMRS2 8#define K_BCM1480_MC_COMMAND_EMRS3 9#define K_BCM1480_MC_COMMAND_ENABLE_MCLK 10#define K_BCM1480_MC_COMMAND_DISABLE_MCLK 11#endif#define V_BCM1480_MC_COMMAND_EMRS V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_EMRS)#define V_BCM1480_MC_COMMAND_MRS V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_MRS)#define V_BCM1480_MC_COMMAND_PRE V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_PRE)#define V_BCM1480_MC_COMMAND_AR V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_AR)#define V_BCM1480_MC_COMMAND_SETRFSH V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_SETRFSH)#define V_BCM1480_MC_COMMAND_CLRRFSH V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_CLRRFSH)#define V_BCM1480_MC_COMMAND_SETPWRDN V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_SETPWRDN)#define V_BCM1480_MC_COMMAND_CLRPWRDN V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_CLRPWRDN)#if SIBYTE_HDR_FEATURE(1480, PASS2)#define V_BCM1480_MC_COMMAND_EMRS2 V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_EMRS2)#define V_BCM1480_MC_COMMAND_EMRS3 V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_EMRS3)#define V_BCM1480_MC_COMMAND_ENABLE_MCLK V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_ENABLE_MCLK)#define V_BCM1480_MC_COMMAND_DISABLE_MCLK V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_DISABLE_MCLK)#endif#define S_BCM1480_MC_CS0 4#define M_BCM1480_MC_CS0 _SB_MAKEMASK1(4)#define M_BCM1480_MC_CS1 _SB_MAKEMASK1(5)#define M_BCM1480_MC_CS2 _SB_MAKEMASK1(6)#define M_BCM1480_MC_CS3 _SB_MAKEMASK1(7)#define M_BCM1480_MC_CS4 _SB_MAKEMASK1(8)#define M_BCM1480_MC_CS5 _SB_MAKEMASK1(9)#define M_BCM1480_MC_CS6 _SB_MAKEMASK1(10)#define M_BCM1480_MC_CS7 _SB_MAKEMASK1(11)#define M_BCM1480_MC_CMD_ACTIVE _SB_MAKEMASK1(16)/* * DRAM Mode Register (Table 91) */#define S_BCM1480_MC_EMODE 0#define M_BCM1480_MC_EMODE _SB_MAKEMASK(15,S_BCM1480_MC_EMODE)#define V_BCM1480_MC_EMODE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_EMODE)#define G_BCM1480_MC_EMODE(x) _SB_GETVALUE(x,S_BCM1480_MC_EMODE,M_BCM1480_MC_EMODE)#define V_BCM1480_MC_EMODE_DEFAULT V_BCM1480_MC_EMODE(0)#define S_BCM1480_MC_MODE 16#define M_BCM1480_MC_MODE _SB_MAKEMASK(15,S_BCM1480_MC_MODE)#define V_BCM1480_MC_MODE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_MODE)#define G_BCM1480_MC_MODE(x) _SB_GETVALUE(x,S_BCM1480_MC_MODE,M_BCM1480_MC_MODE)#define V_BCM1480_MC_MODE_DEFAULT V_BCM1480_MC_MODE(0)#define S_BCM1480_MC_DRAM_TYPE 32#define M_BCM1480_MC_DRAM_TYPE _SB_MAKEMASK(4,S_BCM1480_MC_DRAM_TYPE)#define V_BCM1480_MC_DRAM_TYPE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DRAM_TYPE)#define G_BCM1480_MC_DRAM_TYPE(x) _SB_GETVALUE(x,S_BCM1480_MC_DRAM_TYPE,M_BCM1480_MC_DRAM_TYPE)#define K_BCM1480_MC_DRAM_TYPE_JEDEC 0#define K_BCM1480_MC_DRAM_TYPE_FCRAM 1#if SIBYTE_HDR_FEATURE(1480, PASS2)#define K_BCM1480_MC_DRAM_TYPE_DDR2 2#endif#define V_BCM1480_MC_DRAM_TYPE_JEDEC V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_JEDEC)#define V_BCM1480_MC_DRAM_TYPE_FCRAM V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_FCRAM)#if SIBYTE_HDR_FEATURE(1480, PASS2)#define V_BCM1480_MC_DRAM_TYPE_DDR2 V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_DDR2)#endif#define M_BCM1480_MC_GANGED _SB_MAKEMASK1(36)#define M_BCM1480_MC_BY9_INTF _SB_MAKEMASK1(37)#define M_BCM1480_MC_FORCE_ECC64 _SB_MAKEMASK1(38)#define M_BCM1480_MC_ECC_DISABLE _SB_MAKEMASK1(39)#define S_BCM1480_MC_PG_POLICY 40#define M_BCM1480_MC_PG_POLICY _SB_MAKEMASK(2,S_BCM1480_MC_PG_POLICY)#define V_BCM1480_MC_PG_POLICY(x) _SB_MAKEVALUE(x,S_BCM1480_MC_PG_POLICY)#define G_BCM1480_MC_PG_POLICY(x) _SB_GETVALUE(x,S_BCM1480_MC_PG_POLICY,M_BCM1480_MC_PG_POLICY)#define K_BCM1480_MC_PG_POLICY_CLOSED 0#define K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK 1#define V_BCM1480_MC_PG_POLICY_CLOSED V_BCM1480_MC_PG_POLICY(K_BCM1480_MC_PG_POLICY_CLOSED)#define V_BCM1480_MC_PG_POLICY_CAS_TIME_CHK V_BCM1480_MC_PG_POLICY(K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK)#if SIBYTE_HDR_FEATURE(1480, PASS2)#define M_BCM1480_MC_2T_CMD _SB_MAKEMASK1(42)#define M_BCM1480_MC_ECC_COR_DIS _SB_MAKEMASK1(43)#endif#define V_BCM1480_MC_DRAMMODE_DEFAULT V_BCM1480_MC_EMODE_DEFAULT | V_BCM1480_MC_MODE_DEFAULT | V_BCM1480_MC_DRAM_TYPE_JEDEC | \ V_BCM1480_MC_PG_POLICY(K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK)/* * Memory Clock Configuration Register (Table 92) */#define S_BCM1480_MC_CLK_RATIO 0#define M_BCM1480_MC_CLK_RATIO _SB_MAKEMASK(6,S_BCM1480_MC_CLK_RATIO)#define V_BCM1480_MC_CLK_RATIO(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CLK_RATIO)#define G_BCM1480_MC_CLK_RATIO(x) _SB_GETVALUE(x,S_BCM1480_MC_CLK_RATIO,M_BCM1480_MC_CLK_RATIO)#define V_BCM1480_MC_CLK_RATIO_DEFAULT V_BCM1480_MC_CLK_RATIO(10)#define S_BCM1480_MC_REF_RATE 8#define M_BCM1480_MC_REF_RATE _SB_MAKEMASK(8,S_BCM1480_MC_REF_RATE)#define V_BCM1480_MC_REF_RATE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_REF_RATE)#define G_BCM1480_MC_REF_RATE(x) _SB_GETVALUE(x,S_BCM1480_MC_REF_RATE,M_BCM1480_MC_REF_RATE)#define K_BCM1480_MC_REF_RATE_100MHz 0x31#define K_BCM1480_MC_REF_RATE_200MHz 0x62#define K_BCM1480_MC_REF_RATE_400MHz 0xC4#define V_BCM1480_MC_REF_RATE_100MHz V_BCM1480_MC_REF_RATE(K_BCM1480_MC_REF_RATE_100MHz)#define V_BCM1480_MC_REF_RATE_200MHz V_BCM1480_MC_REF_RATE(K_BCM1480_MC_REF_RATE_200MHz)#define V_BCM1480_MC_REF_RATE_400MHz V_BCM1480_MC_REF_RATE(K_BCM1480_MC_REF_RATE_400MHz)#define V_BCM1480_MC_REF_RATE_DEFAULT V_BCM1480_MC_REF_RATE_400MHz#if SIBYTE_HDR_FEATURE(1480, PASS2)#define M_BCM1480_MC_AUTO_REF_DIS _SB_MAKEMASK1(16)#endif/* * ODT Register (Table 99) */#if SIBYTE_HDR_FEATURE(1480, PASS2)#define M_BCM1480_MC_RD_ODT0_CS0 _SB_MAKEMASK1(0)#define M_BCM1480_MC_RD_ODT0_CS2 _SB_MAKEMASK1(1)#define M_BCM1480_MC_RD_ODT0_CS4 _SB_MAKEMASK1(2)⌨️ 快捷键说明
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