riva_hw.c

linux-2.6.15.6

                    LOAD_FIXED_STATE_32BPP(nv3,PGRAPH);
                    chip->Tri03 = NULL;
                    break;
                case 8:
                default:
                    LOAD_FIXED_STATE_8BPP(nv3,PRAMIN);
                    LOAD_FIXED_STATE_8BPP(nv3,PGRAPH);
                    chip->Tri03 = NULL;
                    break;
            }
            for (i = 0x00000; i < 0x00800; i++)
                NV_WR32(&chip->PRAMIN[0x00000502 + i], 0, (i << 12) | 0x03);
            NV_WR32(chip->PGRAPH, 0x00000630, state->offset0);
            NV_WR32(chip->PGRAPH, 0x00000634, state->offset1);
            NV_WR32(chip->PGRAPH, 0x00000638, state->offset2);
            NV_WR32(chip->PGRAPH, 0x0000063C, state->offset3);
            NV_WR32(chip->PGRAPH, 0x00000650, state->pitch0);
            NV_WR32(chip->PGRAPH, 0x00000654, state->pitch1);
            NV_WR32(chip->PGRAPH, 0x00000658, state->pitch2);
            NV_WR32(chip->PGRAPH, 0x0000065C, state->pitch3);
            break;
        case NV_ARCH_04:
            /*
             * Make sure frame buffer config gets set before loading PRAMIN.
             */
            NV_WR32(chip->PFB, 0x00000200, state->config);
            LOAD_FIXED_STATE(nv4,PFIFO);
            LOAD_FIXED_STATE(nv4,PRAMIN);
            LOAD_FIXED_STATE(nv4,PGRAPH);
            switch (state->bpp)
            {
                case 15:
                    LOAD_FIXED_STATE_15BPP(nv4,PRAMIN);
                    LOAD_FIXED_STATE_15BPP(nv4,PGRAPH);
                    chip->Tri03 = (RivaTexturedTriangle03  __iomem *)&(chip->FIFO[0x0000E000/4]);
                    break;
                case 16:
                    LOAD_FIXED_STATE_16BPP(nv4,PRAMIN);
                    LOAD_FIXED_STATE_16BPP(nv4,PGRAPH);
                    chip->Tri03 = (RivaTexturedTriangle03  __iomem *)&(chip->FIFO[0x0000E000/4]);
                    break;
                case 24:
                case 32:
                    LOAD_FIXED_STATE_32BPP(nv4,PRAMIN);
                    LOAD_FIXED_STATE_32BPP(nv4,PGRAPH);
                    chip->Tri03 = NULL;
                    break;
                case 8:
                default:
                    LOAD_FIXED_STATE_8BPP(nv4,PRAMIN);
                    LOAD_FIXED_STATE_8BPP(nv4,PGRAPH);
                    chip->Tri03 = NULL;
                    break;
            }
            NV_WR32(chip->PGRAPH, 0x00000640, state->offset0);
            NV_WR32(chip->PGRAPH, 0x00000644, state->offset1);
            NV_WR32(chip->PGRAPH, 0x00000648, state->offset2);
            NV_WR32(chip->PGRAPH, 0x0000064C, state->offset3);
            NV_WR32(chip->PGRAPH, 0x00000670, state->pitch0);
            NV_WR32(chip->PGRAPH, 0x00000674, state->pitch1);
            NV_WR32(chip->PGRAPH, 0x00000678, state->pitch2);
            NV_WR32(chip->PGRAPH, 0x0000067C, state->pitch3);
            break;
        case NV_ARCH_10:
        case NV_ARCH_20:
        case NV_ARCH_30:
            if(chip->twoHeads) {
               VGA_WR08(chip->PCIO, 0x03D4, 0x44);
               VGA_WR08(chip->PCIO, 0x03D5, state->crtcOwner);
               chip->LockUnlock(chip, 0);
            }

            LOAD_FIXED_STATE(nv10,PFIFO);
            LOAD_FIXED_STATE(nv10,PRAMIN);
            LOAD_FIXED_STATE(nv10,PGRAPH);
            switch (state->bpp)
            {
                case 15:
                    LOAD_FIXED_STATE_15BPP(nv10,PRAMIN);
                    LOAD_FIXED_STATE_15BPP(nv10,PGRAPH);
                    chip->Tri03 = (RivaTexturedTriangle03  __iomem *)&(chip->FIFO[0x0000E000/4]);
                    break;
                case 16:
                    LOAD_FIXED_STATE_16BPP(nv10,PRAMIN);
                    LOAD_FIXED_STATE_16BPP(nv10,PGRAPH);
                    chip->Tri03 = (RivaTexturedTriangle03  __iomem *)&(chip->FIFO[0x0000E000/4]);
                    break;
                case 24:
                case 32:
                    LOAD_FIXED_STATE_32BPP(nv10,PRAMIN);
                    LOAD_FIXED_STATE_32BPP(nv10,PGRAPH);
                    chip->Tri03 = NULL;
                    break;
                case 8:
                default:
                    LOAD_FIXED_STATE_8BPP(nv10,PRAMIN);
                    LOAD_FIXED_STATE_8BPP(nv10,PGRAPH);
                    chip->Tri03 = NULL;
                    break;
            }

            if(chip->Architecture == NV_ARCH_10) {
                NV_WR32(chip->PGRAPH, 0x00000640, state->offset0);
                NV_WR32(chip->PGRAPH, 0x00000644, state->offset1);
                NV_WR32(chip->PGRAPH, 0x00000648, state->offset2);
                NV_WR32(chip->PGRAPH, 0x0000064C, state->offset3);
                NV_WR32(chip->PGRAPH, 0x00000670, state->pitch0);
                NV_WR32(chip->PGRAPH, 0x00000674, state->pitch1);
                NV_WR32(chip->PGRAPH, 0x00000678, state->pitch2);
                NV_WR32(chip->PGRAPH, 0x0000067C, state->pitch3);
                NV_WR32(chip->PGRAPH, 0x00000680, state->pitch3);
        } else {
        NV_WR32(chip->PGRAPH, 0x00000820, state->offset0);
        NV_WR32(chip->PGRAPH, 0x00000824, state->offset1);
        NV_WR32(chip->PGRAPH, 0x00000828, state->offset2);
        NV_WR32(chip->PGRAPH, 0x0000082C, state->offset3);
        NV_WR32(chip->PGRAPH, 0x00000850, state->pitch0);
        NV_WR32(chip->PGRAPH, 0x00000854, state->pitch1);
        NV_WR32(chip->PGRAPH, 0x00000858, state->pitch2);
        NV_WR32(chip->PGRAPH, 0x0000085C, state->pitch3);
        NV_WR32(chip->PGRAPH, 0x00000860, state->pitch3);
        NV_WR32(chip->PGRAPH, 0x00000864, state->pitch3);
        NV_WR32(chip->PGRAPH, 0x000009A4, NV_RD32(chip->PFB, 0x00000200));
        NV_WR32(chip->PGRAPH, 0x000009A8, NV_RD32(chip->PFB, 0x00000204));
        }
            if(chip->twoHeads) {
               NV_WR32(chip->PCRTC0, 0x00000860, state->head);
               NV_WR32(chip->PCRTC0, 0x00002860, state->head2);
            }
            NV_WR32(chip->PRAMDAC, 0x00000404, NV_RD32(chip->PRAMDAC, 0x00000404) | (1 << 25));

            NV_WR32(chip->PMC, 0x00008704, 1);
            NV_WR32(chip->PMC, 0x00008140, 0);
            NV_WR32(chip->PMC, 0x00008920, 0);
            NV_WR32(chip->PMC, 0x00008924, 0);
            NV_WR32(chip->PMC, 0x00008908, 0x01ffffff);
            NV_WR32(chip->PMC, 0x0000890C, 0x01ffffff);
            NV_WR32(chip->PMC, 0x00001588, 0);

            NV_WR32(chip->PFB, 0x00000240, 0);
            NV_WR32(chip->PFB, 0x00000250, 0);
            NV_WR32(chip->PFB, 0x00000260, 0);
            NV_WR32(chip->PFB, 0x00000270, 0);
            NV_WR32(chip->PFB, 0x00000280, 0);
            NV_WR32(chip->PFB, 0x00000290, 0);
            NV_WR32(chip->PFB, 0x000002A0, 0);
            NV_WR32(chip->PFB, 0x000002B0, 0);

            NV_WR32(chip->PGRAPH, 0x00000B00, NV_RD32(chip->PFB, 0x00000240));
            NV_WR32(chip->PGRAPH, 0x00000B04, NV_RD32(chip->PFB, 0x00000244));
            NV_WR32(chip->PGRAPH, 0x00000B08, NV_RD32(chip->PFB, 0x00000248));
            NV_WR32(chip->PGRAPH, 0x00000B0C, NV_RD32(chip->PFB, 0x0000024C));
            NV_WR32(chip->PGRAPH, 0x00000B10, NV_RD32(chip->PFB, 0x00000250));
            NV_WR32(chip->PGRAPH, 0x00000B14, NV_RD32(chip->PFB, 0x00000254));
            NV_WR32(chip->PGRAPH, 0x00000B18, NV_RD32(chip->PFB, 0x00000258));
            NV_WR32(chip->PGRAPH, 0x00000B1C, NV_RD32(chip->PFB, 0x0000025C));
            NV_WR32(chip->PGRAPH, 0x00000B20, NV_RD32(chip->PFB, 0x00000260));
            NV_WR32(chip->PGRAPH, 0x00000B24, NV_RD32(chip->PFB, 0x00000264));
            NV_WR32(chip->PGRAPH, 0x00000B28, NV_RD32(chip->PFB, 0x00000268));
            NV_WR32(chip->PGRAPH, 0x00000B2C, NV_RD32(chip->PFB, 0x0000026C));
            NV_WR32(chip->PGRAPH, 0x00000B30, NV_RD32(chip->PFB, 0x00000270));
            NV_WR32(chip->PGRAPH, 0x00000B34, NV_RD32(chip->PFB, 0x00000274));
            NV_WR32(chip->PGRAPH, 0x00000B38, NV_RD32(chip->PFB, 0x00000278));
            NV_WR32(chip->PGRAPH, 0x00000B3C, NV_RD32(chip->PFB, 0x0000027C));
            NV_WR32(chip->PGRAPH, 0x00000B40, NV_RD32(chip->PFB, 0x00000280));
            NV_WR32(chip->PGRAPH, 0x00000B44, NV_RD32(chip->PFB, 0x00000284));
            NV_WR32(chip->PGRAPH, 0x00000B48, NV_RD32(chip->PFB, 0x00000288));
            NV_WR32(chip->PGRAPH, 0x00000B4C, NV_RD32(chip->PFB, 0x0000028C));
            NV_WR32(chip->PGRAPH, 0x00000B50, NV_RD32(chip->PFB, 0x00000290));
            NV_WR32(chip->PGRAPH, 0x00000B54, NV_RD32(chip->PFB, 0x00000294));
            NV_WR32(chip->PGRAPH, 0x00000B58, NV_RD32(chip->PFB, 0x00000298));
            NV_WR32(chip->PGRAPH, 0x00000B5C, NV_RD32(chip->PFB, 0x0000029C));
            NV_WR32(chip->PGRAPH, 0x00000B60, NV_RD32(chip->PFB, 0x000002A0));
            NV_WR32(chip->PGRAPH, 0x00000B64, NV_RD32(chip->PFB, 0x000002A4));
            NV_WR32(chip->PGRAPH, 0x00000B68, NV_RD32(chip->PFB, 0x000002A8));
            NV_WR32(chip->PGRAPH, 0x00000B6C, NV_RD32(chip->PFB, 0x000002AC));
            NV_WR32(chip->PGRAPH, 0x00000B70, NV_RD32(chip->PFB, 0x000002B0));
            NV_WR32(chip->PGRAPH, 0x00000B74, NV_RD32(chip->PFB, 0x000002B4));
            NV_WR32(chip->PGRAPH, 0x00000B78, NV_RD32(chip->PFB, 0x000002B8));
            NV_WR32(chip->PGRAPH, 0x00000B7C, NV_RD32(chip->PFB, 0x000002BC));
            NV_WR32(chip->PGRAPH, 0x00000F40, 0x10000000);
            NV_WR32(chip->PGRAPH, 0x00000F44, 0x00000000);
            NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000040);
            NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000008);
            NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000200);
            for (i = 0; i < (3*16); i++)
                NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
            NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000040);
            NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
            NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000800);
            for (i = 0; i < (16*16); i++)
                NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
            NV_WR32(chip->PGRAPH, 0x00000F40, 0x30000000);
            NV_WR32(chip->PGRAPH, 0x00000F44, 0x00000004);
            NV_WR32(chip->PGRAPH, 0x00000F50, 0x00006400);
            for (i = 0; i < (59*4); i++)
                NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
            NV_WR32(chip->PGRAPH, 0x00000F50, 0x00006800);
            for (i = 0; i < (47*4); i++)
                NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
            NV_WR32(chip->PGRAPH, 0x00000F50, 0x00006C00);
            for (i = 0; i < (3*4); i++)
                NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
            NV_WR32(chip->PGRAPH, 0x00000F50, 0x00007000);
            for (i = 0; i < (19*4); i++)
                NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
            NV_WR32(chip->PGRAPH, 0x00000F50, 0x00007400);
            for (i = 0; i < (12*4); i++)
                NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
            NV_WR32(chip->PGRAPH, 0x00000F50, 0x00007800);
            for (i = 0; i < (12*4); i++)
                NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
            NV_WR32(chip->PGRAPH, 0x00000F50, 0x00004400);
            for (i = 0; i < (8*4); i++)
                NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
            NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000000);
            for (i = 0; i < 16; i++)
                NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
            NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000040);
            for (i = 0; i < 4; i++)
                NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);

            NV_WR32(chip->PCRTC, 0x00000810, state->cursorConfig);

            if(chip->flatPanel) {
               if((chip->Chipset & 0x0ff0) == 0x0110) {
                   NV_WR32(chip->PRAMDAC, 0x0528, state->dither);
               } else 
               if((chip->Chipset & 0x0ff0) >= 0x0170) {
                   NV_WR32(chip->PRAMDAC, 0x083C, state->dither);
               }
            
               VGA_WR08(chip->PCIO, 0x03D4, 0x53);
               VGA_WR08(chip->PCIO, 0x03D5, 0);
               VGA_WR08(chip->PCIO, 0x03D4, 0x54);
               VGA_WR08(chip->PCIO, 0x03D5, 0);
               VGA_WR08(chip->PCIO, 0x03D4, 0x21);
               VGA_WR08(chip->PCIO, 0x03D5, 0xfa);
            }

            VGA_WR08(chip->PCIO, 0x03D4, 0x41);
            VGA_WR08(chip->PCIO, 0x03D5, state->extra);
    }
    LOAD_FIXED_STATE(Riva,FIFO);
    UpdateFifoState(chip);
    /*
     * Load HW mode state.
     */
    VGA_WR08(chip->PCIO, 0x03D4, 0x19);
    VGA_WR08(chip->PCIO, 0x03D5, state->repaint0);
    VGA_WR08(chip->PCIO, 0x03D4, 0x1A);
    VGA_WR08(chip->PCIO, 0x03D5, state->repaint1);
    VGA_WR08(chip->PCIO, 0x03D4, 0x25);
    VGA_WR08(chip->PCIO, 0x03D5, state->screen);
    VGA_WR08(chip->PCIO, 0x03D4, 0x28);
    VGA_WR08(chip->PCIO, 0x03D5, state->pixel);
    VGA_WR08(chip->PCIO, 0x03D4, 0x2D);
    VGA_WR08(chip->PCIO, 0x03D5, state->horiz);
    VGA_WR08(chip->PCIO, 0x03D4, 0x1B);
    VGA_WR08(chip->PCIO, 0x03D5, state->arbitration0);
    VGA_WR08(chip->PCIO, 0x03D4, 0x20);
    VGA_WR08(chip->PCIO, 0x03D5, state->arbitration1);
    VGA_WR08(chip->PCIO, 0x03D4, 0x30);
    VGA_WR08(chip->PCIO, 0x03D5, state->cursor0);
    VGA_WR08(chip->PCIO, 0x03D4, 0x31);
    VGA_WR08(chip->PCIO, 0x03D5, state->cursor1);
    VGA_WR08(chip->PCIO, 0x03D4, 0x2F);
    VGA_WR08(chip->PCIO, 0x03D5, state->cursor2);
    VGA_WR08(chip->PCIO, 0x03D4, 0x39);
    VGA_WR08(chip->PCIO, 0x03D5, state->interlace);

    if(!chip->flatPanel) {
       NV_WR32(chip->PRAMDAC0, 0x00000508, state->vpll);
       NV_WR32(chip->PRAMDAC0, 0x0000050C, state->pllsel);
       if(chip->twoHeads)
          NV_WR32(chip->PRAMDAC0, 0x00000520, state->vpll2);
    }  else {
       NV_WR32(chip->PRAMDAC, 0x00000848 , state->scale);
    }  
    NV_WR32(chip->PRAMDAC, 0x00000600 , state->general);

    /*
     * Turn off VBlank enable and reset.
     */
    NV_WR32(chip->PCRTC, 0x00000140, 0);
    NV_WR32(chip->PCRTC, 0x00000100, chip->VBlankBit);
    /*
     * Set interrupt enable.
     */    
    NV_WR32(chip->PMC, 0x00000140, chip->EnableIRQ & 0x01);
    /*
     * Set current state pointer.
     */
    chip->CurrentState = state;
    /*
     * Reset FIFO free and empty counts.
     */
    chip->FifoFreeCount  = 0;
    /* Free count from first subchannel */
    chip->FifoEmptyCount = NV_RD32(&chip->Rop->FifoFree, 0);
}
static void UnloadStateExt
(
    RIVA_HW_INST  *chip,
    RIVA_HW_STATE *state
)
{
    /*
     * Save current HW state.
     */
    VGA_WR08(chip->PCIO, 0x03D4, 0x19);
    state->repaint0     = VGA_RD08(chip->PCIO, 0x03D5);
    VGA_WR08(chip->PCIO, 0x03D4, 0x1A);
    state->repaint1     = VGA_RD08(chip->PCIO, 0x03D5);
    VGA_WR08(chip->PCIO, 0x03D4, 0x25);
    state->screen       = VGA_RD08(chip->PCIO, 0x03D5);
    VGA_WR08(chip->PCIO, 0x03D4, 0x28);
    state->pixel        = VGA_RD08(chip->PCIO, 0x03D5);
    VGA_WR08(chip->PCIO, 0x03D4, 0x2D);
    state->horiz        = VGA_RD08(chip->PCIO, 0x03D5);
    VGA_WR08(chip->PCIO, 0x03D4, 0x1B);
    state->arbitration0 = VGA_RD08(chip->PCIO, 0x03D5);
    VGA_WR08(chip->PCIO, 0x03D4, 0x20);
    state->arbitration1 = VGA_RD08(chip->PCIO, 0x03D5);
    VGA_WR08(chip->PCIO, 0x03D4, 0x30);
    state->cursor0      = VGA_RD08(chip->PCIO, 0x03D5);
    VGA_WR08(chip->PCIO, 0x03D4, 0x31);
    state->cursor1      = VGA_RD08(chip->PCIO, 0x03D5);
    VGA_WR08(chip->PCIO, 0x03D4, 0x2F);
    state->cursor2      = VGA_RD08(chip->PCIO, 0x03D5);
    VGA_WR08(chip->PCIO, 0x03D4, 0x39);
    state->interlace    = VGA_RD08(chip->PCIO, 0x03D5);
    state->vpll         = NV_RD32(chip->PRAMDAC0, 0x00000508);
    state->vpll2        = NV_RD32(chip->PRAMDAC0, 0x00000520);
    state->pllsel       = NV_RD32(chip->PRAMDAC0, 0x0000050C);
    state->general      = NV_RD32(chip->PRAMDAC, 0x00000600);
    state->scale        = NV_RD32(chip->PRAMDAC, 0x00000848);
    state->config       = NV_RD32(chip->PFB, 0x00000200);
    switch (chip->Architecture)
    {
        case NV_ARCH_03:
            state->offset0  = NV_RD32(chip->PGRAPH, 0x00000630);
            state->offset1  = NV_RD32(chip->PGRAPH, 0x00000634);
            state->offset2  = NV_RD32(chip->PGRAPH, 0x00000638);
            state->offset3  = NV_RD32(chip->PGRAPH, 0x0000063C);
            state->pitch0   = NV_RD32(chip->PGRAPH, 0x00000650);
            state->pitch1   = NV_RD32(chip->PGRAPH, 0x00000654);
            state->pitch2   = NV_RD32(chip->PGRAPH, 0x00000658);
            state->pitch3   = NV_RD32(chip->PGRAPH, 0x0000065C);
            break;
        case NV_ARCH_04:
            state->offset0  = NV_RD32(chip->PGRAPH, 0x00000640);
            state->offset1  = NV_RD32(chip->PGRAPH, 0x00000644);
            state->offset2  = NV_RD32(chip->PGRAPH, 0x00000648);
            state->offset3  = NV_RD32(chip->PGRAPH, 0x0000064C);
            state->pitch0   = NV_RD32(chip->