intelfbhw.h

linux-2.6.15.6

#ifndef _INTELFBHW_H
#define _INTELFBHW_H

/* $DHD: intelfb/intelfbhw.h,v 1.5 2003/06/27 15:06:25 dawes Exp $ */


/*** HW-specific data ***/

/* Information about the 852GM/855GM variants */
#define INTEL_85X_CAPID		0x44
#define INTEL_85X_VARIANT_MASK		0x7
#define INTEL_85X_VARIANT_SHIFT		5
#define INTEL_VAR_855GME		0x0
#define INTEL_VAR_855GM			0x4
#define INTEL_VAR_852GME		0x2
#define INTEL_VAR_852GM			0x5

/* Information about DVO/LVDS Ports */
#define DVOA_PORT  0x1
#define DVOB_PORT  0x2
#define DVOC_PORT  0x4
#define LVDS_PORT  0x8

/*
 * The Bridge device's PCI config space has information about the
 * fb aperture size and the amount of pre-reserved memory.
 */
#define INTEL_GMCH_CTRL		0x52
#define INTEL_GMCH_ENABLED		0x4
#define INTEL_GMCH_MEM_MASK		0x1
#define INTEL_GMCH_MEM_64M		0x1
#define INTEL_GMCH_MEM_128M		0

#define INTEL_830_GMCH_GMS_MASK		(0x7 << 4)
#define INTEL_830_GMCH_GMS_DISABLED	(0x0 << 4)
#define INTEL_830_GMCH_GMS_LOCAL	(0x1 << 4)
#define INTEL_830_GMCH_GMS_STOLEN_512	(0x2 << 4)
#define INTEL_830_GMCH_GMS_STOLEN_1024	(0x3 << 4)
#define INTEL_830_GMCH_GMS_STOLEN_8192	(0x4 << 4)

#define INTEL_855_GMCH_GMS_MASK		(0x7 << 4)
#define INTEL_855_GMCH_GMS_DISABLED	(0x0 << 4)
#define INTEL_855_GMCH_GMS_STOLEN_1M	(0x1 << 4)
#define INTEL_855_GMCH_GMS_STOLEN_4M	(0x2 << 4)
#define INTEL_855_GMCH_GMS_STOLEN_8M	(0x3 << 4)
#define INTEL_855_GMCH_GMS_STOLEN_16M	(0x4 << 4)
#define INTEL_855_GMCH_GMS_STOLEN_32M	(0x5 << 4)

#define INTEL_915G_GMCH_GMS_STOLEN_48M	(0x6 << 4)
#define INTEL_915G_GMCH_GMS_STOLEN_64M	(0x7 << 4)

/* HW registers */

/* Fence registers */
#define FENCE			0x2000
#define FENCE_NUM			8

/* Primary ring buffer */
#define PRI_RING_TAIL		0x2030
#define RING_TAIL_MASK			0x001ffff8
#define RING_INUSE			0x1

#define PRI_RING_HEAD		0x2034
#define RING_HEAD_WRAP_MASK		0x7ff
#define RING_HEAD_WRAP_SHIFT		21
#define RING_HEAD_MASK			0x001ffffc

#define PRI_RING_START		0x2038
#define RING_START_MASK			0xfffff000

#define PRI_RING_LENGTH		0x203c
#define RING_LENGTH_MASK		0x001ff000
#define RING_REPORT_MASK		(0x3 << 1)
#define RING_NO_REPORT			(0x0 << 1)
#define RING_REPORT_64K			(0x1 << 1)
#define RING_REPORT_4K			(0x2 << 1)
#define RING_REPORT_128K		(0x3 << 1)
#define RING_ENABLE			0x1

/*
 * Tail can't wrap to any closer than RING_MIN_FREE bytes of the head,
 * and the last RING_MIN_FREE bytes need to be padded with MI_NOOP
 */
#define RING_MIN_FREE			64

#define IPEHR     		0x2088

#define INSTDONE		0x2090
#define PRI_RING_EMPTY			1

#define INSTPM			0x20c0
#define SYNC_FLUSH_ENABLE		(1 << 5)

#define INSTPS			0x20c4

#define MEM_MODE		0x20cc

#define MASK_SHIFT			16

#define FW_BLC_0		0x20d8
#define FW_DISPA_WM_SHIFT		0
#define FW_DISPA_WM_MASK		0x3f
#define FW_DISPA_BL_SHIFT		8
#define FW_DISPA_BL_MASK		0xf
#define FW_DISPB_WM_SHIFT		16
#define FW_DISPB_WM_MASK		0x1f
#define FW_DISPB_BL_SHIFT		24
#define FW_DISPB_BL_MASK		0x7

#define FW_BLC_1		0x20dc
#define FW_DISPC_WM_SHIFT		0
#define FW_DISPC_WM_MASK		0x1f
#define FW_DISPC_BL_SHIFT		8
#define FW_DISPC_BL_MASK		0x7


/* PLL registers */
#define VGA0_DIVISOR		0x06000
#define VGA1_DIVISOR		0x06004
#define VGAPD			0x06010
#define VGAPD_0_P1_SHIFT		0
#define VGAPD_0_P1_FORCE_DIV2		(1 << 5)
#define VGAPD_0_P2_SHIFT		7
#define VGAPD_1_P1_SHIFT		8
#define VGAPD_1_P1_FORCE_DIV2		(1 << 13)
#define VGAPD_1_P2_SHIFT		15

#define DPLL_A			0x06014
#define DPLL_B			0x06018
#define DPLL_VCO_ENABLE			(1 << 31)
#define DPLL_2X_CLOCK_ENABLE		(1 << 30)
#define DPLL_SYNCLOCK_ENABLE		(1 << 29)
#define DPLL_VGA_MODE_DISABLE		(1 << 28)
#define DPLL_P2_MASK			1
#define DPLL_P2_SHIFT			23
#define DPLL_P1_FORCE_DIV2		(1 << 21)
#define DPLL_P1_MASK			0x1f
#define DPLL_P1_SHIFT			16
#define DPLL_REFERENCE_SELECT_MASK	(0x3 << 13)
#define DPLL_REFERENCE_DEFAULT		(0x0 << 13)
#define DPLL_REFERENCE_TVCLK		(0x2 << 13)
#define DPLL_RATE_SELECT_MASK		(1 << 8)
#define DPLL_RATE_SELECT_FP0		(0 << 8)
#define DPLL_RATE_SELECT_FP1		(1 << 8)

#define FPA0			0x06040
#define FPA1			0x06044
#define FPB0			0x06048
#define FPB1			0x0604c
#define FP_DIVISOR_MASK			0x3f
#define FP_N_DIVISOR_SHIFT		16
#define FP_M1_DIVISOR_SHIFT		8
#define FP_M2_DIVISOR_SHIFT		0

/* PLL parameters (these are for 852GM/855GM/865G, check earlier chips). */
/* Clock values are in units of kHz */
#define PLL_REFCLK		48000
#define MIN_VCO_FREQ		930000
#define MAX_VCO_FREQ		1400000
#define MIN_CLOCK		25000
#define MAX_CLOCK		350000
#define P_TRANSITION_CLOCK	165000
#define MIN_M			108
#define MAX_M			140
#define MIN_M1			18
#define MAX_M1			26
#define MIN_M2			6
#define MAX_M2			16
#define MIN_P			4
#define MAX_P			128
#define MIN_P1			0
#define MAX_P1			31
#define MIN_N			3
#define MAX_N			16

#define CALC_VCLOCK(m1, m2, n, p1, p2) \
        ((PLL_REFCLK * (5 * ((m1) + 2) + ((m2) + 2)) / ((n) + 2)) / \
        (((p1) + 2) * (1 << (p2 + 1))))

#define CALC_VCLOCK3(m, n, p)	((PLL_REFCLK * (m) / (n)) / (p))

/* Two pipes */
#define PIPE_A			0
#define PIPE_B			1
#define PIPE_MASK		1

/* palette registers */
#define PALETTE_A		0x0a000
#define PALETTE_B		0x0a800
#ifndef PALETTE_8_ENTRIES
#define PALETTE_8_ENTRIES		256
#endif
#define PALETTE_8_SIZE			(PALETTE_8_ENTRIES * 4)
#define PALETTE_10_ENTRIES		128
#define PALETTE_10_SIZE			(PALETTE_10_ENTRIES * 8)
#define PALETTE_8_MASK			0xff
#define PALETTE_8_RED_SHIFT		16
#define PALETTE_8_GREEN_SHIFT		8
#define PALETTE_8_BLUE_SHIFT		0

/* CRTC registers */
#define HTOTAL_A		0x60000
#define HBLANK_A		0x60004
#define HSYNC_A			0x60008
#define VTOTAL_A		0x6000c
#define VBLANK_A		0x60010
#define VSYNC_A			0x60014
#define SRC_SIZE_A		0x6001c
#define BCLRPAT_A		0x60020

#define HTOTAL_B		0x61000
#define HBLANK_B		0x61004
#define HSYNC_B			0x61008
#define VTOTAL_B		0x6100c
#define VBLANK_B		0x61010
#define VSYNC_B			0x61014
#define SRC_SIZE_B		0x6101c
#define BCLRPAT_B		0x61020

#define HTOTAL_MASK			0xfff
#define HTOTAL_SHIFT			16
#define HACTIVE_MASK			0x7ff
#define HACTIVE_SHIFT			0
#define HBLANKEND_MASK			0xfff
#define HBLANKEND_SHIFT			16
#define HBLANKSTART_MASK		0xfff
#define HBLANKSTART_SHIFT		0
#define HSYNCEND_MASK			0xfff
#define HSYNCEND_SHIFT			16
#define HSYNCSTART_MASK			0xfff
#define HSYNCSTART_SHIFT		0
#define VTOTAL_MASK			0xfff
#define VTOTAL_SHIFT			16
#define VACTIVE_MASK			0x7ff
#define VACTIVE_SHIFT			0
#define VBLANKEND_MASK			0xfff
#define VBLANKEND_SHIFT			16
#define VBLANKSTART_MASK		0xfff
#define VBLANKSTART_SHIFT		0
#define VSYNCEND_MASK			0xfff
#define VSYNCEND_SHIFT			16
#define VSYNCSTART_MASK			0xfff
#define VSYNCSTART_SHIFT		0
#define SRC_SIZE_HORIZ_MASK		0x7ff
#define SRC_SIZE_HORIZ_SHIFT		16
#define SRC_SIZE_VERT_MASK		0x7ff
#define SRC_SIZE_VERT_SHIFT		0

#define ADPA			0x61100
#define ADPA_DAC_ENABLE			(1 << 31)
#define ADPA_DAC_DISABLE		0
#define ADPA_PIPE_SELECT_SHIFT		30
#define ADPA_USE_VGA_HVPOLARITY		(1 << 15)
#define ADPA_SETS_HVPOLARITY		0
#define ADPA_DPMS_CONTROL_MASK		(0x3 << 10)
#define ADPA_DPMS_D0			(0x0 << 10)
#define ADPA_DPMS_D2			(0x1 << 10)
#define ADPA_DPMS_D1			(0x2 << 10)
#define ADPA_DPMS_D3			(0x3 << 10)
#define ADPA_VSYNC_ACTIVE_SHIFT		4
#define ADPA_HSYNC_ACTIVE_SHIFT		3
#define ADPA_SYNC_ACTIVE_MASK		1
#define ADPA_SYNC_ACTIVE_HIGH		1
#define ADPA_SYNC_ACTIVE_LOW		0

#define DVOA			0x61120
#define DVOB			0x61140
#define DVOC			0x61160
#define LVDS			0x61180
#define PORT_ENABLE		        (1 << 31)
#define PORT_PIPE_SELECT_SHIFT	        30
#define PORT_TV_FLAGS_MASK              0xFF
#define PORT_TV_FLAGS                   0xC4  // ripped from my BIOS
                                              // to understand and correct

#define DVOA_SRCDIM		0x61124
#define DVOB_SRCDIM		0x61144
#define DVOC_SRCDIM		0x61164

#define PIPEACONF		0x70008
#define PIPEBCONF		0x71008
#define PIPECONF_ENABLE			(1 << 31)
#define PIPECONF_DISABLE		0
#define PIPECONF_DOUBLE_WIDE		(1 << 30)
#define PIPECONF_SINGLE_WIDE		0
#define PIPECONF_LOCKED			(1 << 25)