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📄 i2c-pxa.c

📁 linux-2.6.15.6
💻 C
📖 第 1 页 / 共 2 页
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	if (i2c_debug > 0)		dev_dbg(&i2c->adap.dev, "SAD, mode is slave-%cx\n",		       (isr & ISR_RWM) ? 'r' : 't');	if (i2c->slave != NULL)		i2c->slave->event(i2c->slave->data,				 (isr & ISR_RWM) ? I2C_SLAVE_EVENT_START_READ : I2C_SLAVE_EVENT_START_WRITE);	/*	 * slave could interrupt in the middle of us generating a	 * start condition... if this happens, we'd better back off	 * and stop holding the poor thing up	 */	ICR &= ~(ICR_START|ICR_STOP);	ICR |= ICR_TB;	timeout = 0x10000;	while (1) {		if ((IBMR & 2) == 2)			break;		timeout--;		if (timeout <= 0) {			dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");			break;		}	}	ICR &= ~ICR_SCLE;}static void i2c_pxa_slave_stop(struct pxa_i2c *i2c){	if (i2c_debug > 2)		dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop)\n");	if (i2c->slave != NULL)		i2c->slave->event(i2c->slave->data, I2C_SLAVE_EVENT_STOP);	if (i2c_debug > 2)		dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop) acked\n");	/*	 * If we have a master-mode message waiting,	 * kick it off now that the slave has completed.	 */	if (i2c->msg)		i2c_pxa_master_complete(i2c, I2C_RETRY);}#elsestatic void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr){	if (isr & ISR_BED) {		/* what should we do here? */	} else {		IDBR = 0;		ICR |= ICR_TB;	}}static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr){	ICR |= ICR_TB | ICR_ACKNAK;}static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr){	int timeout;	/*	 * slave could interrupt in the middle of us generating a	 * start condition... if this happens, we'd better back off	 * and stop holding the poor thing up	 */	ICR &= ~(ICR_START|ICR_STOP);	ICR |= ICR_TB | ICR_ACKNAK;	timeout = 0x10000;	while (1) {		if ((IBMR & 2) == 2)			break;		timeout--;		if (timeout <= 0) {			dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");			break;		}	}	ICR &= ~ICR_SCLE;}static void i2c_pxa_slave_stop(struct pxa_i2c *i2c){	if (i2c->msg)		i2c_pxa_master_complete(i2c, I2C_RETRY);}#endif/* * PXA I2C Master mode */static inline unsigned int i2c_pxa_addr_byte(struct i2c_msg *msg){	unsigned int addr = (msg->addr & 0x7f) << 1;	if (msg->flags & I2C_M_RD)		addr |= 1;	return addr;}static inline void i2c_pxa_start_message(struct pxa_i2c *i2c){	u32 icr;	/*	 * Step 1: target slave address into IDBR	 */	IDBR = i2c_pxa_addr_byte(i2c->msg);	/*	 * Step 2: initiate the write.	 */	icr = ICR & ~(ICR_STOP | ICR_ALDIE);	ICR = icr | ICR_START | ICR_TB;}/* * We are protected by the adapter bus semaphore. */static int i2c_pxa_do_xfer(struct pxa_i2c *i2c, struct i2c_msg *msg, int num){	long timeout;	int ret;	/*	 * Wait for the bus to become free.	 */	ret = i2c_pxa_wait_bus_not_busy(i2c);	if (ret) {		dev_err(&i2c->adap.dev, "i2c_pxa: timeout waiting for bus free\n");		goto out;	}	/*	 * Set master mode.	 */	ret = i2c_pxa_set_master(i2c);	if (ret) {		dev_err(&i2c->adap.dev, "i2c_pxa_set_master: error %d\n", ret);		goto out;	}	spin_lock_irq(&i2c->lock);	i2c->msg = msg;	i2c->msg_num = num;	i2c->msg_idx = 0;	i2c->msg_ptr = 0;	i2c->irqlogidx = 0;	i2c_pxa_start_message(i2c);	spin_unlock_irq(&i2c->lock);	/*	 * The rest of the processing occurs in the interrupt handler.	 */	timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);	/*	 * We place the return code in i2c->msg_idx.	 */	ret = i2c->msg_idx;	if (timeout == 0)		i2c_pxa_scream_blue_murder(i2c, "timeout"); out:	return ret;}/* * i2c_pxa_master_complete - complete the message and wake up. */static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret){	i2c->msg_ptr = 0;	i2c->msg = NULL;	i2c->msg_idx ++;	i2c->msg_num = 0;	if (ret)		i2c->msg_idx = ret;	wake_up(&i2c->wait);}static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr){	u32 icr = ICR & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB); again:	/*	 * If ISR_ALD is set, we lost arbitration.	 */	if (isr & ISR_ALD) {		/*		 * Do we need to do anything here?  The PXA docs		 * are vague about what happens.		 */		i2c_pxa_scream_blue_murder(i2c, "ALD set");		/*		 * We ignore this error.  We seem to see spurious ALDs		 * for seemingly no reason.  If we handle them as I think		 * they should, we end up causing an I2C error, which		 * is painful for some systems.		 */		return; /* ignore */	}	if (isr & ISR_BED) {		int ret = BUS_ERROR;		/*		 * I2C bus error - either the device NAK'd us, or		 * something more serious happened.  If we were NAK'd		 * on the initial address phase, we can retry.		 */		if (isr & ISR_ACKNAK) {			if (i2c->msg_ptr == 0 && i2c->msg_idx == 0)				ret = I2C_RETRY;			else				ret = XFER_NAKED;		}		i2c_pxa_master_complete(i2c, ret);	} else if (isr & ISR_RWM) {		/*		 * Read mode.  We have just sent the address byte, and		 * now we must initiate the transfer.		 */		if (i2c->msg_ptr == i2c->msg->len - 1 &&		    i2c->msg_idx == i2c->msg_num - 1)			icr |= ICR_STOP | ICR_ACKNAK;		icr |= ICR_ALDIE | ICR_TB;	} else if (i2c->msg_ptr < i2c->msg->len) {		/*		 * Write mode.  Write the next data byte.		 */		IDBR = i2c->msg->buf[i2c->msg_ptr++];		icr |= ICR_ALDIE | ICR_TB;		/*		 * If this is the last byte of the last message, send		 * a STOP.		 */		if (i2c->msg_ptr == i2c->msg->len &&		    i2c->msg_idx == i2c->msg_num - 1)			icr |= ICR_STOP;	} else if (i2c->msg_idx < i2c->msg_num - 1) {		/*		 * Next segment of the message.		 */		i2c->msg_ptr = 0;		i2c->msg_idx ++;		i2c->msg++;		/*		 * If we aren't doing a repeated start and address,		 * go back and try to send the next byte.  Note that		 * we do not support switching the R/W direction here.		 */		if (i2c->msg->flags & I2C_M_NOSTART)			goto again;		/*		 * Write the next address.		 */		IDBR = i2c_pxa_addr_byte(i2c->msg);		/*		 * And trigger a repeated start, and send the byte.		 */		icr &= ~ICR_ALDIE;		icr |= ICR_START | ICR_TB;	} else {		if (i2c->msg->len == 0) {			/*			 * Device probes have a message length of zero			 * and need the bus to be reset before it can			 * be used again.			 */			i2c_pxa_reset(i2c);		}		i2c_pxa_master_complete(i2c, 0);	}	i2c->icrlog[i2c->irqlogidx-1] = icr;	ICR = icr;	show_state(i2c);}static void i2c_pxa_irq_rxfull(struct pxa_i2c *i2c, u32 isr){	u32 icr = ICR & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);	/*	 * Read the byte.	 */	i2c->msg->buf[i2c->msg_ptr++] = IDBR;	if (i2c->msg_ptr < i2c->msg->len) {		/*		 * If this is the last byte of the last		 * message, send a STOP.		 */		if (i2c->msg_ptr == i2c->msg->len - 1)			icr |= ICR_STOP | ICR_ACKNAK;		icr |= ICR_ALDIE | ICR_TB;	} else {		i2c_pxa_master_complete(i2c, 0);	}	i2c->icrlog[i2c->irqlogidx-1] = icr;	ICR = icr;}static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id, struct pt_regs *regs){	struct pxa_i2c *i2c = dev_id;	u32 isr = ISR;	if (i2c_debug > 2 && 0) {		dev_dbg(&i2c->adap.dev, "%s: ISR=%08x, ICR=%08x, IBMR=%02x\n",			__func__, isr, ICR, IBMR);		decode_ISR(isr);	}	if (i2c->irqlogidx < sizeof(i2c->isrlog)/sizeof(u32))		i2c->isrlog[i2c->irqlogidx++] = isr;	show_state(i2c);	/*	 * Always clear all pending IRQs.	 */	ISR = isr & (ISR_SSD|ISR_ALD|ISR_ITE|ISR_IRF|ISR_SAD|ISR_BED);	if (isr & ISR_SAD)		i2c_pxa_slave_start(i2c, isr);	if (isr & ISR_SSD)		i2c_pxa_slave_stop(i2c);	if (i2c_pxa_is_slavemode(i2c)) {		if (isr & ISR_ITE)			i2c_pxa_slave_txempty(i2c, isr);		if (isr & ISR_IRF)			i2c_pxa_slave_rxfull(i2c, isr);	} else if (i2c->msg) {		if (isr & ISR_ITE)			i2c_pxa_irq_txempty(i2c, isr);		if (isr & ISR_IRF)			i2c_pxa_irq_rxfull(i2c, isr);	} else {		i2c_pxa_scream_blue_murder(i2c, "spurious irq");	}	return IRQ_HANDLED;}static int i2c_pxa_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num){	struct pxa_i2c *i2c = adap->algo_data;	int ret, i;	for (i = adap->retries; i >= 0; i--) {		ret = i2c_pxa_do_xfer(i2c, msgs, num);		if (ret != I2C_RETRY)			goto out;		if (i2c_debug)			dev_dbg(&adap->dev, "Retrying transmission\n");		udelay(100);	}	i2c_pxa_scream_blue_murder(i2c, "exhausted retries");	ret = -EREMOTEIO; out:	i2c_pxa_set_slave(i2c, ret);	return ret;}static u32 i2c_pxa_functionality(struct i2c_adapter *adap){	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;}static struct i2c_algorithm i2c_pxa_algorithm = {	.master_xfer	= i2c_pxa_xfer,	.functionality	= i2c_pxa_functionality,};static struct pxa_i2c i2c_pxa = {	.lock	= SPIN_LOCK_UNLOCKED,	.wait	= __WAIT_QUEUE_HEAD_INITIALIZER(i2c_pxa.wait),	.adap	= {		.owner		= THIS_MODULE,		.algo		= &i2c_pxa_algorithm,		.name		= "pxa2xx-i2c",		.retries	= 5,	},};static int i2c_pxa_probe(struct platform_device *dev){	struct pxa_i2c *i2c = &i2c_pxa;	struct i2c_pxa_platform_data *plat = dev->dev.platform_data;	int ret;#ifdef CONFIG_PXA27x	pxa_gpio_mode(GPIO117_I2CSCL_MD);	pxa_gpio_mode(GPIO118_I2CSDA_MD);	udelay(100);#endif	i2c->slave_addr = I2C_PXA_SLAVE_ADDR;#ifdef CONFIG_I2C_PXA_SLAVE	i2c->slave = &eeprom_client;	if (plat) {		i2c->slave_addr = plat->slave_addr;		if (plat->slave)			i2c->slave = plat->slave;	}#endif	pxa_set_cken(CKEN14_I2C, 1);	ret = request_irq(IRQ_I2C, i2c_pxa_handler, SA_INTERRUPT,			  "pxa2xx-i2c", i2c);	if (ret)		goto out;	i2c_pxa_reset(i2c);	i2c->adap.algo_data = i2c;	i2c->adap.dev.parent = &dev->dev;	ret = i2c_add_adapter(&i2c->adap);	if (ret < 0) {		printk(KERN_INFO "I2C: Failed to add bus\n");		goto err_irq;	}	platform_set_drvdata(dev, i2c);#ifdef CONFIG_I2C_PXA_SLAVE	printk(KERN_INFO "I2C: %s: PXA I2C adapter, slave address %d\n",	       i2c->adap.dev.bus_id, i2c->slave_addr);#else	printk(KERN_INFO "I2C: %s: PXA I2C adapter\n",	       i2c->adap.dev.bus_id);#endif	return 0; err_irq:	free_irq(IRQ_I2C, i2c); out:	return ret;}static int i2c_pxa_remove(struct platform_device *dev){	struct pxa_i2c *i2c = platform_get_drvdata(dev);	platform_set_drvdata(dev, NULL);	i2c_del_adapter(&i2c->adap);	free_irq(IRQ_I2C, i2c);	pxa_set_cken(CKEN14_I2C, 0);	return 0;}static struct platform_driver i2c_pxa_driver = {	.probe		= i2c_pxa_probe,	.remove		= i2c_pxa_remove,	.driver		= {		.name	= "pxa2xx-i2c",	},};static int __init i2c_adap_pxa_init(void){	return platform_driver_register(&i2c_pxa_driver);}static void i2c_adap_pxa_exit(void){	return platform_driver_unregister(&i2c_pxa_driver);}module_init(i2c_adap_pxa_init);module_exit(i2c_adap_pxa_exit);

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