ixgb_hw.h

linux-2.6.15.6

#define IXGB_RX_DESC_STATUS_IPCS  0x40
#define IXGB_RX_DESC_STATUS_PIF   0x80

#define IXGB_RX_DESC_ERRORS_CE   0x01
#define IXGB_RX_DESC_ERRORS_SE   0x02
#define IXGB_RX_DESC_ERRORS_P    0x08
#define IXGB_RX_DESC_ERRORS_TCPE 0x20
#define IXGB_RX_DESC_ERRORS_IPE  0x40
#define IXGB_RX_DESC_ERRORS_RXE  0x80

#define IXGB_RX_DESC_SPECIAL_VLAN_MASK  0x0FFF	/* VLAN ID is in lower 12 bits */
#define IXGB_RX_DESC_SPECIAL_PRI_MASK   0xE000	/* Priority is in upper 3 bits */
#define IXGB_RX_DESC_SPECIAL_PRI_SHIFT  0x000D	/* Priority is in upper 3 of 16 */

/* Layout of a single transmit descriptor.  The controller assumes that this
 * structure is packed into 16 bytes, which is a safe assumption with most
 * compilers.  However, some compilers may insert padding between the fields,
 * in which case the structure must be packed in some compiler-specific
 * manner. */
struct ixgb_tx_desc {
	uint64_t buff_addr;
	uint32_t cmd_type_len;
	uint8_t status;
	uint8_t popts;
	uint16_t vlan;
};

#define IXGB_TX_DESC_LENGTH_MASK    0x000FFFFF
#define IXGB_TX_DESC_TYPE_MASK      0x00F00000
#define IXGB_TX_DESC_TYPE_SHIFT     20
#define IXGB_TX_DESC_CMD_MASK       0xFF000000
#define IXGB_TX_DESC_CMD_SHIFT      24
#define IXGB_TX_DESC_CMD_EOP        0x01000000
#define IXGB_TX_DESC_CMD_TSE        0x04000000
#define IXGB_TX_DESC_CMD_RS         0x08000000
#define IXGB_TX_DESC_CMD_VLE        0x40000000
#define IXGB_TX_DESC_CMD_IDE        0x80000000

#define IXGB_TX_DESC_TYPE           0x00100000

#define IXGB_TX_DESC_STATUS_DD  0x01

#define IXGB_TX_DESC_POPTS_IXSM 0x01
#define IXGB_TX_DESC_POPTS_TXSM 0x02
#define IXGB_TX_DESC_SPECIAL_PRI_SHIFT  IXGB_RX_DESC_SPECIAL_PRI_SHIFT	/* Priority is in upper 3 of 16 */

struct ixgb_context_desc {
	uint8_t ipcss;
	uint8_t ipcso;
	uint16_t ipcse;
	uint8_t tucss;
	uint8_t tucso;
	uint16_t tucse;
	uint32_t cmd_type_len;
	uint8_t status;
	uint8_t hdr_len;
	uint16_t mss;
};

#define IXGB_CONTEXT_DESC_CMD_TCP 0x01000000
#define IXGB_CONTEXT_DESC_CMD_IP  0x02000000
#define IXGB_CONTEXT_DESC_CMD_TSE 0x04000000
#define IXGB_CONTEXT_DESC_CMD_RS  0x08000000
#define IXGB_CONTEXT_DESC_CMD_IDE 0x80000000

#define IXGB_CONTEXT_DESC_TYPE 0x00000000

#define IXGB_CONTEXT_DESC_STATUS_DD 0x01

/* Filters */
#define IXGB_MC_TBL_SIZE          128	/* Multicast Filter Table (4096 bits) */
#define IXGB_VLAN_FILTER_TBL_SIZE 128	/* VLAN Filter Table (4096 bits) */
#define IXGB_RAR_ENTRIES		  3	/* Number of entries in Rx Address array */

#define IXGB_MEMORY_REGISTER_BASE_ADDRESS   0
#define ENET_HEADER_SIZE			14
#define ENET_FCS_LENGTH			 4
#define IXGB_MAX_NUM_MULTICAST_ADDRESSES	128
#define IXGB_MIN_ENET_FRAME_SIZE_WITHOUT_FCS	60
#define IXGB_MAX_ENET_FRAME_SIZE_WITHOUT_FCS	1514
#define IXGB_MAX_JUMBO_FRAME_SIZE		0x3F00

/* Phy Addresses */
#define IXGB_OPTICAL_PHY_ADDR 0x0	/* Optical Module phy address */
#define IXGB_XAUII_PHY_ADDR   0x1	/* Xauii transceiver phy address */
#define IXGB_DIAG_PHY_ADDR    0x1F	/* Diagnostic Device phy address */

/* This structure takes a 64k flash and maps it for identification commands */
struct ixgb_flash_buffer {
	uint8_t manufacturer_id;
	uint8_t device_id;
	uint8_t filler1[0x2AA8];
	uint8_t cmd2;
	uint8_t filler2[0x2AAA];
	uint8_t cmd1;
	uint8_t filler3[0xAAAA];
};

/*
 * This is a little-endian specific check.
 */
#define IS_MULTICAST(Address) \
    (boolean_t)(((uint8_t *)(Address))[0] & ((uint8_t)0x01))

/*
 * Check whether an address is broadcast.
 */
#define IS_BROADCAST(Address)               \
    ((((uint8_t *)(Address))[0] == ((uint8_t)0xff)) && (((uint8_t *)(Address))[1] == ((uint8_t)0xff)))

/* Flow control parameters */
struct ixgb_fc {
	uint32_t high_water;	/* Flow Control High-water          */
	uint32_t low_water;	/* Flow Control Low-water           */
	uint16_t pause_time;	/* Flow Control Pause timer         */
	boolean_t send_xon;	/* Flow control send XON            */
	ixgb_fc_type type;	/* Type of flow control             */
};

/* The historical defaults for the flow control values are given below. */
#define FC_DEFAULT_HI_THRESH        (0x8000)	/* 32KB */
#define FC_DEFAULT_LO_THRESH        (0x4000)	/* 16KB */
#define FC_DEFAULT_TX_TIMER         (0x100)	/* ~130 us */

/* Phy definitions */
#define IXGB_MAX_PHY_REG_ADDRESS    0xFFFF
#define IXGB_MAX_PHY_ADDRESS        31
#define IXGB_MAX_PHY_DEV_TYPE       31

/* Bus parameters */
struct ixgb_bus {
	ixgb_bus_speed speed;
	ixgb_bus_width width;
	ixgb_bus_type type;
};

struct ixgb_hw {
	uint8_t __iomem *hw_addr;/* Base Address of the hardware     */
	void *back;		/* Pointer to OS-dependent struct   */
	struct ixgb_fc fc;	/* Flow control parameters          */
	struct ixgb_bus bus;	/* Bus parameters                   */
	uint32_t phy_id;	/* Phy Identifier                   */
	uint32_t phy_addr;	/* XGMII address of Phy             */
	ixgb_mac_type mac_type;	/* Identifier for MAC controller    */
	ixgb_phy_type phy_type;	/* Transceiver/phy identifier       */
	uint32_t max_frame_size;	/* Maximum frame size supported     */
	uint32_t mc_filter_type;	/* Multicast filter hash type       */
	uint32_t num_mc_addrs;	/* Number of current Multicast addrs */
	uint8_t curr_mac_addr[IXGB_ETH_LENGTH_OF_ADDRESS];	/* Individual address currently programmed in MAC */
	uint32_t num_tx_desc;	/* Number of Transmit descriptors   */
	uint32_t num_rx_desc;	/* Number of Receive descriptors    */
	uint32_t rx_buffer_size;	/* Size of Receive buffer           */
	boolean_t link_up;	/* TRUE if link is valid            */
	boolean_t adapter_stopped;	/* State of adapter                 */
	uint16_t device_id;	/* device id from PCI configuration space */
	uint16_t vendor_id;	/* vendor id from PCI configuration space */
	uint8_t revision_id;	/* revision id from PCI configuration space */
	uint16_t subsystem_vendor_id;	/* subsystem vendor id from PCI configuration space */
	uint16_t subsystem_id;	/* subsystem id from PCI configuration space */
	uint32_t bar0;		/* Base Address registers           */
	uint32_t bar1;
	uint32_t bar2;
	uint32_t bar3;
	uint16_t pci_cmd_word;	/* PCI command register id from PCI configuration space */
	uint16_t eeprom[IXGB_EEPROM_SIZE];	/* EEPROM contents read at init time  */
	unsigned long io_base;	/* Our I/O mapped location */
	uint32_t lastLFC;
	uint32_t lastRFC;
};

/* Statistics reported by the hardware */
struct ixgb_hw_stats {
	uint64_t tprl;
	uint64_t tprh;
	uint64_t gprcl;
	uint64_t gprch;
	uint64_t bprcl;
	uint64_t bprch;
	uint64_t mprcl;
	uint64_t mprch;
	uint64_t uprcl;
	uint64_t uprch;
	uint64_t vprcl;
	uint64_t vprch;
	uint64_t jprcl;
	uint64_t jprch;
	uint64_t gorcl;
	uint64_t gorch;
	uint64_t torl;
	uint64_t torh;
	uint64_t rnbc;
	uint64_t ruc;
	uint64_t roc;
	uint64_t rlec;
	uint64_t crcerrs;
	uint64_t icbc;
	uint64_t ecbc;
	uint64_t mpc;
	uint64_t tptl;
	uint64_t tpth;
	uint64_t gptcl;
	uint64_t gptch;
	uint64_t bptcl;
	uint64_t bptch;
	uint64_t mptcl;
	uint64_t mptch;
	uint64_t uptcl;
	uint64_t uptch;
	uint64_t vptcl;
	uint64_t vptch;
	uint64_t jptcl;
	uint64_t jptch;
	uint64_t gotcl;
	uint64_t gotch;
	uint64_t totl;
	uint64_t toth;
	uint64_t dc;
	uint64_t plt64c;
	uint64_t tsctc;
	uint64_t tsctfc;
	uint64_t ibic;
	uint64_t rfc;
	uint64_t lfc;
	uint64_t pfrc;
	uint64_t pftc;
	uint64_t mcfrc;
	uint64_t mcftc;
	uint64_t xonrxc;
	uint64_t xontxc;
	uint64_t xoffrxc;
	uint64_t xofftxc;
	uint64_t rjc;
};

/* Function Prototypes */
extern boolean_t ixgb_adapter_stop(struct ixgb_hw *hw);
extern boolean_t ixgb_init_hw(struct ixgb_hw *hw);
extern boolean_t ixgb_adapter_start(struct ixgb_hw *hw);
extern void ixgb_check_for_link(struct ixgb_hw *hw);
extern boolean_t ixgb_check_for_bad_link(struct ixgb_hw *hw);

extern void ixgb_rar_set(struct ixgb_hw *hw,
				uint8_t *addr,
				uint32_t index);


/* Filters (multicast, vlan, receive) */
extern void ixgb_mc_addr_list_update(struct ixgb_hw *hw,
				   uint8_t *mc_addr_list,
				   uint32_t mc_addr_count,
				   uint32_t pad);

/* Vfta functions */
extern void ixgb_write_vfta(struct ixgb_hw *hw,
				 uint32_t offset,
				 uint32_t value);

/* Access functions to eeprom data */
void ixgb_get_ee_mac_addr(struct ixgb_hw *hw, uint8_t *mac_addr);
uint32_t ixgb_get_ee_pba_number(struct ixgb_hw *hw);
uint16_t ixgb_get_ee_device_id(struct ixgb_hw *hw);
boolean_t ixgb_get_eeprom_data(struct ixgb_hw *hw);
uint16_t ixgb_get_eeprom_word(struct ixgb_hw *hw, uint16_t index);

/* Everything else */
void ixgb_led_on(struct ixgb_hw *hw);
void ixgb_led_off(struct ixgb_hw *hw);
void ixgb_write_pci_cfg(struct ixgb_hw *hw,
			 uint32_t reg,
			 uint16_t * value);


#endif /* _IXGB_HW_H_ */