ixgb_hw.h

linux-2.6.15.6

#define IXGB_CTRL1_SDP7_DIR    0x00000800
#define IXGB_CTRL1_EE_RST      0x00002000
#define IXGB_CTRL1_RO_DIS      0x00020000
#define IXGB_CTRL1_PCIXHM_MASK 0x00C00000
#define IXGB_CTRL1_PCIXHM_1_2  0x00000000
#define IXGB_CTRL1_PCIXHM_5_8  0x00400000
#define IXGB_CTRL1_PCIXHM_3_4  0x00800000
#define IXGB_CTRL1_PCIXHM_7_8  0x00C00000

/* STATUS Bit Masks */
#define IXGB_STATUS_LU            0x00000002
#define IXGB_STATUS_AIP           0x00000004
#define IXGB_STATUS_TXOFF         0x00000010
#define IXGB_STATUS_XAUIME        0x00000020
#define IXGB_STATUS_RES           0x00000040
#define IXGB_STATUS_RIS           0x00000080
#define IXGB_STATUS_RIE           0x00000100
#define IXGB_STATUS_RLF           0x00000200
#define IXGB_STATUS_RRF           0x00000400
#define IXGB_STATUS_PCI_SPD       0x00000800
#define IXGB_STATUS_BUS64         0x00001000
#define IXGB_STATUS_PCIX_MODE     0x00002000
#define IXGB_STATUS_PCIX_SPD_MASK 0x0000C000
#define IXGB_STATUS_PCIX_SPD_66   0x00000000
#define IXGB_STATUS_PCIX_SPD_100  0x00004000
#define IXGB_STATUS_PCIX_SPD_133  0x00008000
#define IXGB_STATUS_REV_ID_MASK   0x000F0000
#define IXGB_STATUS_REV_ID_SHIFT  16

/* EECD Bit Masks */
#define IXGB_EECD_SK       0x00000001
#define IXGB_EECD_CS       0x00000002
#define IXGB_EECD_DI       0x00000004
#define IXGB_EECD_DO       0x00000008
#define IXGB_EECD_FWE_MASK 0x00000030
#define IXGB_EECD_FWE_DIS  0x00000010
#define IXGB_EECD_FWE_EN   0x00000020

/* MFS */
#define IXGB_MFS_SHIFT 16

/* Interrupt Register Bit Masks (used for ICR, ICS, IMS, and IMC) */
#define IXGB_INT_TXDW     0x00000001
#define IXGB_INT_TXQE     0x00000002
#define IXGB_INT_LSC      0x00000004
#define IXGB_INT_RXSEQ    0x00000008
#define IXGB_INT_RXDMT0   0x00000010
#define IXGB_INT_RXO      0x00000040
#define IXGB_INT_RXT0     0x00000080
#define IXGB_INT_AUTOSCAN 0x00000200
#define IXGB_INT_GPI0     0x00000800
#define IXGB_INT_GPI1     0x00001000
#define IXGB_INT_GPI2     0x00002000
#define IXGB_INT_GPI3     0x00004000

/* RCTL Bit Masks */
#define IXGB_RCTL_RXEN        0x00000002
#define IXGB_RCTL_SBP         0x00000004
#define IXGB_RCTL_UPE         0x00000008
#define IXGB_RCTL_MPE         0x00000010
#define IXGB_RCTL_RDMTS_MASK  0x00000300
#define IXGB_RCTL_RDMTS_1_2   0x00000000
#define IXGB_RCTL_RDMTS_1_4   0x00000100
#define IXGB_RCTL_RDMTS_1_8   0x00000200
#define IXGB_RCTL_MO_MASK     0x00003000
#define IXGB_RCTL_MO_47_36    0x00000000
#define IXGB_RCTL_MO_46_35    0x00001000
#define IXGB_RCTL_MO_45_34    0x00002000
#define IXGB_RCTL_MO_43_32    0x00003000
#define IXGB_RCTL_MO_SHIFT    12
#define IXGB_RCTL_BAM         0x00008000
#define IXGB_RCTL_BSIZE_MASK  0x00030000
#define IXGB_RCTL_BSIZE_2048  0x00000000
#define IXGB_RCTL_BSIZE_4096  0x00010000
#define IXGB_RCTL_BSIZE_8192  0x00020000
#define IXGB_RCTL_BSIZE_16384 0x00030000
#define IXGB_RCTL_VFE         0x00040000
#define IXGB_RCTL_CFIEN       0x00080000
#define IXGB_RCTL_CFI         0x00100000
#define IXGB_RCTL_RPDA_MASK   0x00600000
#define IXGB_RCTL_RPDA_MC_MAC 0x00000000
#define IXGB_RCTL_MC_ONLY     0x00400000
#define IXGB_RCTL_CFF         0x00800000
#define IXGB_RCTL_SECRC       0x04000000
#define IXGB_RDT_FPDB         0x80000000

#define IXGB_RCTL_IDLE_RX_UNIT 0

/* FCRTL Bit Masks */
#define IXGB_FCRTL_XONE       0x80000000

/* RXDCTL Bit Masks */
#define IXGB_RXDCTL_PTHRESH_MASK  0x000001FF
#define IXGB_RXDCTL_PTHRESH_SHIFT 0
#define IXGB_RXDCTL_HTHRESH_MASK  0x0003FE00
#define IXGB_RXDCTL_HTHRESH_SHIFT 9
#define IXGB_RXDCTL_WTHRESH_MASK  0x07FC0000
#define IXGB_RXDCTL_WTHRESH_SHIFT 18

/* RAIDC Bit Masks */
#define IXGB_RAIDC_HIGHTHRS_MASK 0x0000003F
#define IXGB_RAIDC_DELAY_MASK    0x000FF800
#define IXGB_RAIDC_DELAY_SHIFT   11
#define IXGB_RAIDC_POLL_MASK     0x1FF00000
#define IXGB_RAIDC_POLL_SHIFT    20
#define IXGB_RAIDC_RXT_GATE      0x40000000
#define IXGB_RAIDC_EN            0x80000000

#define IXGB_RAIDC_POLL_1000_INTERRUPTS_PER_SECOND      1220
#define IXGB_RAIDC_POLL_5000_INTERRUPTS_PER_SECOND      244
#define IXGB_RAIDC_POLL_10000_INTERRUPTS_PER_SECOND     122
#define IXGB_RAIDC_POLL_20000_INTERRUPTS_PER_SECOND     61

/* RXCSUM Bit Masks */
#define IXGB_RXCSUM_IPOFL 0x00000100
#define IXGB_RXCSUM_TUOFL 0x00000200

/* RAH Bit Masks */
#define IXGB_RAH_ASEL_MASK 0x00030000
#define IXGB_RAH_ASEL_DEST 0x00000000
#define IXGB_RAH_ASEL_SRC  0x00010000
#define IXGB_RAH_AV        0x80000000

/* TCTL Bit Masks */
#define IXGB_TCTL_TCE  0x00000001
#define IXGB_TCTL_TXEN 0x00000002
#define IXGB_TCTL_TPDE 0x00000004

#define IXGB_TCTL_IDLE_TX_UNIT  0

/* TXDCTL Bit Masks */
#define IXGB_TXDCTL_PTHRESH_MASK  0x0000007F
#define IXGB_TXDCTL_HTHRESH_MASK  0x00007F00
#define IXGB_TXDCTL_HTHRESH_SHIFT 8
#define IXGB_TXDCTL_WTHRESH_MASK  0x007F0000
#define IXGB_TXDCTL_WTHRESH_SHIFT 16

/* TSPMT Bit Masks */
#define IXGB_TSPMT_TSMT_MASK   0x0000FFFF
#define IXGB_TSPMT_TSPBP_MASK  0xFFFF0000
#define IXGB_TSPMT_TSPBP_SHIFT 16

/* PAP Bit Masks */
#define IXGB_PAP_TXPC_MASK 0x0000FFFF
#define IXGB_PAP_TXPV_MASK 0x000F0000
#define IXGB_PAP_TXPV_10G  0x00000000
#define IXGB_PAP_TXPV_1G   0x00010000
#define IXGB_PAP_TXPV_2G   0x00020000
#define IXGB_PAP_TXPV_3G   0x00030000
#define IXGB_PAP_TXPV_4G   0x00040000
#define IXGB_PAP_TXPV_5G   0x00050000
#define IXGB_PAP_TXPV_6G   0x00060000
#define IXGB_PAP_TXPV_7G   0x00070000
#define IXGB_PAP_TXPV_8G   0x00080000
#define IXGB_PAP_TXPV_9G   0x00090000
#define IXGB_PAP_TXPV_WAN  0x000F0000

/* PCSC1 Bit Masks */
#define IXGB_PCSC1_LOOPBACK 0x00004000

/* PCSC2 Bit Masks */
#define IXGB_PCSC2_PCS_TYPE_MASK  0x00000003
#define IXGB_PCSC2_PCS_TYPE_10GBX 0x00000001

/* PCSS1 Bit Masks */
#define IXGB_PCSS1_LOCAL_FAULT    0x00000080
#define IXGB_PCSS1_RX_LINK_STATUS 0x00000004

/* PCSS2 Bit Masks */
#define IXGB_PCSS2_DEV_PRES_MASK 0x0000C000
#define IXGB_PCSS2_DEV_PRES      0x00004000
#define IXGB_PCSS2_TX_LF         0x00000800
#define IXGB_PCSS2_RX_LF         0x00000400
#define IXGB_PCSS2_10GBW         0x00000004
#define IXGB_PCSS2_10GBX         0x00000002
#define IXGB_PCSS2_10GBR         0x00000001

/* XPCSS Bit Masks */
#define IXGB_XPCSS_ALIGN_STATUS 0x00001000
#define IXGB_XPCSS_PATTERN_TEST 0x00000800
#define IXGB_XPCSS_LANE_3_SYNC  0x00000008
#define IXGB_XPCSS_LANE_2_SYNC  0x00000004
#define IXGB_XPCSS_LANE_1_SYNC  0x00000002
#define IXGB_XPCSS_LANE_0_SYNC  0x00000001

/* XPCSTC Bit Masks */
#define IXGB_XPCSTC_BERT_TRIG       0x00200000
#define IXGB_XPCSTC_BERT_SST        0x00100000
#define IXGB_XPCSTC_BERT_PSZ_MASK   0x000C0000
#define IXGB_XPCSTC_BERT_PSZ_SHIFT  17
#define IXGB_XPCSTC_BERT_PSZ_INF    0x00000003
#define IXGB_XPCSTC_BERT_PSZ_68     0x00000001
#define IXGB_XPCSTC_BERT_PSZ_1028   0x00000000

/* MSCA bit Masks */
/* New Protocol Address */
#define IXGB_MSCA_NP_ADDR_MASK      0x0000FFFF
#define IXGB_MSCA_NP_ADDR_SHIFT     0
/* Either Device Type or Register Address,depending on ST_CODE */
#define IXGB_MSCA_DEV_TYPE_MASK     0x001F0000
#define IXGB_MSCA_DEV_TYPE_SHIFT    16
#define IXGB_MSCA_PHY_ADDR_MASK     0x03E00000
#define IXGB_MSCA_PHY_ADDR_SHIFT    21
#define IXGB_MSCA_OP_CODE_MASK      0x0C000000
/* OP_CODE == 00, Address cycle, New Protocol           */
/* OP_CODE == 01, Write operation                       */
/* OP_CODE == 10, Read operation                        */
/* OP_CODE == 11, Read, auto increment, New Protocol    */
#define IXGB_MSCA_ADDR_CYCLE        0x00000000
#define IXGB_MSCA_WRITE             0x04000000
#define IXGB_MSCA_READ              0x08000000
#define IXGB_MSCA_READ_AUTOINC      0x0C000000
#define IXGB_MSCA_OP_CODE_SHIFT     26
#define IXGB_MSCA_ST_CODE_MASK      0x30000000
/* ST_CODE == 00, New Protocol  */
/* ST_CODE == 01, Old Protocol  */
#define IXGB_MSCA_NEW_PROTOCOL      0x00000000
#define IXGB_MSCA_OLD_PROTOCOL      0x10000000
#define IXGB_MSCA_ST_CODE_SHIFT     28
/* Initiate command, self-clearing when command completes */
#define IXGB_MSCA_MDI_COMMAND       0x40000000
/*MDI In Progress Enable. */
#define IXGB_MSCA_MDI_IN_PROG_EN    0x80000000

/* MSRWD bit masks */
#define IXGB_MSRWD_WRITE_DATA_MASK  0x0000FFFF
#define IXGB_MSRWD_WRITE_DATA_SHIFT 0
#define IXGB_MSRWD_READ_DATA_MASK   0xFFFF0000
#define IXGB_MSRWD_READ_DATA_SHIFT  16

/* Definitions for the optics devices on the MDIO bus. */
#define IXGB_PHY_ADDRESS             0x0	/* Single PHY, multiple "Devices" */

/* Standard five-bit Device IDs.  See IEEE 802.3ae, clause 45 */
#define MDIO_PMA_PMD_DID        0x01
#define MDIO_WIS_DID            0x02
#define MDIO_PCS_DID            0x03
#define MDIO_XGXS_DID           0x04

/* Standard PMA/PMD registers and bit definitions. */
/* Note: This is a very limited set of definitions,      */
/* only implemented features are defined.                */
#define MDIO_PMA_PMD_CR1        0x0000
#define MDIO_PMA_PMD_CR1_RESET  0x8000

#define MDIO_PMA_PMD_XPAK_VENDOR_NAME       0x803A	/* XPAK/XENPAK devices only */

/* Vendor-specific MDIO registers */
#define G6XXX_PMA_PMD_VS1                   0xC001	/* Vendor-specific register */
#define G6XXX_XGXS_XAUI_VS2                 0x18	/* Vendor-specific register */

#define G6XXX_PMA_PMD_VS1_PLL_RESET         0x80
#define G6XXX_PMA_PMD_VS1_REMOVE_PLL_RESET  0x00
#define G6XXX_XGXS_XAUI_VS2_INPUT_MASK      0x0F	/* XAUI lanes synchronized */

/* Layout of a single receive descriptor.  The controller assumes that this
 * structure is packed into 16 bytes, which is a safe assumption with most
 * compilers.  However, some compilers may insert padding between the fields,
 * in which case the structure must be packed in some compiler-specific
 * manner. */
struct ixgb_rx_desc {
	uint64_t buff_addr;
	uint16_t length;
	uint16_t reserved;
	uint8_t status;
	uint8_t errors;
	uint16_t special;
};

#define IXGB_RX_DESC_STATUS_DD    0x01
#define IXGB_RX_DESC_STATUS_EOP   0x02
#define IXGB_RX_DESC_STATUS_IXSM  0x04
#define IXGB_RX_DESC_STATUS_VP    0x08
#define IXGB_RX_DESC_STATUS_TCPCS 0x20