de4x5.h

linux-2.6.15.6

#define MII_ANLPA_100M 0x0380      /* 100Mb Technology Ability Mask */
#define MII_ANLPA_10M  0x0060      /* 10Mb Technology Ability Mask */
#define MII_ANLPA_CSMA 0x0001      /* CSMA-CD Capable */

/*
** SROM Media Definitions (ABG SROM Section)
*/
#define MEDIA_NWAY     0x0080      /* Nway (Auto Negotiation) on PHY */
#define MEDIA_MII      0x0040      /* MII Present on the adapter */
#define MEDIA_FIBRE    0x0008      /* Fibre Media present */
#define MEDIA_AUI      0x0004      /* AUI Media present */
#define MEDIA_TP       0x0002      /* TP Media present */
#define MEDIA_BNC      0x0001      /* BNC Media present */

/*
** SROM Definitions (Digital Semiconductor Format)
*/
#define SROM_SSVID     0x0000      /* Sub-system Vendor ID offset */
#define SROM_SSID      0x0002      /* Sub-system ID offset */
#define SROM_CISPL     0x0004      /* CardBus CIS Pointer low offset */
#define SROM_CISPH     0x0006      /* CardBus CIS Pointer high offset */
#define SROM_IDCRC     0x0010      /* ID Block CRC offset*/
#define SROM_RSVD2     0x0011      /* ID Reserved 2 offset */
#define SROM_SFV       0x0012      /* SROM Format Version offset */
#define SROM_CCNT      0x0013      /* Controller Count offset */
#define SROM_HWADD     0x0014      /* Hardware Address offset */
#define SROM_MRSVD     0x007c      /* Manufacturer Reserved offset*/
#define SROM_CRC       0x007e      /* SROM CRC offset */

/*
** SROM Media Connection Definitions
*/
#define SROM_10BT      0x0000      /*  10BASE-T half duplex */
#define SROM_10BTN     0x0100      /*  10BASE-T with Nway */
#define SROM_10BTF     0x0204      /*  10BASE-T full duplex */
#define SROM_10BTNLP   0x0400      /*  10BASE-T without Link Pass test */
#define SROM_10B2      0x0001      /*  10BASE-2 (BNC) */
#define SROM_10B5      0x0002      /*  10BASE-5 (AUI) */
#define SROM_100BTH    0x0003      /*  100BASE-T half duplex */
#define SROM_100BTF    0x0205      /*  100BASE-T full duplex */
#define SROM_100BT4    0x0006      /*  100BASE-T4 */
#define SROM_100BFX    0x0007      /*  100BASE-FX half duplex (Fiber) */
#define SROM_M10BT     0x0009      /*  MII 10BASE-T half duplex */
#define SROM_M10BTF    0x020a      /*  MII 10BASE-T full duplex */
#define SROM_M100BT    0x000d      /*  MII 100BASE-T half duplex */
#define SROM_M100BTF   0x020e      /*  MII 100BASE-T full duplex */
#define SROM_M100BT4   0x000f      /*  MII 100BASE-T4 */
#define SROM_M100BF    0x0010      /*  MII 100BASE-FX half duplex */
#define SROM_M100BFF   0x0211      /*  MII 100BASE-FX full duplex */
#define SROM_PDA       0x0800      /*  Powerup & Dynamic Autosense */
#define SROM_PAO       0x8800      /*  Powerup Autosense Only */
#define SROM_NSMI      0xffff      /*  No Selected Media Information */

/*
** SROM Media Definitions
*/
#define SROM_10BASET   0x0000      /*  10BASE-T half duplex */
#define SROM_10BASE2   0x0001      /*  10BASE-2 (BNC) */
#define SROM_10BASE5   0x0002      /*  10BASE-5 (AUI) */
#define SROM_100BASET  0x0003      /*  100BASE-T half duplex */
#define SROM_10BASETF  0x0004      /*  10BASE-T full duplex */
#define SROM_100BASETF 0x0005      /*  100BASE-T full duplex */
#define SROM_100BASET4 0x0006      /*  100BASE-T4 */
#define SROM_100BASEF  0x0007      /*  100BASE-FX half duplex */
#define SROM_100BASEFF 0x0008      /*  100BASE-FX full duplex */

#define BLOCK_LEN      0x7f        /* Extended blocks length mask */
#define EXT_FIELD      0x40        /* Extended blocks extension field bit */
#define MEDIA_CODE     0x3f        /* Extended blocks media code mask */

/*
** SROM Compact Format Block Masks
*/
#define COMPACT_FI      0x80       /* Format Indicator */
#define COMPACT_LEN     0x04       /* Length */
#define COMPACT_MC      0x3f       /* Media Code */

/*
** SROM Extended Format Block Type 0 Masks
*/
#define BLOCK0_FI      0x80        /* Format Indicator */
#define BLOCK0_MCS     0x80        /* Media Code byte Sign */
#define BLOCK0_MC      0x3f        /* Media Code */

/*
** DC21040 Full Duplex Register (DE4X5_FDR)
*/
#define FDR_FDACV  0x0000ffff      /* Full Duplex Auto Configuration Value */

/*
** DC21041 General Purpose Timer Register (DE4X5_GPT)
*/
#define GPT_CON  0x00010000        /* One shot: 0,  Continuous: 1 */
#define GPT_VAL  0x0000ffff        /* Timer Value */

/*
** DC21140 General Purpose Register (DE4X5_GEP) (hardware dependent bits)
*/
/* Valid ONLY for DE500 hardware */
#define GEP_LNP  0x00000080        /* Link Pass               (input)        */
#define GEP_SLNK 0x00000040        /* SYM LINK                (input)        */
#define GEP_SDET 0x00000020        /* Signal Detect           (input)        */
#define GEP_HRST 0x00000010        /* Hard RESET (to PHY)     (output)       */
#define GEP_FDXD 0x00000008        /* Full Duplex Disable     (output)       */
#define GEP_PHYL 0x00000004        /* PHY Loopback            (output)       */
#define GEP_FLED 0x00000002        /* Force Activity LED on   (output)       */
#define GEP_MODE 0x00000001        /* 0: 10Mb/s,  1: 100Mb/s                 */
#define GEP_INIT 0x0000011f        /* Setup inputs (0) and outputs (1)       */
#define GEP_CTRL 0x00000100        /* GEP control bit                        */

/*
** SIA Register Defaults
*/
#define CSR13 0x00000001
#define CSR14 0x0003ff7f           /* Autonegotiation disabled               */
#define CSR15 0x00000008

/*
** SIA Status Register (DE4X5_SISR)
*/
#define SISR_LPC   0xffff0000      /* Link Partner's Code Word               */
#define SISR_LPN   0x00008000      /* Link Partner Negotiable                */
#define SISR_ANS   0x00007000      /* Auto Negotiation Arbitration State     */
#define SISR_NSN   0x00000800      /* Non Stable NLPs Detected (DC21041)     */
#define SISR_TRF   0x00000800      /* Transmit Remote Fault                  */
#define SISR_NSND  0x00000400      /* Non Stable NLPs Detected (DC21142)     */
#define SISR_ANR_FDS 0x00000400    /* Auto Negotiate Restart/Full Duplex Sel.*/
#define SISR_TRA   0x00000200      /* 10BASE-T Receive Port Activity         */
#define SISR_NRA   0x00000200      /* Non Selected Port Receive Activity     */
#define SISR_ARA   0x00000100      /* AUI Receive Port Activity              */
#define SISR_SRA   0x00000100      /* Selected Port Receive Activity         */
#define SISR_DAO   0x00000080      /* PLL All One                            */
#define SISR_DAZ   0x00000040      /* PLL All Zero                           */
#define SISR_DSP   0x00000020      /* PLL Self-Test Pass                     */
#define SISR_DSD   0x00000010      /* PLL Self-Test Done                     */
#define SISR_APS   0x00000008      /* Auto Polarity State                    */
#define SISR_LKF   0x00000004      /* Link Fail Status                       */
#define SISR_LS10  0x00000004      /* 10Mb/s Link Fail Status                */
#define SISR_NCR   0x00000002      /* Network Connection Error               */
#define SISR_LS100 0x00000002      /* 100Mb/s Link Fail Status               */
#define SISR_PAUI  0x00000001      /* AUI_TP Indication                      */
#define SISR_MRA   0x00000001      /* MII Receive Port Activity              */

#define ANS_NDIS   0x00000000      /* Nway disable                           */
#define ANS_TDIS   0x00001000      /* Transmit Disable                       */
#define ANS_ADET   0x00002000      /* Ability Detect                         */
#define ANS_ACK    0x00003000      /* Acknowledge                            */
#define ANS_CACK   0x00004000      /* Complete Acknowledge                   */
#define ANS_NWOK   0x00005000      /* Nway OK - FLP Link Good                */
#define ANS_LCHK   0x00006000      /* Link Check                             */

#define SISR_RST   0x00000301      /* CSR12 reset                            */
#define SISR_ANR   0x00001301      /* Autonegotiation restart                */

/*
** SIA Connectivity Register (DE4X5_SICR)
*/
#define SICR_SDM   0xffff0000       /* SIA Diagnostics Mode */
#define SICR_OE57  0x00008000       /* Output Enable 5 6 7 */
#define SICR_OE24  0x00004000       /* Output Enable 2 4 */
#define SICR_OE13  0x00002000       /* Output Enable 1 3 */
#define SICR_IE    0x00001000       /* Input Enable */
#define SICR_EXT   0x00000000       /* SIA MUX Select External SIA Mode */
#define SICR_D_SIA 0x00000400       /* SIA MUX Select Diagnostics - SIA Sigs */
#define SICR_DPLL  0x00000800       /* SIA MUX Select Diagnostics - DPLL Sigs*/
#define SICR_APLL  0x00000a00       /* SIA MUX Select Diagnostics - DPLL Sigs*/
#define SICR_D_RxM 0x00000c00       /* SIA MUX Select Diagnostics - RxM Sigs */
#define SICR_M_RxM 0x00000d00       /* SIA MUX Select Diagnostics - RxM Sigs */
#define SICR_LNKT  0x00000e00       /* SIA MUX Select Diagnostics - Link Test*/
#define SICR_SEL   0x00000f00       /* SIA MUX Select AUI or TP with LEDs */
#define SICR_ASE   0x00000080       /* APLL Start Enable*/
#define SICR_SIM   0x00000040       /* Serial Interface Input Multiplexer */
#define SICR_ENI   0x00000020       /* Encoder Input Multiplexer */
#define SICR_EDP   0x00000010       /* SIA PLL External Input Enable */
#define SICR_AUI   0x00000008       /* 10Base-T (0) or AUI (1) */
#define SICR_CAC   0x00000004       /* CSR Auto Configuration */
#define SICR_PS    0x00000002       /* Pin AUI/TP Selection */
#define SICR_SRL   0x00000001       /* SIA Reset */
#define SIA_RESET  0x00000000       /* SIA Reset Value */

/*
** SIA Transmit and Receive Register (DE4X5_STRR)
*/
#define STRR_TAS   0x00008000       /* 10Base-T/AUI Autosensing Enable */
#define STRR_SPP   0x00004000       /* Set Polarity Plus */
#define STRR_APE   0x00002000       /* Auto Polarity Enable */
#define STRR_LTE   0x00001000       /* Link Test Enable */
#define STRR_SQE   0x00000800       /* Signal Quality Enable */
#define STRR_CLD   0x00000400       /* Collision Detect Enable */
#define STRR_CSQ   0x00000200       /* Collision Squelch Enable */
#define STRR_RSQ   0x00000100       /* Receive Squelch Enable */
#define STRR_ANE   0x00000080       /* Auto Negotiate Enable */
#define STRR_HDE   0x00000040       /* Half Duplex Enable */
#define STRR_CPEN  0x00000030       /* Compensation Enable */
#define STRR_LSE   0x00000008       /* Link Pulse Send Enable */
#define STRR_DREN  0x00000004       /* Driver Enable */
#define STRR_LBK   0x00000002       /* Loopback Enable */
#define STRR_ECEN  0x00000001       /* Encoder Enable */
#define STRR_RESET 0xffffffff       /* Reset value for STRR */

/*
** SIA General Register (DE4X5_SIGR)
*/
#define SIGR_RMI   0x40000000       /* Receive Match Interrupt */
#define SIGR_GI1   0x20000000       /* General Port Interrupt 1 */
#define SIGR_GI0   0x10000000       /* General Port Interrupt 0 */
#define SIGR_CWE   0x08000000       /* Control Write Enable */
#define SIGR_RME   0x04000000       /* Receive Match Enable */
#define SIGR_GEI1  0x02000000       /* GEP Interrupt Enable on Port 1 */
#define SIGR_GEI0  0x01000000       /* GEP Interrupt Enable on Port 0 */
#define SIGR_LGS3  0x00800000       /* LED/GEP3 Select */
#define SIGR_LGS2  0x00400000       /* LED/GEP2 Select */
#define SIGR_LGS1  0x00200000       /* LED/GEP1 Select */
#define SIGR_LGS0  0x00100000       /* LED/GEP0 Select */
#define SIGR_MD    0x000f0000       /* General Purpose Mode and Data */
#define SIGR_LV2   0x00008000       /* General Purpose LED2 value */
#define SIGR_LE2   0x00004000       /* General Purpose LED2 enable */
#define SIGR_FRL   0x00002000       /* Force Receiver Low */
#define SIGR_DPST  0x00001000       /* PLL Self Test Start */
#define SIGR_LSD   0x00000800       /* LED Stretch Disable */
#define SIGR_FLF   0x00000400       /* Force Link Fail */
#define SIGR_FUSQ  0x00000200       /* Force Unsquelch */
#define SIGR_TSCK  0x00000100       /* Test Clock */
#define SIGR_LV1   0x00000080       /* General Purpose LED1 value */
#define SIGR_LE1   0x00000040       /* General Purpose LED1 enable */
#define SIGR_RWR   0x00000020       /* Receive Watchdog Release */
#define SIGR_RWD   0x00000010       /* Receive Watchdog Disable */
#define SIGR_ABM   0x00000008       /* BNC: 0,  AUI:1 */
#define SIGR_JCK   0x00000004       /* Jabber Clock */
#define SIGR_HUJ   0x00000002       /* Host Unjab */
#define SIGR_JBD   0x00000001       /* Jabber Disable */
#define SIGR_RESET 0xffff0000       /* Reset value for SIGR */

/*
** Receive Descriptor Bit Summary
*/
#define R_OWN      0x80000000       /* Own Bit */
#define RD_FF      0x40000000       /* Filtering Fail */
#define RD_FL      0x3fff0000       /* Frame Length */
#define RD_ES      0x00008000       /* Error Summary */
#define RD_LE      0x00004000       /* Length Error */
#define RD_DT      0x00003000       /* Data Type */
#define RD_RF      0x00000800       /* Runt Frame */
#define RD_MF      0x00000400       /* Multicast Frame */
#define RD_FS      0x00000200       /* First Descriptor */
#define RD_LS      0x00000100       /* Last Descriptor */
#define RD_TL      0x00000080       /* Frame Too Long */
#define RD_CS      0x00000040       /* Collision Seen */
#define RD_FT      0x00000020       /* Frame Type */
#define RD_RJ      0x00000010       /* Receive Watchdog */
#define RD_RE      0x00000008       /* Report on MII Error */
#define RD_DB      0x00000004       /* Dribbling Bit */
#define RD_CE      0x00000002       /* CRC Error */
#define RD_OF      0x00000001       /* Overflow */

#define RD_RER     0x02000000       /* Receive End Of Ring */
#define RD_RCH     0x01000000       /* Second Address Chained */
#define RD_RBS2    0x003ff800       /* Buffer 2 Size */