skgehw.h

linux-2.6.15.6

#define CSR_DREAD_RUN	BIT_13		/* Release Descr Read SM */
#define CSR_DREAD_RST	BIT_12		/* Reset   Descr Read SM */
#define CSR_DWRITE_RUN	BIT_11		/* Release Descr Write SM */
#define CSR_DWRITE_RST	BIT_10		/* Reset   Descr Write SM */
#define CSR_TRANS_RUN	BIT_9		/* Release Transfer SM */
#define CSR_TRANS_RST	BIT_8		/* Reset   Transfer SM */
#define CSR_ENA_POL		BIT_7		/* Enable  Descr Polling */
#define CSR_DIS_POL		BIT_6		/* Disable Descr Polling */
#define CSR_STOP		BIT_5		/* Stop  Rx/Tx Queue */
#define CSR_START		BIT_4		/* Start Rx/Tx Queue */
#define CSR_IRQ_CL_P	BIT_3		/* (Rx)	Clear Parity IRQ */
#define CSR_IRQ_CL_B	BIT_2		/* Clear EOB IRQ */
#define CSR_IRQ_CL_F	BIT_1		/* Clear EOF IRQ */
#define CSR_IRQ_CL_C	BIT_0		/* Clear ERR IRQ */

#define CSR_SET_RESET	(CSR_DESC_SET | CSR_FIFO_SET | CSR_HPI_RST |\
						CSR_SV_RST | CSR_DREAD_RST | CSR_DWRITE_RST |\
						CSR_TRANS_RST)
#define CSR_CLR_RESET	(CSR_DESC_CLR | CSR_FIFO_CLR | CSR_HPI_RUN |\
						CSR_SV_RUN | CSR_DREAD_RUN | CSR_DWRITE_RUN |\
						CSR_TRANS_RUN)

/*	Q_F				32 bit	Flag Register */
									/* Bit 31..28:	reserved */
#define F_ALM_FULL		BIT_27		/* Rx FIFO: almost full */
#define F_EMPTY			BIT_27		/* Tx FIFO: empty flag */
#define F_FIFO_EOF		BIT_26		/* Tag (EOF Flag) bit in FIFO */
#define F_WM_REACHED	BIT_25		/* Watermark reached */
									/* reserved */
#define F_FIFO_LEVEL	(0x1fL<<16)	/* Bit 23..16:	# of Qwords in FIFO */
									/* Bit 15..11: 	reserved */
#define F_WATER_MARK	0x0007ffL	/* Bit 10.. 0:	Watermark */

/*	Q_T1			32 bit	Test Register 1 */
/*		Holds four State Machine control Bytes */
#define SM_CTRL_SV_MSK	(0xffL<<24)	/* Bit 31..24:	Control Supervisor SM */
#define SM_CTRL_RD_MSK	(0xffL<<16)	/* Bit 23..16:	Control Read Desc SM */
#define SM_CTRL_WR_MSK	(0xffL<<8)	/* Bit 15.. 8:	Control Write Desc SM */
#define SM_CTRL_TR_MSK	0xffL		/* Bit	7.. 0:	Control Transfer SM */

/*	Q_T1_TR			 8 bit	Test Register 1 Transfer SM */
/*	Q_T1_WR			 8 bit	Test Register 1 Write Descriptor SM */
/*	Q_T1_RD			 8 bit	Test Register 1 Read Descriptor SM */
/*	Q_T1_SV			 8 bit	Test Register 1 Supervisor SM */

/* The control status byte of each machine looks like ... */
#define SM_STATE		0xf0	/* Bit 7.. 4:	State which shall be loaded */
#define SM_LOAD			BIT_3S	/* Load the SM with SM_STATE */
#define SM_TEST_ON		BIT_2S	/* Switch on SM Test Mode */
#define SM_TEST_OFF		BIT_1S	/* Go off the Test Mode */
#define SM_STEP			BIT_0S	/* Step the State Machine */
/* The encoding of the states is not supported by the Diagnostics Tool */

/*	Q_T2			32 bit	Test Register 2	*/
								/* Bit 31.. 8:	reserved */
#define T2_AC_T_ON		BIT_7	/* Address Counter Test Mode on */
#define T2_AC_T_OFF		BIT_6	/* Address Counter Test Mode off */
#define T2_BC_T_ON		BIT_5	/* Byte Counter Test Mode on */
#define T2_BC_T_OFF		BIT_4	/* Byte Counter Test Mode off */
#define T2_STEP04		BIT_3	/* Inc AC/Dec BC by 4 */
#define T2_STEP03		BIT_2	/* Inc AC/Dec BC by 3 */
#define T2_STEP02		BIT_1	/* Inc AC/Dec BC by 2 */
#define T2_STEP01		BIT_0	/* Inc AC/Dec BC by 1 */

/*	Q_T3			32 bit	Test Register 3	*/
								/* Bit 31.. 7:	reserved */
#define T3_MUX_MSK		(7<<4)	/* Bit  6.. 4:	Mux Position */
								/* Bit  3:	reserved */
#define T3_VRAM_MSK		7		/* Bit  2.. 0:	Virtual RAM Buffer Address */

/* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */
/*	RB_START		32 bit	RAM Buffer Start Address */
/*	RB_END			32 bit	RAM Buffer End Address */
/*	RB_WP			32 bit	RAM Buffer Write Pointer */
/*	RB_RP			32 bit	RAM Buffer Read Pointer */
/*	RB_RX_UTPP		32 bit	Rx Upper Threshold, Pause Pack */
/*	RB_RX_LTPP		32 bit	Rx Lower Threshold, Pause Pack */
/*	RB_RX_UTHP		32 bit	Rx Upper Threshold, High Prio */
/*	RB_RX_LTHP		32 bit	Rx Lower Threshold, High Prio */
/*	RB_PC			32 bit	RAM Buffer Packet Counter */
/*	RB_LEV			32 bit	RAM Buffer Level Register */
				/* Bit 31..19:	reserved */
#define RB_MSK	0x0007ffff	/* Bit 18.. 0:	RAM Buffer Pointer Bits */

/*	RB_TST2			 8 bit	RAM Buffer Test Register 2 */
								/* Bit 7.. 4:	reserved */
#define RB_PC_DEC		BIT_3S	/* Packet Counter Decrem */
#define RB_PC_T_ON		BIT_2S	/* Packet Counter Test On */
#define RB_PC_T_OFF		BIT_1S	/* Packet Counter Tst Off */
#define RB_PC_INC		BIT_0S	/* Packet Counter Increm */

/*	RB_TST1			 8 bit	RAM Buffer Test Register 1 */
							/* Bit 7:	reserved */
#define RB_WP_T_ON		BIT_6S	/* Write Pointer Test On */
#define RB_WP_T_OFF		BIT_5S	/* Write Pointer Test Off */
#define RB_WP_INC		BIT_4S	/* Write Pointer Increm */
								/* Bit 3:	reserved */
#define RB_RP_T_ON		BIT_2S	/* Read Pointer Test On */
#define RB_RP_T_OFF		BIT_1S	/* Read Pointer Test Off */
#define RB_RP_DEC		BIT_0S	/* Read Pointer Decrement */

/*	RB_CTRL			 8 bit	RAM Buffer Control Register */
								/* Bit 7.. 6:	reserved */
#define RB_ENA_STFWD	BIT_5S	/* Enable  Store & Forward */
#define RB_DIS_STFWD	BIT_4S	/* Disable Store & Forward */
#define RB_ENA_OP_MD	BIT_3S	/* Enable  Operation Mode */
#define RB_DIS_OP_MD	BIT_2S	/* Disable Operation Mode */
#define RB_RST_CLR		BIT_1S	/* Clear RAM Buf STM Reset */
#define RB_RST_SET		BIT_0S	/* Set   RAM Buf STM Reset */


/* Receive and Transmit MAC FIFO Registers (GENESIS only) */

/*	RX_MFF_EA		32 bit	Receive MAC FIFO End Address */
/*	RX_MFF_WP		32 bit 	Receive MAC FIFO Write Pointer */
/*	RX_MFF_RP		32 bit	Receive MAC FIFO Read Pointer */
/*	RX_MFF_PC		32 bit	Receive MAC FIFO Packet Counter */
/*	RX_MFF_LEV		32 bit	Receive MAC FIFO Level */
/*	TX_MFF_EA		32 bit	Transmit MAC FIFO End Address */
/*	TX_MFF_WP		32 bit 	Transmit MAC FIFO Write Pointer */
/*	TX_MFF_WSP		32 bit	Transmit MAC FIFO WR Shadow Pointer */
/*	TX_MFF_RP		32 bit	Transmit MAC FIFO Read Pointer */
/*	TX_MFF_PC		32 bit	Transmit MAC FIFO Packet Cnt */
/*	TX_MFF_LEV		32 bit	Transmit MAC FIFO Level */
								/* Bit 31.. 6:	reserved */
#define MFF_MSK			0x007fL	/* Bit	5.. 0:	MAC FIFO Address/Ptr Bits */

/*	RX_MFF_CTRL1	16 bit	Receive MAC FIFO Control Reg 1 */
								/* Bit 15..14:	reserved */
#define MFF_ENA_RDY_PAT	BIT_13S		/* Enable  Ready Patch */
#define MFF_DIS_RDY_PAT	BIT_12S		/* Disable Ready Patch */
#define MFF_ENA_TIM_PAT	BIT_11S		/* Enable  Timing Patch */
#define MFF_DIS_TIM_PAT	BIT_10S		/* Disable Timing Patch */
#define MFF_ENA_ALM_FUL	BIT_9S		/* Enable  AlmostFull Sign */
#define MFF_DIS_ALM_FUL	BIT_8S		/* Disable AlmostFull Sign */
#define MFF_ENA_PAUSE	BIT_7S		/* Enable  Pause Signaling */
#define MFF_DIS_PAUSE	BIT_6S		/* Disable Pause Signaling */
#define MFF_ENA_FLUSH	BIT_5S		/* Enable  Frame Flushing */
#define MFF_DIS_FLUSH	BIT_4S		/* Disable Frame Flushing */
#define MFF_ENA_TIST	BIT_3S		/* Enable  Time Stamp Gener */
#define MFF_DIS_TIST	BIT_2S		/* Disable Time Stamp Gener */
#define MFF_CLR_INTIST	BIT_1S		/* Clear IRQ No Time Stamp */
#define MFF_CLR_INSTAT	BIT_0S		/* Clear IRQ No Status */

#define MFF_RX_CTRL_DEF MFF_ENA_TIM_PAT

/*	TX_MFF_CTRL1	16 bit	Transmit MAC FIFO Control Reg 1 */
#define MFF_CLR_PERR	BIT_15S		/* Clear Parity Error IRQ */
								/* Bit 14:	reserved */
#define MFF_ENA_PKT_REC	BIT_13S		/* Enable  Packet Recovery */
#define MFF_DIS_PKT_REC BIT_12S		/* Disable Packet Recovery */
/*	MFF_ENA_TIM_PAT	 (see RX_MFF_CTRL1) Bit 11:	Enable  Timing Patch */
/*	MFF_DIS_TIM_PAT	 (see RX_MFF_CTRL1) Bit 10:	Disable Timing Patch */
/*	MFF_ENA_ALM_FUL	 (see RX_MFF_CTRL1) Bit	 9:	Enable  Almost Full Sign */
/*	MFF_DIS_ALM_FUL	 (see RX_MFF_CTRL1) Bit	 8:	Disable Almost Full Sign */
#define MFF_ENA_W4E		BIT_7S		/* Enable  Wait for Empty */
#define MFF_DIS_W4E		BIT_6S		/* Disable Wait for Empty */
/*	MFF_ENA_FLUSH	 (see RX_MFF_CTRL1) Bit	 5:	Enable  Frame Flushing */
/*	MFF_DIS_FLUSH	 (see RX_MFF_CTRL1) Bit	 4:	Disable Frame Flushing */
#define MFF_ENA_LOOPB	BIT_3S		/* Enable  Loopback */
#define MFF_DIS_LOOPB	BIT_2S		/* Disable Loopback */
#define MFF_CLR_MAC_RST	BIT_1S		/* Clear XMAC Reset */
#define MFF_SET_MAC_RST	BIT_0S		/* Set   XMAC Reset */

#define MFF_TX_CTRL_DEF	(MFF_ENA_PKT_REC | MFF_ENA_TIM_PAT | MFF_ENA_FLUSH)

/*	RX_MFF_TST2	 	 8 bit	Receive MAC FIFO Test Register 2 */
/*	TX_MFF_TST2	 	 8 bit	Transmit MAC FIFO Test Register 2 */
								/* Bit 7:	reserved */
#define MFF_WSP_T_ON	BIT_6S	/* Tx: Write Shadow Ptr TestOn */
#define MFF_WSP_T_OFF	BIT_5S	/* Tx: Write Shadow Ptr TstOff */
#define MFF_WSP_INC		BIT_4S	/* Tx: Write Shadow Ptr Increment */
#define MFF_PC_DEC		BIT_3S	/* Packet Counter Decrement */
#define MFF_PC_T_ON		BIT_2S	/* Packet Counter Test On */
#define MFF_PC_T_OFF	BIT_1S	/* Packet Counter Test Off */
#define MFF_PC_INC		BIT_0S	/* Packet Counter Increment */

/*	RX_MFF_TST1	 	 8 bit	Receive MAC FIFO Test Register 1 */
/*	TX_MFF_TST1	 	 8 bit	Transmit MAC FIFO Test Register 1 */
					/* Bit 7:	reserved */
#define MFF_WP_T_ON		BIT_6S	/* Write Pointer Test On */
#define MFF_WP_T_OFF	BIT_5S	/* Write Pointer Test Off */
#define MFF_WP_INC		BIT_4S	/* Write Pointer Increm */
							/* Bit 3:	reserved */
#define MFF_RP_T_ON		BIT_2S	/* Read Pointer Test On */
#define MFF_RP_T_OFF	BIT_1S	/* Read Pointer Test Off */
#define MFF_RP_DEC		BIT_0S	/* Read Pointer Decrement */

/*	RX_MFF_CTRL2	 8 bit	Receive MAC FIFO Control Reg 2 */
/*	TX_MFF_CTRL2	 8 bit	Transmit MAC FIFO Control Reg 2 */
								/* Bit 7..4:	reserved */
#define MFF_ENA_OP_MD	BIT_3S	/* Enable  Operation Mode */
#define MFF_DIS_OP_MD	BIT_2S	/* Disable Operation Mode */
#define MFF_RST_CLR		BIT_1S	/* Clear MAC FIFO Reset */
#define MFF_RST_SET		BIT_0S	/* Set   MAC FIFO Reset */


/*	Link LED Counter Registers (GENESIS only) */

/*	RX_LED_CTRL		 8 bit	Receive LED Cnt Control Reg */
/*	TX_LED_CTRL		 8 bit	Transmit LED Cnt Control Reg */
/*	LNK_SYNC_CTRL	 8 bit	Link Sync Cnt Control Register */
							/* Bit 7.. 3:	reserved */
#define LED_START		BIT_2S	/* Start Timer */
#define LED_STOP		BIT_1S	/* Stop Timer */
#define LED_STATE		BIT_0S	/* Rx/Tx: LED State, 1=LED on */
#define LED_CLR_IRQ		BIT_0S	/* Lnk: 	Clear Link IRQ */

/*	RX_LED_TST		 8 bit	Receive LED Cnt Test Register */
/*	TX_LED_TST		 8 bit	Transmit LED Cnt Test Register */
/*	LNK_SYNC_TST	 8 bit	Link Sync Cnt Test Register */
							/* Bit 7.. 3:	reserved */
#define LED_T_ON		BIT_2S	/* LED Counter Test mode On */
#define LED_T_OFF		BIT_1S	/* LED Counter Test mode Off */
#define LED_T_STEP		BIT_0S	/* LED Counter Step */

/*	LNK_LED_REG	 	 8 bit	Link LED Register */
								/* Bit 7.. 6:	reserved */
#define LED_BLK_ON		BIT_5S	/* Link LED Blinking On */
#define LED_BLK_OFF		BIT_4S	/* Link LED Blinking Off */
#define LED_SYNC_ON		BIT_3S	/* Use Sync Wire to switch LED */
#define LED_SYNC_OFF	BIT_2S	/* Disable Sync Wire Input */
#define LED_ON			BIT_1S	/* switch LED on */
#define LED_OFF			BIT_0S	/* switch LED off */

/*	Receive and Transmit GMAC FIFO Registers (YUKON only) */

/*	RX_GMF_EA		32 bit	Rx GMAC FIFO End Address */
/*	RX_GMF_AF_THR	32 bit	Rx GMAC FIFO Almost Full Thresh. */
/*	RX_GMF_WP		32 bit 	Rx GMAC FIFO Write Pointer */
/*	RX_GMF_WLEV		32 bit 	Rx GMAC FIFO Write Level */
/*	RX_GMF_RP		32 bit 	Rx GMAC FIFO Read Pointer */
/*	RX_GMF_RLEV		32 bit 	Rx GMAC FIFO Read Level */
/*	TX_GMF_EA		32 bit	Tx GMAC FIFO End Address */
/*	TX_GMF_AE_THR	32 bit	Tx GMAC FIFO Almost Empty Thresh.*/
/*	TX_GMF_WP		32 bit 	Tx GMAC FIFO Write Pointer */
/*	TX_GMF_WSP		32 bit 	Tx GMAC FIFO Write Shadow Ptr. */
/*	TX_GMF_WLEV		32 bit 	Tx GMAC FIFO Write Level */
/*	TX_GMF_RP		32 bit 	Tx GMAC FIFO Read Pointer */
/*	TX_GMF_RSTP		32 bit 	Tx GMAC FIFO Restart Pointer */
/*	TX_GMF_RLEV		32 bit 	Tx GMAC FIFO Read Level */

/*	RX_GMF_CTRL_T	32 bit	Rx GMAC FIFO Control/Test */
						/* Bits 31..15:	reserved */
#define GMF_WP_TST_ON	BIT_14		/* Write Pointer Test On */
#define GMF_WP_TST_OFF	BIT_13		/* Write Pointer Test Off */
#define GMF_WP_STEP		BIT_12		/* Write Pointer Step/Increment */
						/* Bit 11:	reserved */
#define GMF_RP_TST_ON	BIT_10		/* Read Pointer Test On */
#define GMF_RP_TST_OFF	BIT_9		/* Read Pointer Test Off */
#define GMF_RP_STEP		BIT_8		/* Read Pointer Step/Increment */
#define GMF_RX_F_FL_ON	BIT_7		/* Rx FIFO Flush Mode On */
#define GMF_RX_F_FL_OFF	BIT_6		/* Rx FIFO Flush Mode Off */
#define GMF_CLI_RX_FO	BIT_5		/* Clear IRQ Rx FIFO Overrun */
#define GMF_CLI_RX_FC	BIT_4		/* Clear IRQ Rx Frame Complete */
#define GMF_OPER_ON		BIT_3		/* Operational Mode On */
#define GMF_OPER_OFF	BIT_2		/* Operational Mode Off */
#define GMF_RST_CLR		BIT_1		/* Clear GMAC FIFO Reset */
#define GMF_RST_SET		BIT_0		/* Set   GMAC FIFO Reset */

/*	TX_GMF_CTRL_T	32 bit	Tx GMAC FIFO Control/Test */
						/* Bits 31..19:	reserved */
#define GMF_WSP_TST_ON	BIT_18		/* Write Shadow Pointer Test On */
#define GMF_WSP_TST_OFF	BIT_17		/* Write Shadow Pointer Test Off */
#define GMF_WSP_STEP	BIT_16		/* Write Shadow Pointer Step/Increment */
						/* Bits 15..7: same as for RX_GMF_CTRL_T */
#define GMF_CLI_TX_FU	BIT_6		/* Clear IRQ Tx FIFO Underrun */
#define GMF_CLI_TX_FC	BIT_5		/* Clear IRQ Tx Frame Complete */
#define GMF_CLI_TX_PE	BIT_4		/* Clear IRQ Tx Parity Error */
						/* Bits 3..0: same as for RX_GMF_CTRL_T */

#define GMF_RX_CTRL_DEF		(GMF_OPER_ON | GMF_RX_F_FL_ON)
#define GMF_TX_CTRL_DEF		GMF_OPER_ON

#define RX_GMF_FL_THR_DEF	0x0a	/* Rx GMAC FIFO Flush Threshold default */

/*	GMAC_TI_ST_CTRL	 8 bit	Time Stamp Timer Ctrl Reg (YUKON only) */
								/* Bit 7.. 3:	reserved */
#define GMT_ST_START	BIT_2S		/* Start Time Stamp Timer */
#define GMT_ST_STOP		BIT_1S		/* Stop  Time Stamp Timer */
#define GMT_ST_CLR_IRQ	BIT_0S		/* Clear Time Stamp Timer IRQ */

/*	GMAC_CTRL		32 bit	GMAC Control Reg (YUKON only) */
						/* Bits 31.. 8:	reserved */
#define GMC_H_BURST_ON	BIT_7		/* Half Duplex Burst Mode On */
#define GMC_H_BURST_OFF	BIT_6		/* Half Duplex Burst Mode Off */
#define GMC_F_LOOPB_ON	BIT_5		/* FIFO Loopback On */
#define GMC_F_LOOPB_OFF	BIT_4		/* FIFO Loopback Off */
#define GMC_PAUSE_ON	BIT_3		/* Pause On */
#define GMC_PAUSE_OFF	BIT_2		/* Pause Off */
#define GMC_RST_CLR		BIT_1		/* Clear GMAC Reset */
#define GMC_RST_SET		BIT_0		/* Set   GMAC Reset */

/*	GPHY_CTRL		32 bit	GPHY Control Reg (YUKON