regs.h

linux-2.6.15.6

#define S_TCP_CSUM    11
#define V_TCP_CSUM(x) ((x) << S_TCP_CSUM)
#define F_TCP_CSUM    V_TCP_CSUM(1U)

#define S_UDP_CSUM    12
#define V_UDP_CSUM(x) ((x) << S_UDP_CSUM)
#define F_UDP_CSUM    V_UDP_CSUM(1U)

#define S_IP_CSUM    13
#define V_IP_CSUM(x) ((x) << S_IP_CSUM)
#define F_IP_CSUM    V_IP_CSUM(1U)

#define S_PATH_MTU    15
#define V_PATH_MTU(x) ((x) << S_PATH_MTU)
#define F_PATH_MTU    V_PATH_MTU(1U)

#define S_5TUPLE_LOOKUP    17
#define V_5TUPLE_LOOKUP(x) ((x) << S_5TUPLE_LOOKUP)

#define S_SYN_COOKIE_PARAMETER    26
#define V_SYN_COOKIE_PARAMETER(x) ((x) << S_SYN_COOKIE_PARAMETER)

#define A_TP_PC_CONFIG 0x348
#define S_DIS_TX_FILL_WIN_PUSH    12
#define V_DIS_TX_FILL_WIN_PUSH(x) ((x) << S_DIS_TX_FILL_WIN_PUSH)
#define F_DIS_TX_FILL_WIN_PUSH    V_DIS_TX_FILL_WIN_PUSH(1U)

#define S_TP_PC_REV    30
#define M_TP_PC_REV    0x3
#define G_TP_PC_REV(x) (((x) >> S_TP_PC_REV) & M_TP_PC_REV)
#define A_TP_RESET 0x44c
#define S_TP_RESET    0
#define V_TP_RESET(x) ((x) << S_TP_RESET)
#define F_TP_RESET    V_TP_RESET(1U)

#define A_TP_INT_ENABLE 0x470
#define A_TP_INT_CAUSE 0x474
#define A_TP_TX_DROP_CONFIG 0x4b8

#define S_ENABLE_TX_DROP    31
#define V_ENABLE_TX_DROP(x) ((x) << S_ENABLE_TX_DROP)
#define F_ENABLE_TX_DROP    V_ENABLE_TX_DROP(1U)

#define S_ENABLE_TX_ERROR    30
#define V_ENABLE_TX_ERROR(x) ((x) << S_ENABLE_TX_ERROR)
#define F_ENABLE_TX_ERROR    V_ENABLE_TX_ERROR(1U)

#define S_DROP_TICKS_CNT    4
#define V_DROP_TICKS_CNT(x) ((x) << S_DROP_TICKS_CNT)

#define S_NUM_PKTS_DROPPED    0
#define V_NUM_PKTS_DROPPED(x) ((x) << S_NUM_PKTS_DROPPED)

/* CSPI registers */

#define S_DIP4ERR    0
#define V_DIP4ERR(x) ((x) << S_DIP4ERR)
#define F_DIP4ERR    V_DIP4ERR(1U)

#define S_RXDROP    1
#define V_RXDROP(x) ((x) << S_RXDROP)
#define F_RXDROP    V_RXDROP(1U)

#define S_TXDROP    2
#define V_TXDROP(x) ((x) << S_TXDROP)
#define F_TXDROP    V_TXDROP(1U)

#define S_RXOVERFLOW    3
#define V_RXOVERFLOW(x) ((x) << S_RXOVERFLOW)
#define F_RXOVERFLOW    V_RXOVERFLOW(1U)

#define S_RAMPARITYERR    4
#define V_RAMPARITYERR(x) ((x) << S_RAMPARITYERR)
#define F_RAMPARITYERR    V_RAMPARITYERR(1U)

/* ESPI registers */

#define A_ESPI_SCH_TOKEN0 0x880
#define A_ESPI_SCH_TOKEN1 0x884
#define A_ESPI_SCH_TOKEN2 0x888
#define A_ESPI_SCH_TOKEN3 0x88c
#define A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK 0x890
#define A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK 0x894
#define A_ESPI_CALENDAR_LENGTH 0x898
#define A_PORT_CONFIG 0x89c

#define S_RX_NPORTS    0
#define V_RX_NPORTS(x) ((x) << S_RX_NPORTS)

#define S_TX_NPORTS    8
#define V_TX_NPORTS(x) ((x) << S_TX_NPORTS)

#define A_ESPI_FIFO_STATUS_ENABLE 0x8a0

#define S_RXSTATUSENABLE    0
#define V_RXSTATUSENABLE(x) ((x) << S_RXSTATUSENABLE)
#define F_RXSTATUSENABLE    V_RXSTATUSENABLE(1U)

#define S_INTEL1010MODE    4
#define V_INTEL1010MODE(x) ((x) << S_INTEL1010MODE)
#define F_INTEL1010MODE    V_INTEL1010MODE(1U)

#define A_ESPI_MAXBURST1_MAXBURST2 0x8a8
#define A_ESPI_TRAIN 0x8ac
#define A_ESPI_INTR_STATUS 0x8c8

#define S_DIP2PARITYERR    5
#define V_DIP2PARITYERR(x) ((x) << S_DIP2PARITYERR)
#define F_DIP2PARITYERR    V_DIP2PARITYERR(1U)

#define A_ESPI_INTR_ENABLE 0x8cc
#define A_RX_DROP_THRESHOLD 0x8d0
#define A_ESPI_RX_RESET 0x8ec
#define A_ESPI_MISC_CONTROL 0x8f0

#define S_OUT_OF_SYNC_COUNT    0
#define V_OUT_OF_SYNC_COUNT(x) ((x) << S_OUT_OF_SYNC_COUNT)

#define S_DIP2_PARITY_ERR_THRES    5
#define V_DIP2_PARITY_ERR_THRES(x) ((x) << S_DIP2_PARITY_ERR_THRES)

#define S_DIP4_THRES    9
#define V_DIP4_THRES(x) ((x) << S_DIP4_THRES)

#define S_MONITORED_PORT_NUM    25
#define V_MONITORED_PORT_NUM(x) ((x) << S_MONITORED_PORT_NUM)

#define S_MONITORED_DIRECTION    27
#define V_MONITORED_DIRECTION(x) ((x) << S_MONITORED_DIRECTION)
#define F_MONITORED_DIRECTION    V_MONITORED_DIRECTION(1U)

#define S_MONITORED_INTERFACE    28
#define V_MONITORED_INTERFACE(x) ((x) << S_MONITORED_INTERFACE)
#define F_MONITORED_INTERFACE    V_MONITORED_INTERFACE(1U)

#define A_ESPI_DIP2_ERR_COUNT 0x8f4
#define A_ESPI_CMD_ADDR 0x8f8

#define S_WRITE_DATA    0
#define V_WRITE_DATA(x) ((x) << S_WRITE_DATA)

#define S_REGISTER_OFFSET    8
#define V_REGISTER_OFFSET(x) ((x) << S_REGISTER_OFFSET)

#define S_CHANNEL_ADDR    12
#define V_CHANNEL_ADDR(x) ((x) << S_CHANNEL_ADDR)

#define S_MODULE_ADDR    16
#define V_MODULE_ADDR(x) ((x) << S_MODULE_ADDR)

#define S_BUNDLE_ADDR    20
#define V_BUNDLE_ADDR(x) ((x) << S_BUNDLE_ADDR)

#define S_SPI4_COMMAND    24
#define V_SPI4_COMMAND(x) ((x) << S_SPI4_COMMAND)

#define A_ESPI_GOSTAT 0x8fc
#define S_ESPI_CMD_BUSY    8
#define V_ESPI_CMD_BUSY(x) ((x) << S_ESPI_CMD_BUSY)
#define F_ESPI_CMD_BUSY    V_ESPI_CMD_BUSY(1U)

/* PL registers */

#define A_PL_ENABLE 0xa00

#define S_PL_INTR_SGE_ERR    0
#define V_PL_INTR_SGE_ERR(x) ((x) << S_PL_INTR_SGE_ERR)
#define F_PL_INTR_SGE_ERR    V_PL_INTR_SGE_ERR(1U)

#define S_PL_INTR_SGE_DATA    1
#define V_PL_INTR_SGE_DATA(x) ((x) << S_PL_INTR_SGE_DATA)
#define F_PL_INTR_SGE_DATA    V_PL_INTR_SGE_DATA(1U)

#define S_PL_INTR_TP    6
#define V_PL_INTR_TP(x) ((x) << S_PL_INTR_TP)
#define F_PL_INTR_TP    V_PL_INTR_TP(1U)

#define S_PL_INTR_ESPI    8
#define V_PL_INTR_ESPI(x) ((x) << S_PL_INTR_ESPI)
#define F_PL_INTR_ESPI    V_PL_INTR_ESPI(1U)

#define S_PL_INTR_PCIX    10
#define V_PL_INTR_PCIX(x) ((x) << S_PL_INTR_PCIX)
#define F_PL_INTR_PCIX    V_PL_INTR_PCIX(1U)

#define S_PL_INTR_EXT    11
#define V_PL_INTR_EXT(x) ((x) << S_PL_INTR_EXT)
#define F_PL_INTR_EXT    V_PL_INTR_EXT(1U)

#define A_PL_CAUSE 0xa04

/* MC5 registers */

#define A_MC5_CONFIG 0xc04

#define S_TCAM_RESET    1
#define V_TCAM_RESET(x) ((x) << S_TCAM_RESET)
#define F_TCAM_RESET    V_TCAM_RESET(1U)

#define S_M_BUS_ENABLE    5
#define V_M_BUS_ENABLE(x) ((x) << S_M_BUS_ENABLE)
#define F_M_BUS_ENABLE    V_M_BUS_ENABLE(1U)

/* PCICFG registers */

#define A_PCICFG_PM_CSR 0x44
#define A_PCICFG_VPD_ADDR 0x4a

#define S_VPD_OP_FLAG    15
#define V_VPD_OP_FLAG(x) ((x) << S_VPD_OP_FLAG)
#define F_VPD_OP_FLAG    V_VPD_OP_FLAG(1U)

#define A_PCICFG_VPD_DATA 0x4c

#define A_PCICFG_INTR_ENABLE 0xf4
#define A_PCICFG_INTR_CAUSE 0xf8

#define A_PCICFG_MODE 0xfc

#define S_PCI_MODE_64BIT    0
#define V_PCI_MODE_64BIT(x) ((x) << S_PCI_MODE_64BIT)
#define F_PCI_MODE_64BIT    V_PCI_MODE_64BIT(1U)

#define S_PCI_MODE_PCIX    5
#define V_PCI_MODE_PCIX(x) ((x) << S_PCI_MODE_PCIX)
#define F_PCI_MODE_PCIX    V_PCI_MODE_PCIX(1U)

#define S_PCI_MODE_CLK    6
#define M_PCI_MODE_CLK    0x3
#define G_PCI_MODE_CLK(x) (((x) >> S_PCI_MODE_CLK) & M_PCI_MODE_CLK)

#endif /* _CXGB_REGS_H_ */