📄 regs.h
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/***************************************************************************** * * * File: regs.h * * $Revision: 1.8 $ * * $Date: 2005/06/21 18:29:48 $ * * Description: * * part of the Chelsio 10Gb Ethernet Driver. * * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License, version 2, as * * published by the Free Software Foundation. * * * * You should have received a copy of the GNU General Public License along * * with this program; if not, write to the Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * * * * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED * * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF * * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. * * * * http://www.chelsio.com * * * * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. * * All rights reserved. * * * * Maintainers: maintainers@chelsio.com * * * * Authors: Dimitrios Michailidis <dm@chelsio.com> * * Tina Yang <tainay@chelsio.com> * * Felix Marti <felix@chelsio.com> * * Scott Bardone <sbardone@chelsio.com> * * Kurt Ottaway <kottaway@chelsio.com> * * Frank DiMambro <frank@chelsio.com> * * * * History: * * * ****************************************************************************/#ifndef _CXGB_REGS_H_#define _CXGB_REGS_H_/* SGE registers */#define A_SG_CONTROL 0x0#define S_CMDQ0_ENABLE 0#define V_CMDQ0_ENABLE(x) ((x) << S_CMDQ0_ENABLE)#define F_CMDQ0_ENABLE V_CMDQ0_ENABLE(1U)#define S_CMDQ1_ENABLE 1#define V_CMDQ1_ENABLE(x) ((x) << S_CMDQ1_ENABLE)#define F_CMDQ1_ENABLE V_CMDQ1_ENABLE(1U)#define S_FL0_ENABLE 2#define V_FL0_ENABLE(x) ((x) << S_FL0_ENABLE)#define F_FL0_ENABLE V_FL0_ENABLE(1U)#define S_FL1_ENABLE 3#define V_FL1_ENABLE(x) ((x) << S_FL1_ENABLE)#define F_FL1_ENABLE V_FL1_ENABLE(1U)#define S_CPL_ENABLE 4#define V_CPL_ENABLE(x) ((x) << S_CPL_ENABLE)#define F_CPL_ENABLE V_CPL_ENABLE(1U)#define S_RESPONSE_QUEUE_ENABLE 5#define V_RESPONSE_QUEUE_ENABLE(x) ((x) << S_RESPONSE_QUEUE_ENABLE)#define F_RESPONSE_QUEUE_ENABLE V_RESPONSE_QUEUE_ENABLE(1U)#define S_CMDQ_PRIORITY 6#define M_CMDQ_PRIORITY 0x3#define V_CMDQ_PRIORITY(x) ((x) << S_CMDQ_PRIORITY)#define G_CMDQ_PRIORITY(x) (((x) >> S_CMDQ_PRIORITY) & M_CMDQ_PRIORITY)#define S_DISABLE_CMDQ1_GTS 9#define V_DISABLE_CMDQ1_GTS(x) ((x) << S_DISABLE_CMDQ1_GTS)#define F_DISABLE_CMDQ1_GTS V_DISABLE_CMDQ1_GTS(1U)#define S_DISABLE_FL0_GTS 10#define V_DISABLE_FL0_GTS(x) ((x) << S_DISABLE_FL0_GTS)#define F_DISABLE_FL0_GTS V_DISABLE_FL0_GTS(1U)#define S_DISABLE_FL1_GTS 11#define V_DISABLE_FL1_GTS(x) ((x) << S_DISABLE_FL1_GTS)#define F_DISABLE_FL1_GTS V_DISABLE_FL1_GTS(1U)#define S_ENABLE_BIG_ENDIAN 12#define V_ENABLE_BIG_ENDIAN(x) ((x) << S_ENABLE_BIG_ENDIAN)#define F_ENABLE_BIG_ENDIAN V_ENABLE_BIG_ENDIAN(1U)#define S_ISCSI_COALESCE 14#define V_ISCSI_COALESCE(x) ((x) << S_ISCSI_COALESCE)#define F_ISCSI_COALESCE V_ISCSI_COALESCE(1U)#define S_RX_PKT_OFFSET 15#define V_RX_PKT_OFFSET(x) ((x) << S_RX_PKT_OFFSET)#define S_VLAN_XTRACT 18#define V_VLAN_XTRACT(x) ((x) << S_VLAN_XTRACT)#define F_VLAN_XTRACT V_VLAN_XTRACT(1U)#define A_SG_DOORBELL 0x4#define A_SG_CMD0BASELWR 0x8#define A_SG_CMD0BASEUPR 0xc#define A_SG_CMD1BASELWR 0x10#define A_SG_CMD1BASEUPR 0x14#define A_SG_FL0BASELWR 0x18#define A_SG_FL0BASEUPR 0x1c#define A_SG_FL1BASELWR 0x20#define A_SG_FL1BASEUPR 0x24#define A_SG_CMD0SIZE 0x28#define A_SG_FL0SIZE 0x2c#define A_SG_RSPSIZE 0x30#define A_SG_RSPBASELWR 0x34#define A_SG_RSPBASEUPR 0x38#define A_SG_FLTHRESHOLD 0x3c#define A_SG_RSPQUEUECREDIT 0x40#define A_SG_SLEEPING 0x48#define A_SG_INTRTIMER 0x4c#define A_SG_CMD1SIZE 0xb0#define A_SG_FL1SIZE 0xb4#define A_SG_INT_ENABLE 0xb8#define S_RESPQ_EXHAUSTED 0#define V_RESPQ_EXHAUSTED(x) ((x) << S_RESPQ_EXHAUSTED)#define F_RESPQ_EXHAUSTED V_RESPQ_EXHAUSTED(1U)#define S_RESPQ_OVERFLOW 1#define V_RESPQ_OVERFLOW(x) ((x) << S_RESPQ_OVERFLOW)#define F_RESPQ_OVERFLOW V_RESPQ_OVERFLOW(1U)#define S_FL_EXHAUSTED 2#define V_FL_EXHAUSTED(x) ((x) << S_FL_EXHAUSTED)#define F_FL_EXHAUSTED V_FL_EXHAUSTED(1U)#define S_PACKET_TOO_BIG 3#define V_PACKET_TOO_BIG(x) ((x) << S_PACKET_TOO_BIG)#define F_PACKET_TOO_BIG V_PACKET_TOO_BIG(1U)#define S_PACKET_MISMATCH 4#define V_PACKET_MISMATCH(x) ((x) << S_PACKET_MISMATCH)#define F_PACKET_MISMATCH V_PACKET_MISMATCH(1U)#define A_SG_INT_CAUSE 0xbc#define A_SG_RESPACCUTIMER 0xc0/* MC3 registers */#define S_READY 1#define V_READY(x) ((x) << S_READY)#define F_READY V_READY(1U)/* MC4 registers */#define A_MC4_CFG 0x180#define S_MC4_SLOW 25#define V_MC4_SLOW(x) ((x) << S_MC4_SLOW)#define F_MC4_SLOW V_MC4_SLOW(1U)/* TPI registers */#define A_TPI_ADDR 0x280#define A_TPI_WR_DATA 0x284#define A_TPI_RD_DATA 0x288#define A_TPI_CSR 0x28c#define S_TPIWR 0#define V_TPIWR(x) ((x) << S_TPIWR)#define F_TPIWR V_TPIWR(1U)#define S_TPIRDY 1#define V_TPIRDY(x) ((x) << S_TPIRDY)#define F_TPIRDY V_TPIRDY(1U)#define A_TPI_PAR 0x29c#define S_TPIPAR 0#define M_TPIPAR 0x7f#define V_TPIPAR(x) ((x) << S_TPIPAR)#define G_TPIPAR(x) (((x) >> S_TPIPAR) & M_TPIPAR)/* TP registers */#define A_TP_IN_CONFIG 0x300#define S_TP_IN_CSPI_CPL 3#define V_TP_IN_CSPI_CPL(x) ((x) << S_TP_IN_CSPI_CPL)#define F_TP_IN_CSPI_CPL V_TP_IN_CSPI_CPL(1U)#define S_TP_IN_CSPI_CHECK_IP_CSUM 5#define V_TP_IN_CSPI_CHECK_IP_CSUM(x) ((x) << S_TP_IN_CSPI_CHECK_IP_CSUM)#define F_TP_IN_CSPI_CHECK_IP_CSUM V_TP_IN_CSPI_CHECK_IP_CSUM(1U)#define S_TP_IN_CSPI_CHECK_TCP_CSUM 6#define V_TP_IN_CSPI_CHECK_TCP_CSUM(x) ((x) << S_TP_IN_CSPI_CHECK_TCP_CSUM)#define F_TP_IN_CSPI_CHECK_TCP_CSUM V_TP_IN_CSPI_CHECK_TCP_CSUM(1U)#define S_TP_IN_ESPI_ETHERNET 8#define V_TP_IN_ESPI_ETHERNET(x) ((x) << S_TP_IN_ESPI_ETHERNET)#define F_TP_IN_ESPI_ETHERNET V_TP_IN_ESPI_ETHERNET(1U)#define S_TP_IN_ESPI_CHECK_IP_CSUM 12#define V_TP_IN_ESPI_CHECK_IP_CSUM(x) ((x) << S_TP_IN_ESPI_CHECK_IP_CSUM)#define F_TP_IN_ESPI_CHECK_IP_CSUM V_TP_IN_ESPI_CHECK_IP_CSUM(1U)#define S_TP_IN_ESPI_CHECK_TCP_CSUM 13#define V_TP_IN_ESPI_CHECK_TCP_CSUM(x) ((x) << S_TP_IN_ESPI_CHECK_TCP_CSUM)#define F_TP_IN_ESPI_CHECK_TCP_CSUM V_TP_IN_ESPI_CHECK_TCP_CSUM(1U)#define S_OFFLOAD_DISABLE 14#define V_OFFLOAD_DISABLE(x) ((x) << S_OFFLOAD_DISABLE)#define F_OFFLOAD_DISABLE V_OFFLOAD_DISABLE(1U)#define A_TP_OUT_CONFIG 0x304#define S_TP_OUT_CSPI_CPL 2#define V_TP_OUT_CSPI_CPL(x) ((x) << S_TP_OUT_CSPI_CPL)#define F_TP_OUT_CSPI_CPL V_TP_OUT_CSPI_CPL(1U)#define S_TP_OUT_ESPI_ETHERNET 6#define V_TP_OUT_ESPI_ETHERNET(x) ((x) << S_TP_OUT_ESPI_ETHERNET)#define F_TP_OUT_ESPI_ETHERNET V_TP_OUT_ESPI_ETHERNET(1U)#define S_TP_OUT_ESPI_GENERATE_IP_CSUM 10#define V_TP_OUT_ESPI_GENERATE_IP_CSUM(x) ((x) << S_TP_OUT_ESPI_GENERATE_IP_CSUM)#define F_TP_OUT_ESPI_GENERATE_IP_CSUM V_TP_OUT_ESPI_GENERATE_IP_CSUM(1U)#define S_TP_OUT_ESPI_GENERATE_TCP_CSUM 11#define V_TP_OUT_ESPI_GENERATE_TCP_CSUM(x) ((x) << S_TP_OUT_ESPI_GENERATE_TCP_CSUM)#define F_TP_OUT_ESPI_GENERATE_TCP_CSUM V_TP_OUT_ESPI_GENERATE_TCP_CSUM(1U)#define A_TP_GLOBAL_CONFIG 0x308#define S_IP_TTL 0#define M_IP_TTL 0xff#define V_IP_TTL(x) ((x) << S_IP_TTL)⌨️ 快捷键说明
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