📄 ipw2100.h
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#define IPW2100_WEP_DROP_CLEAR (1<<2)#define IPW_NONE_CIPHER (1<<0)#define IPW_WEP40_CIPHER (1<<1)#define IPW_TKIP_CIPHER (1<<2)#define IPW_CCMP_CIPHER (1<<4)#define IPW_WEP104_CIPHER (1<<5)#define IPW_CKIP_CIPHER (1<<6)#define IPW_AUTH_OPEN 0#define IPW_AUTH_SHARED 1struct statistic { int value; int hi; int lo;};#define INIT_STAT(x) do { \ (x)->value = (x)->hi = 0; \ (x)->lo = 0x7fffffff; \} while (0)#define SET_STAT(x,y) do { \ (x)->value = y; \ if ((x)->value > (x)->hi) (x)->hi = (x)->value; \ if ((x)->value < (x)->lo) (x)->lo = (x)->value; \} while (0)#define INC_STAT(x) do { if (++(x)->value > (x)->hi) (x)->hi = (x)->value; } \while (0)#define DEC_STAT(x) do { if (--(x)->value < (x)->lo) (x)->lo = (x)->value; } \while (0)#define IPW2100_ERROR_QUEUE 5/* Power management code: enable or disable? */enum {#ifdef CONFIG_PM IPW2100_PM_DISABLED = 0, PM_STATE_SIZE = 16,#else IPW2100_PM_DISABLED = 1, PM_STATE_SIZE = 0,#endif};#define STATUS_POWERED (1<<0)#define STATUS_CMD_ACTIVE (1<<1) /**< host command in progress */#define STATUS_RUNNING (1<<2) /* Card initialized, but not enabled */#define STATUS_ENABLED (1<<3) /* Card enabled -- can scan,Tx,Rx */#define STATUS_STOPPING (1<<4) /* Card is in shutdown phase */#define STATUS_INITIALIZED (1<<5) /* Card is ready for external calls */#define STATUS_ASSOCIATING (1<<9) /* Associated, but no BSSID yet */#define STATUS_ASSOCIATED (1<<10) /* Associated and BSSID valid */#define STATUS_INT_ENABLED (1<<11)#define STATUS_RF_KILL_HW (1<<12)#define STATUS_RF_KILL_SW (1<<13)#define STATUS_RF_KILL_MASK (STATUS_RF_KILL_HW | STATUS_RF_KILL_SW)#define STATUS_EXIT_PENDING (1<<14)#define STATUS_SCAN_PENDING (1<<23)#define STATUS_SCANNING (1<<24)#define STATUS_SCAN_ABORTING (1<<25)#define STATUS_SCAN_COMPLETE (1<<26)#define STATUS_WX_EVENT_PENDING (1<<27)#define STATUS_RESET_PENDING (1<<29)#define STATUS_SECURITY_UPDATED (1<<30) /* Security sync needed *//* Internal NIC states */#define IPW_STATE_INITIALIZED (1<<0)#define IPW_STATE_COUNTRY_FOUND (1<<1)#define IPW_STATE_ASSOCIATED (1<<2)#define IPW_STATE_ASSN_LOST (1<<3)#define IPW_STATE_ASSN_CHANGED (1<<4)#define IPW_STATE_SCAN_COMPLETE (1<<5)#define IPW_STATE_ENTERED_PSP (1<<6)#define IPW_STATE_LEFT_PSP (1<<7)#define IPW_STATE_RF_KILL (1<<8)#define IPW_STATE_DISABLED (1<<9)#define IPW_STATE_POWER_DOWN (1<<10)#define IPW_STATE_SCANNING (1<<11)#define CFG_STATIC_CHANNEL (1<<0) /* Restrict assoc. to single channel */#define CFG_STATIC_ESSID (1<<1) /* Restrict assoc. to single SSID */#define CFG_STATIC_BSSID (1<<2) /* Restrict assoc. to single BSSID */#define CFG_CUSTOM_MAC (1<<3)#define CFG_LONG_PREAMBLE (1<<4)#define CFG_ASSOCIATE (1<<6)#define CFG_FIXED_RATE (1<<7)#define CFG_ADHOC_CREATE (1<<8)#define CFG_C3_DISABLED (1<<9)#define CFG_PASSIVE_SCAN (1<<10)#ifdef CONFIG_IPW2100_MONITOR#define CFG_CRC_CHECK (1<<11)#endif#define CAP_SHARED_KEY (1<<0) /* Off = OPEN */#define CAP_PRIVACY_ON (1<<1) /* Off = No privacy */struct ipw2100_priv { int stop_hang_check; /* Set 1 when shutting down to kill hang_check */ int stop_rf_kill; /* Set 1 when shutting down to kill rf_kill */ struct ieee80211_device *ieee; unsigned long status; unsigned long config; unsigned long capability; /* Statistics */ int resets; int reset_backoff; /* Context */ u8 essid[IW_ESSID_MAX_SIZE]; u8 essid_len; u8 bssid[ETH_ALEN]; u8 channel; int last_mode; int cstate_limit; unsigned long connect_start; unsigned long last_reset; u32 channel_mask; u32 fatal_error; u32 fatal_errors[IPW2100_ERROR_QUEUE]; u32 fatal_index; int eeprom_version; int firmware_version; unsigned long hw_features; int hangs; u32 last_rtc; int dump_raw; /* 1 to dump raw bytes in /sys/.../memory */ u8 *snapshot[0x30]; u8 mandatory_bssid_mac[ETH_ALEN]; u8 mac_addr[ETH_ALEN]; int power_mode; int messages_sent; int short_retry_limit; int long_retry_limit; u32 rts_threshold; u32 frag_threshold; int in_isr; u32 tx_rates; int tx_power; u32 beacon_interval; char nick[IW_ESSID_MAX_SIZE + 1]; struct ipw2100_status_queue status_queue; struct statistic txq_stat; struct statistic rxq_stat; struct ipw2100_bd_queue rx_queue; struct ipw2100_bd_queue tx_queue; struct ipw2100_rx_packet *rx_buffers; struct statistic fw_pend_stat; struct list_head fw_pend_list; struct statistic msg_free_stat; struct statistic msg_pend_stat; struct list_head msg_free_list; struct list_head msg_pend_list; struct ipw2100_tx_packet *msg_buffers; struct statistic tx_free_stat; struct statistic tx_pend_stat; struct list_head tx_free_list; struct list_head tx_pend_list; struct ipw2100_tx_packet *tx_buffers; struct ipw2100_ordinals ordinals; struct pci_dev *pci_dev; struct proc_dir_entry *dir_dev; struct net_device *net_dev; struct iw_statistics wstats; struct iw_public_data wireless_data; struct tasklet_struct irq_tasklet; struct workqueue_struct *workqueue; struct work_struct reset_work; struct work_struct security_work; struct work_struct wx_event_work; struct work_struct hang_check; struct work_struct rf_kill; u32 interrupts; int tx_interrupts; int rx_interrupts; int inta_other; spinlock_t low_lock; struct semaphore action_sem; struct semaphore adapter_sem; wait_queue_head_t wait_command_queue;};/********************************************************* * Host Command -> From Driver to FW *********************************************************//** * Host command identifiers */#define HOST_COMPLETE 2#define SYSTEM_CONFIG 6#define SSID 8#define MANDATORY_BSSID 9#define AUTHENTICATION_TYPE 10#define ADAPTER_ADDRESS 11#define PORT_TYPE 12#define INTERNATIONAL_MODE 13#define CHANNEL 14#define RTS_THRESHOLD 15#define FRAG_THRESHOLD 16#define POWER_MODE 17#define TX_RATES 18#define BASIC_TX_RATES 19#define WEP_KEY_INFO 20#define WEP_KEY_INDEX 25#define WEP_FLAGS 26#define ADD_MULTICAST 27#define CLEAR_ALL_MULTICAST 28#define BEACON_INTERVAL 29#define ATIM_WINDOW 30#define CLEAR_STATISTICS 31#define SEND 33#define TX_POWER_INDEX 36#define BROADCAST_SCAN 43#define CARD_DISABLE 44#define PREFERRED_BSSID 45#define SET_SCAN_OPTIONS 46#define SCAN_DWELL_TIME 47#define SWEEP_TABLE 48#define AP_OR_STATION_TABLE 49#define GROUP_ORDINALS 50#define SHORT_RETRY_LIMIT 51#define LONG_RETRY_LIMIT 52#define HOST_PRE_POWER_DOWN 58#define CARD_DISABLE_PHY_OFF 61#define MSDU_TX_RATES 62/* Rogue AP Detection */#define SET_STATION_STAT_BITS 64#define CLEAR_STATIONS_STAT_BITS 65#define LEAP_ROGUE_MODE 66 //TODO tbw replaced by CFG_LEAP_ROGUE_AP#define SET_SECURITY_INFORMATION 67#define DISASSOCIATION_BSSID 68#define SET_WPA_IE 69/* system configuration bit mask: */#define IPW_CFG_MONITOR 0x00004#define IPW_CFG_PREAMBLE_AUTO 0x00010#define IPW_CFG_IBSS_AUTO_START 0x00020#define IPW_CFG_LOOPBACK 0x00100#define IPW_CFG_ANSWER_BCSSID_PROBE 0x00800#define IPW_CFG_BT_SIDEBAND_SIGNAL 0x02000#define IPW_CFG_802_1x_ENABLE 0x04000#define IPW_CFG_BSS_MASK 0x08000#define IPW_CFG_IBSS_MASK 0x10000#define IPW_SCAN_NOASSOCIATE (1<<0)#define IPW_SCAN_MIXED_CELL (1<<1)/* RESERVED (1<<2) */#define IPW_SCAN_PASSIVE (1<<3)#define IPW_NIC_FATAL_ERROR 0x2A7F0#define IPW_ERROR_ADDR(x) (x & 0x3FFFF)#define IPW_ERROR_CODE(x) ((x & 0xFF000000) >> 24)#define IPW2100_ERR_C3_CORRUPTION (0x10 << 24)#define IPW2100_ERR_MSG_TIMEOUT (0x11 << 24)#define IPW2100_ERR_FW_LOAD (0x12 << 24)#define IPW_MEM_SRAM_HOST_SHARED_LOWER_BOUND 0x200#define IPW_MEM_SRAM_HOST_INTERRUPT_AREA_LOWER_BOUND IPW_MEM_SRAM_HOST_SHARED_LOWER_BOUND + 0x0D80#define IPW_MEM_HOST_SHARED_RX_BD_BASE (IPW_MEM_SRAM_HOST_SHARED_LOWER_BOUND + 0x40)#define IPW_MEM_HOST_SHARED_RX_STATUS_BASE (IPW_MEM_SRAM_HOST_SHARED_LOWER_BOUND + 0x44)#define IPW_MEM_HOST_SHARED_RX_BD_SIZE (IPW_MEM_SRAM_HOST_SHARED_LOWER_BOUND + 0x48)#define IPW_MEM_HOST_SHARED_RX_READ_INDEX (IPW_MEM_SRAM_HOST_SHARED_LOWER_BOUND + 0xa0)#define IPW_MEM_HOST_SHARED_TX_QUEUE_BD_BASE (IPW_MEM_SRAM_HOST_SHARED_LOWER_BOUND + 0x00)#define IPW_MEM_HOST_SHARED_TX_QUEUE_BD_SIZE (IPW_MEM_SRAM_HOST_SHARED_LOWER_BOUND + 0x04)#define IPW_MEM_HOST_SHARED_TX_QUEUE_READ_INDEX (IPW_MEM_SRAM_HOST_SHARED_LOWER_BOUND + 0x80)#define IPW_MEM_HOST_SHARED_RX_WRITE_INDEX \ (IPW_MEM_SRAM_HOST_INTERRUPT_AREA_LOWER_BOUND + 0x20)#define IPW_MEM_HOST_SHARED_TX_QUEUE_WRITE_INDEX \ (IPW_MEM_SRAM_HOST_INTERRUPT_AREA_LOWER_BOUND)#define IPW_MEM_HOST_SHARED_ORDINALS_TABLE_1 (IPW_MEM_SRAM_HOST_SHARED_LOWER_BOUND + 0x180)#define IPW_MEM_HOST_SHARED_ORDINALS_TABLE_2 (IPW_MEM_SRAM_HOST_SHARED_LOWER_BOUND + 0x184)#define IPW2100_INTA_TX_TRANSFER (0x00000001) // Bit 0 (LSB)#define IPW2100_INTA_RX_TRANSFER (0x00000002) // Bit 1#define IPW2100_INTA_TX_COMPLETE (0x00000004) // Bit 2#define IPW2100_INTA_EVENT_INTERRUPT (0x00000008) // Bit 3#define IPW2100_INTA_STATUS_CHANGE (0x00000010) // Bit 4#define IPW2100_INTA_BEACON_PERIOD_EXPIRED (0x00000020) // Bit 5#define IPW2100_INTA_SLAVE_MODE_HOST_COMMAND_DONE (0x00010000) // Bit 16#define IPW2100_INTA_FW_INIT_DONE (0x01000000) // Bit 24#define IPW2100_INTA_FW_CALIBRATION_CALC (0x02000000) // Bit 25#define IPW2100_INTA_FATAL_ERROR (0x40000000) // Bit 30#define IPW2100_INTA_PARITY_ERROR (0x80000000) // Bit 31 (MSB)#define IPW_AUX_HOST_RESET_REG_PRINCETON_RESET (0x00000001)#define IPW_AUX_HOST_RESET_REG_FORCE_NMI (0x00000002)#define IPW_AUX_HOST_RESET_REG_PCI_HOST_CLUSTER_FATAL_NMI (0x00000004)#define IPW_AUX_HOST_RESET_REG_CORE_FATAL_NMI (0x00000008)#define IPW_AUX_HOST_RESET_REG_SW_RESET (0x00000080)#define IPW_AUX_HOST_RESET_REG_MASTER_DISABLED (0x00000100)#define IPW_AUX_HOST_RESET_REG_STOP_MASTER (0x00000200)#define IPW_AUX_HOST_GP_CNTRL_BIT_CLOCK_READY (0x00000001) // Bit 0 (LSB)#define IPW_AUX_HOST_GP_CNTRL_BIT_HOST_ALLOWS_STANDBY (0x00000002) // Bit 1#define IPW_AUX_HOST_GP_CNTRL_BIT_INIT_DONE (0x00000004) // Bit 2#define IPW_AUX_HOST_GP_CNTRL_BITS_SYS_CONFIG (0x000007c0) // Bits 6-10#define IPW_AUX_HOST_GP_CNTRL_BIT_BUS_TYPE (0x00000200) // Bit 9#define IPW_AUX_HOST_GP_CNTRL_BIT_BAR0_BLOCK_SIZE (0x00000400) // Bit 10#define IPW_AUX_HOST_GP_CNTRL_BIT_USB_MODE (0x20000000) // Bit 29#define IPW_AUX_HOST_GP_CNTRL_BIT_HOST_FORCES_SYS_CLK (0x40000000) // Bit 30#define IPW_AUX_HOST_GP_CNTRL_BIT_FW_FORCES_SYS_CLK (0x80000000) // Bit 31 (MSB)#define IPW_BIT_GPIO_GPIO1_MASK 0x0000000C#define IPW_BIT_GPIO_GPIO3_MASK 0x000000C0#define IPW_BIT_GPIO_GPIO1_ENABLE 0x00000008#define IPW_BIT_GPIO_RF_KILL 0x00010000#define IPW_BIT_GPIO_LED_OFF 0x00002000 // Bit 13 = 1#define IPW_REG_DOMAIN_0_OFFSET 0x0000#define IPW_REG_DOMAIN_1_OFFSET IPW_MEM_SRAM_HOST_SHARED_LOWER_BOUND#define IPW_REG_INTA IPW_REG_DOMAIN_0_OFFSET + 0x0008#define IPW_REG_INTA_MASK IPW_REG_DOMAIN_0_OFFSET + 0x000C#define IPW_REG_INDIRECT_ACCESS_ADDRESS IPW_REG_DOMAIN_0_OFFSET + 0x0010#define IPW_REG_INDIRECT_ACCESS_DATA IPW_REG_DOMAIN_0_OFFSET + 0x0014#define IPW_REG_AUTOINCREMENT_ADDRESS IPW_REG_DOMAIN_0_OFFSET + 0x0018#define IPW_REG_AUTOINCREMENT_DATA IPW_REG_DOMAIN_0_OFFSET + 0x001C#define IPW_REG_RESET_REG IPW_REG_DOMAIN_0_OFFSET + 0x0020#define IPW_REG_GP_CNTRL IPW_REG_DOMAIN_0_OFFSET + 0x0024#define IPW_REG_GPIO IPW_REG_DOMAIN_0_OFFSET + 0x0030#define IPW_REG_FW_TYPE IPW_REG_DOMAIN_1_OFFSET + 0x0188#define IPW_REG_FW_VERSION IPW_REG_DOMAIN_1_OFFSET + 0x018C#define IPW_REG_FW_COMPATABILITY_VERSION IPW_REG_DOMAIN_1_OFFSET + 0x0190#define IPW_REG_INDIRECT_ADDR_MASK 0x00FFFFFC#define IPW_INTERRUPT_MASK 0xC1010013#define IPW2100_CONTROL_REG 0x220000#define IPW2100_CONTROL_PHY_OFF 0x8#define IPW2100_COMMAND 0x00300004#define IPW2100_COMMAND_PHY_ON 0x0#define IPW2100_COMMAND_PHY_OFF 0x1/* in DEBUG_AREA, values of memory always 0xd55555d5 */#define IPW_REG_DOA_DEBUG_AREA_START IPW_REG_DOMAIN_0_OFFSET + 0x0090#define IPW_REG_DOA_DEBUG_AREA_END IPW_REG_DOMAIN_0_OFFSET + 0x00FF#define IPW_DATA_DOA_DEBUG_VALUE 0xd55555d5#define IPW_INTERNAL_REGISTER_HALT_AND_RESET 0x003000e0#define IPW_WAIT_CLOCK_STABILIZATION_DELAY 50 // micro seconds#define IPW_WAIT_RESET_ARC_COMPLETE_DELAY 10 // micro seconds#define IPW_WAIT_RESET_MASTER_ASSERT_COMPLETE_DELAY 10 // micro seconds// BD ring queue read/write difference⌨️ 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