smctr.h

linux-2.6.15.6

#define BID_SOFT_CONFIG_BIT     0x20
#define BID_RAM_SIZE_BIT        0x40
#define BID_BUS_TYPE_BIT        0x80

#define BID_CR          0x10

#define BID_TXP         0x04            /* Transmit Packet Command */

#define BID_TCR_DIFF    0x0D    /* Transmit Configuration Register */

#define BID_TCR_VAL     0x18            /* Value to Test 8390 or 690 */
#define BID_PS0         0x00            /* Register Page Select 0 */
#define BID_PS1         0x40            /* Register Page Select 1 */
#define BID_PS2         0x80            /* Register Page Select 2 */
#define BID_PS_MASK     0x3F            /* For Masking Off Page Select Bits */

#define BID_EEPROM_0                    0x08
#define BID_EEPROM_1                    0x09
#define BID_EEPROM_2                    0x0A
#define BID_EEPROM_3                    0x0B
#define BID_EEPROM_4                    0x0C
#define BID_EEPROM_5                    0x0D
#define BID_EEPROM_6                    0x0E
#define BID_EEPROM_7                    0x0F

#define BID_OTHER_BIT                   0x02
#define BID_ICR_MASK                    0x0C
#define BID_EAR_MASK                    0x0F
#define BID_ENGR_PAGE                   0x0A0
#define BID_RLA                         0x10
#define BID_EA6                         0x80
#define BID_RECALL_DONE_MASK            0x10
#define BID_BID_EEPROM_OVERRIDE         0xFFB0
#define BID_EXTRA_EEPROM_OVERRIDE       0xFFD0
#define BID_EEPROM_MEDIA_MASK           0x07
#define BID_STARLAN_TYPE                0x00
#define BID_ETHERNET_TYPE               0x01
#define BID_TP_TYPE                     0x02
#define BID_EW_TYPE                     0x03
#define BID_TOKEN_RING_TYPE             0x04
#define BID_UTP2_TYPE                   0x05
#define BID_EEPROM_IRQ_MASK             0x18
#define BID_PRIMARY_IRQ                 0x00
#define BID_ALTERNATE_IRQ_1             0x08
#define BID_ALTERNATE_IRQ_2             0x10
#define BID_ALTERNATE_IRQ_3             0x18
#define BID_EEPROM_RAM_SIZE_MASK        0xE0
#define BID_EEPROM_RAM_SIZE_RES1        0x00
#define BID_EEPROM_RAM_SIZE_RES2        0x20
#define BID_EEPROM_RAM_SIZE_8K          0x40
#define BID_EEPROM_RAM_SIZE_16K         0x60
#define BID_EEPROM_RAM_SIZE_32K         0x80
#define BID_EEPROM_RAM_SIZE_64K         0xA0
#define BID_EEPROM_RAM_SIZE_RES3        0xC0
#define BID_EEPROM_RAM_SIZE_RES4        0xE0
#define BID_EEPROM_BUS_TYPE_MASK        0x07
#define BID_EEPROM_BUS_TYPE_AT          0x00
#define BID_EEPROM_BUS_TYPE_MCA         0x01
#define BID_EEPROM_BUS_TYPE_EISA        0x02
#define BID_EEPROM_BUS_TYPE_NEC         0x03
#define BID_EEPROM_BUS_SIZE_MASK        0x18
#define BID_EEPROM_BUS_SIZE_8BIT        0x00
#define BID_EEPROM_BUS_SIZE_16BIT       0x08
#define BID_EEPROM_BUS_SIZE_32BIT       0x10
#define BID_EEPROM_BUS_SIZE_64BIT       0x18
#define BID_EEPROM_BUS_MASTER           0x20
#define BID_EEPROM_RAM_PAGING           0x40
#define BID_EEPROM_ROM_PAGING           0x80
#define BID_EEPROM_PAGING_MASK          0xC0
#define BID_EEPROM_LOW_COST             0x08
#define BID_EEPROM_IO_MAPPED            0x10
#define BID_EEPROM_HMI                  0x01
#define BID_EEPROM_AUTO_MEDIA_DETECT    0x01
#define BID_EEPROM_CHIP_REV_MASK        0x0C

#define BID_EEPROM_LAN_ADDR             0x30

#define BID_EEPROM_MEDIA_OPTION         0x54
#define BID_EEPROM_MEDIA_UTP            0x01
#define BID_EEPROM_4MB_RING             0x08
#define BID_EEPROM_16MB_RING            0x10
#define BID_EEPROM_MEDIA_STP            0x40

#define BID_EEPROM_MISC_DATA            0x56
#define BID_EEPROM_EARLY_TOKEN_RELEASE  0x02

#define CNFG_ID_8003E           0x6fc0
#define CNFG_ID_8003S           0x6fc1
#define CNFG_ID_8003W           0x6fc2
#define CNFG_ID_8115TRA         0x6ec6
#define CNFG_ID_8013E           0x61C8
#define CNFG_ID_8013W           0x61C9
#define CNFG_ID_BISTRO03E       0xEFE5
#define CNFG_ID_BISTRO13E       0xEFD5
#define CNFG_ID_BISTRO13W       0xEFD4
#define CNFG_MSR_583    0x0
#define CNFG_ICR_583    0x1
#define CNFG_IAR_583    0x2
#define CNFG_BIO_583    0x3
#define CNFG_EAR_583    0x3
#define CNFG_IRR_583    0x4
#define CNFG_LAAR_584   0x5
#define CNFG_GP2                0x7
#define CNFG_LAAR_MASK          0x1F
#define CNFG_LAAR_ZWS           0x20
#define CNFG_LAAR_L16E          0x40
#define CNFG_ICR_IR2_584        0x04
#define CNFG_ICR_MASK       0x08
#define CNFG_ICR_MSZ        0x08
#define CNFG_ICR_RLA        0x10
#define CNFG_ICR_STO        0x80
#define CNFG_IRR_IRQS           0x60
#define CNFG_IRR_IEN            0x80
#define CNFG_IRR_ZWS            0x01
#define CNFG_GP2_BOOT_NIBBLE    0x0F
#define CNFG_IRR_OUT2       0x04
#define CNFG_IRR_OUT1       0x02

#define CNFG_SIZE_8KB           8
#define CNFG_SIZE_16KB          16
#define CNFG_SIZE_32KB          32
#define CNFG_SIZE_64KB          64
#define CNFG_SIZE_128KB     128
#define CNFG_SIZE_256KB     256
#define ROM_DISABLE             0x0

#define CNFG_SLOT_ENABLE_BIT    0x08

#define CNFG_POS_CONTROL_REG    0x096
#define CNFG_POS_REG0           0x100
#define CNFG_POS_REG1           0x101
#define CNFG_POS_REG2           0x102
#define CNFG_POS_REG3           0x103
#define CNFG_POS_REG4           0x104
#define CNFG_POS_REG5           0x105

#define CNFG_ADAPTER_TYPE_MASK  0x0e

#define SLOT_16BIT              0x0008
#define INTERFACE_5X3_CHIP      0x0000          /* 0000 = 583 or 593 chips */
#define NIC_690_BIT                     0x0010          /* NIC is 690 */
#define ALTERNATE_IRQ_BIT       0x0020          /* Alternate IRQ is used */
#define INTERFACE_584_CHIP      0x0040          /* 0001 = 584 chip */
#define INTERFACE_594_CHIP      0x0080          /* 0010 = 594 chip */
#define INTERFACE_585_CHIP      0x0100          /* 0100 = 585/790 chip */
#define INTERFACE_CHIP_MASK     0x03C0          /* Isolates Intfc Chip Type */

#define BOARD_16BIT             0x0040
#define NODE_ADDR_CKSUM 	0xEE
#define BRD_ID_8115T    	0x04

#define NIC_825_BIT             0x0400          /* TRC 83C825 NIC */
#define NIC_790_BIT             0x0800          /* NIC is 83C790 Ethernet */

#define CHIP_REV_MASK           0x3000

#define HWR_CBUSY			0x02
#define HWR_CA				0x01

#define MAC_QUEUE                       0
#define NON_MAC_QUEUE                   1
#define BUG_QUEUE                       2       /* NO RECEIVE QUEUE, ONLY TX */

#define NUM_MAC_TX_FCBS                 8
#define NUM_MAC_TX_BDBS                 NUM_MAC_TX_FCBS
#define NUM_MAC_RX_FCBS                 7
#define NUM_MAC_RX_BDBS                 8

#define NUM_NON_MAC_TX_FCBS             6
#define NUM_NON_MAC_TX_BDBS             NUM_NON_MAC_TX_FCBS

#define NUM_NON_MAC_RX_BDBS             0       /* CALCULATED DYNAMICALLY */

#define NUM_BUG_TX_FCBS                 8
#define NUM_BUG_TX_BDBS                 NUM_BUG_TX_FCBS

#define MAC_TX_BUFFER_MEMORY            1024
#define NON_MAC_TX_BUFFER_MEMORY        (20 * 1024)
#define BUG_TX_BUFFER_MEMORY            (NUM_BUG_TX_FCBS * 32)

#define RX_BUFFER_MEMORY                0       /* CALCULATED DYNAMICALLY */
#define RX_DATA_BUFFER_SIZE             256
#define RX_BDB_SIZE_SHIFT               3       /* log2(RX_DATA_BUFFER_SIZE)-log2(sizeof(BDBlock)) */
#define RX_BDB_SIZE_MASK                (sizeof(BDBlock) - 1)
#define RX_DATA_BUFFER_SIZE_MASK        (RX_DATA_BUFFER_SIZE-1)

#define NUM_OF_INTERRUPTS               0x20

#define NOT_TRANSMITING                 0
#define TRANSMITING			1

#define TRC_INTERRUPT_ENABLE_MASK       0x7FF6

#define UCODE_VERSION                   0x58

#define UCODE_SIZE_OFFSET               0x0000  /* WORD */
#define UCODE_CHECKSUM_OFFSET           0x0002  /* WORD */
#define UCODE_VERSION_OFFSET            0x0004  /* BYTE */

#define CS_RAM_SIZE                     0X2000
#define CS_RAM_CHECKSUM_OFFSET          0x1FFE  /* WORD 1FFE(MSB)-1FFF(LSB)*/
#define CS_RAM_VERSION_OFFSET           0x1FFC  /* WORD 1FFC(MSB)-1FFD(LSB)*/

#define MISC_DATA_SIZE                  128
#define NUM_OF_ACBS                     1

#define ACB_COMMAND_NOT_DONE            0x0000  /* Init, command not done */
#define ACB_COMMAND_DONE                0x8000  /* TRC says command done */
#define ACB_COMMAND_STATUS_MASK         0x00FF  /* low byte is status */
#define ACB_COMMAND_SUCCESSFUL          0x0000  /* means cmd was successful */
#define ACB_NOT_CHAIN_END               0x0000  /* tell TRC more CBs in chain */
#define ACB_CHAIN_END                   0x8000  /* tell TRC last CB in chain */
#define ACB_COMMAND_NO_INTERRUPT        0x0000  /* tell TRC no INT after CB */
#define ACB_COMMAND_INTERRUPT           0x2000  /* tell TRC to INT after CB */
#define ACB_SUB_CMD_NOP                 0x0000
#define ACB_CMD_HIC_NOP                 0x0080
#define ACB_CMD_MCT_NOP                 0x0000
#define ACB_CMD_MCT_TEST                0x0001
#define ACB_CMD_HIC_TEST                0x0081
#define ACB_CMD_INSERT                  0x0002
#define ACB_CMD_REMOVE                  0x0003
#define ACB_CMD_MCT_WRITE_VALUE         0x0004
#define ACB_CMD_HIC_WRITE_VALUE         0x0084
#define ACB_CMD_MCT_READ_VALUE          0x0005
#define ACB_CMD_HIC_READ_VALUE          0x0085
#define ACB_CMD_INIT_TX_RX              0x0086
#define ACB_CMD_INIT_TRC_TIMERS         0x0006
#define ACB_CMD_READ_TRC_STATUS         0x0007
#define ACB_CMD_CHANGE_JOIN_STATE       0x0008
#define ACB_CMD_RESERVED_9              0x0009
#define ACB_CMD_RESERVED_A              0x000A
#define ACB_CMD_RESERVED_B              0x000B
#define ACB_CMD_RESERVED_C              0x000C
#define ACB_CMD_RESERVED_D              0x000D
#define ACB_CMD_RESERVED_E              0x000E
#define ACB_CMD_RESERVED_F              0x000F

#define TRC_MAC_REGISTERS_TEST          0x0000
#define TRC_INTERNAL_LOOPBACK           0x0001
#define TRC_TRI_LOOPBACK                0x0002
#define TRC_INTERNAL_ROM_TEST           0x0003
#define TRC_LOBE_MEDIA_TEST             0x0004
#define TRC_ANALOG_TEST                 0x0005
#define TRC_HOST_INTERFACE_REG_TEST     0x0003

#define TEST_DMA_1                      0x0000
#define TEST_DMA_2                      0x0001
#define TEST_MCT_ROM                    0x0002
#define HIC_INTERNAL_DIAG               0x0003

#define ABORT_TRANSMIT_PRIORITY_0       0x0001
#define ABORT_TRANSMIT_PRIORITY_1       0x0002
#define ABORT_TRANSMIT_PRIORITY_2       0x0004
#define ABORT_TRANSMIT_PRIORITY_3       0x0008
#define ABORT_TRANSMIT_PRIORITY_4       0x0010
#define ABORT_TRANSMIT_PRIORITY_5       0x0020
#define ABORT_TRANSMIT_PRIORITY_6       0x0040
#define ABORT_TRANSMIT_PRIORITY_7       0x0080

#define TX_PENDING_PRIORITY_0           0x0001
#define TX_PENDING_PRIORITY_1           0x0002
#define TX_PENDING_PRIORITY_2           0x0004
#define TX_PENDING_PRIORITY_3           0x0008
#define TX_PENDING_PRIORITY_4           0x0010
#define TX_PENDING_PRIORITY_5           0x0020
#define TX_PENDING_PRIORITY_6           0x0040
#define TX_PENDING_PRIORITY_7           0x0080

#define FCB_FRAME_LENGTH                0x100
#define FCB_COMMAND_DONE                0x8000  /* FCB Word 0 */
#define FCB_NOT_CHAIN_END               0x0000  /* FCB Word 1 */
#define FCB_CHAIN_END                   0x8000
#define FCB_NO_WARNING                  0x0000
#define FCB_WARNING                     0x4000
#define FCB_INTERRUPT_DISABLE           0x0000
#define FCB_INTERRUPT_ENABLE            0x2000

#define FCB_ENABLE_IMA                  0x0008
#define FCB_ENABLE_TES                  0x0004  /* Guarantee Tx before Int */
#define FCB_ENABLE_TFS                  0x0002  /* Post Tx Frame Status */
#define FCB_ENABLE_NTC                  0x0001  /* No Tx CRC */

#define FCB_TX_STATUS_CR2               0x0004
#define FCB_TX_STATUS_AR2               0x0008
#define FCB_TX_STATUS_CR1               0x0040
#define FCB_TX_STATUS_AR1               0x0080
#define FCB_TX_AC_BITS                  (FCB_TX_STATUS_AR1+FCB_TX_STATUS_AR2+FCB_TX_STATUS_CR1+FCB_TX_STATUS_CR2)
#define FCB_TX_STATUS_E                 0x0100

#define FCB_RX_STATUS_ANY_ERROR         0x0001
#define FCB_RX_STATUS_FCS_ERROR         0x0002

#define FCB_RX_STATUS_IA_MATCHED        0x0400
#define FCB_RX_STATUS_IGA_BSGA_MATCHED  0x0500
#define FCB_RX_STATUS_FA_MATCHED        0x0600
#define FCB_RX_STATUS_BA_MATCHED        0x0700
#define FCB_RX_STATUS_DA_MATCHED        0x0400
#define FCB_RX_STATUS_SOURCE_ROUTING    0x0800

#define BDB_BUFFER_SIZE                 0x100
#define BDB_NOT_CHAIN_END               0x0000
#define BDB_CHAIN_END                   0x8000
#define BDB_NO_WARNING                  0x0000
#define BDB_WARNING                     0x4000

#define ERROR_COUNTERS_CHANGED          0x0001
#define TI_NDIS_RING_STATUS_CHANGED     0x0002
#define UNA_CHANGED                     0x0004
#define READY_TO_SEND_RQ_INIT           0x0008

#define SCGB_ADDRESS_POINTER_FORMAT     INTEL_ADDRESS_POINTER_FORMAT
#define SCGB_DATA_FORMAT                INTEL_DATA_FORMAT
#define SCGB_MULTI_WORD_CONTROL         0
#define SCGB_BURST_LENGTH               0x000E  /* DMA Burst Length */

#define SCGB_CONFIG                     (INTEL_ADDRESS_POINTER_FORMAT+INTEL_DATA_FORMAT+SCGB_BURST_LENGTH)

#define ISCP_BLOCK_SIZE                 0x0A