📄 tms380tr.h
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/* * tms380tr.h: TI TMS380 Token Ring driver for Linux * * Authors: * - Christoph Goos <cgoos@syskonnect.de> * - Adam Fritzler <mid@auk.cx> */#ifndef __LINUX_TMS380TR_H#define __LINUX_TMS380TR_H#ifdef __KERNEL__#include <linux/interrupt.h>/* module prototypes */int tms380tr_open(struct net_device *dev);int tms380tr_close(struct net_device *dev);irqreturn_t tms380tr_interrupt(int irq, void *dev_id, struct pt_regs *regs);int tmsdev_init(struct net_device *dev, struct device *pdev);void tmsdev_term(struct net_device *dev);void tms380tr_wait(unsigned long time);#define TMS380TR_MAX_ADAPTERS 7#define SEND_TIMEOUT 10*HZ#define TR_RCF_LONGEST_FRAME_MASK 0x0070#define TR_RCF_FRAME4K 0x0030/*------------------------------------------------------------------*//* Bit order for adapter communication with DMA *//* -------------------------------------------------------------- *//* Bit 8 | 9| 10| 11|| 12| 13| 14| 15|| 0| 1| 2| 3|| 4| 5| 6| 7| *//* -------------------------------------------------------------- *//* The bytes in a word must be byte swapped. Also, if a double *//* word is used for storage, then the words, as well as the bytes, *//* must be swapped. *//* Bit order for adapter communication with DIO *//* -------------------------------------------------------------- *//* Bit 0 | 1| 2| 3|| 4| 5| 6| 7|| 8| 9| 10| 11|| 12| 13| 14| 15| *//* -------------------------------------------------------------- *//*------------------------------------------------------------------*//* Swap words of a long. */#define SWAPW(x) (((x) << 16) | ((x) >> 16))/* Get the low byte of a word. */#define LOBYTE(w) ((unsigned char)(w))/* Get the high byte of a word. */#define HIBYTE(w) ((unsigned char)((unsigned short)(w) >> 8))/* Get the low word of a long. */#define LOWORD(l) ((unsigned short)(l))/* Get the high word of a long. */#define HIWORD(l) ((unsigned short)((unsigned long)(l) >> 16))/* Token ring adapter I/O addresses for normal mode. *//* * The SIF registers. Common to all adapters. *//* Basic SIF (SRSX = 0) */#define SIFDAT 0x00 /* SIF/DMA data. */#define SIFINC 0x02 /* IO Word data with auto increment. */#define SIFINH 0x03 /* IO Byte data with auto increment. */#define SIFADR 0x04 /* SIF/DMA Address. */#define SIFCMD 0x06 /* SIF Command. */#define SIFSTS 0x06 /* SIF Status. *//* "Extended" SIF (SRSX = 1) */#define SIFACL 0x08 /* SIF Adapter Control Register. */#define SIFADD 0x0a /* SIF/DMA Address. -- 0x0a */#define SIFADX 0x0c /* 0x0c */#define DMALEN 0x0e /* SIF DMA length. -- 0x0e *//* * POS Registers. Only for ISA Adapters. */#define POSREG 0x10 /* Adapter Program Option Select (POS) * Register: base IO address + 16 byte. */#define POSREG_2 24L /* only for TR4/16+ adapter * base IO address + 24 byte. -- 0x18 *//* SIFCMD command codes (high-low) */#define CMD_INTERRUPT_ADAPTER 0x8000 /* Cause internal adapter interrupt */#define CMD_ADAPTER_RESET 0x4000 /* Hardware reset of adapter */#define CMD_SSB_CLEAR 0x2000 /* Acknowledge to adapter to * system interrupts. */#define CMD_EXECUTE 0x1000 /* Execute SCB command */#define CMD_SCB_REQUEST 0x0800 /* Request adapter to interrupt * system when SCB is available for * another command. */#define CMD_RX_CONTINUE 0x0400 /* Continue receive after odd pointer * stop. (odd pointer receive method) */#define CMD_RX_VALID 0x0200 /* Now actual RPL is valid. */#define CMD_TX_VALID 0x0100 /* Now actual TPL is valid. (valid * bit receive/transmit method) */#define CMD_SYSTEM_IRQ 0x0080 /* Adapter-to-attached-system * interrupt is reset. */#define CMD_CLEAR_SYSTEM_IRQ 0x0080 /* Clear SYSTEM_INTERRUPT bit. * (write: 1=ignore, 0=reset) */#define EXEC_SOFT_RESET 0xFF00 /* adapter soft reset. (restart * adapter after hardware reset) *//* ACL commands (high-low) */#define ACL_SWHLDA 0x0800 /* Software hold acknowledge. */#define ACL_SWDDIR 0x0400 /* Data transfer direction. */#define ACL_SWHRQ 0x0200 /* Pseudo DMA operation. */#define ACL_PSDMAEN 0x0100 /* Enable pseudo system DMA. */#define ACL_ARESET 0x0080 /* Adapter hardware reset command. * (held in reset condition as * long as bit is set) */#define ACL_CPHALT 0x0040 /* Communication processor halt. * (can only be set while ACL_ARESET * bit is set; prevents adapter * processor from executing code while * downloading firmware) */#define ACL_BOOT 0x0020#define ACL_SINTEN 0x0008 /* System interrupt enable/disable * (1/0): can be written if ACL_ARESET * is zero. */#define ACL_PEN 0x0004#define ACL_NSELOUT0 0x0002 #define ACL_NSELOUT1 0x0001 /* NSELOUTx have a card-specific * meaning for setting ring speed. */#define PS_DMA_MASK (ACL_SWHRQ | ACL_PSDMAEN)/* SIFSTS register return codes (high-low) */#define STS_SYSTEM_IRQ 0x0080 /* Adapter-to-attached-system * interrupt is valid. */#define STS_INITIALIZE 0x0040 /* INITIALIZE status. (ready to * initialize) */#define STS_TEST 0x0020 /* TEST status. (BUD not completed) */#define STS_ERROR 0x0010 /* ERROR status. (unrecoverable * HW error occurred) */#define STS_MASK 0x00F0 /* Mask interesting status bits. */#define STS_ERROR_MASK 0x000F /* Get Error Code by masking the * interrupt code bits. */#define ADAPTER_INT_PTRS 0x0A00 /* Address offset of adapter internal * pointers 01:0a00 (high-low) have to * be read after init and before open. *//* Interrupt Codes (only MAC IRQs) */#define STS_IRQ_ADAPTER_CHECK 0x0000 /* unrecoverable hardware or * software error. */ #define STS_IRQ_RING_STATUS 0x0004 /* SSB is updated with ring status. */#define STS_IRQ_LLC_STATUS 0x0005 /* Not used in MAC-only microcode */#define STS_IRQ_SCB_CLEAR 0x0006 /* SCB clear, following an * SCB_REQUEST IRQ. */#define STS_IRQ_TIMER 0x0007 /* Not normally used in MAC ucode */#define STS_IRQ_COMMAND_STATUS 0x0008 /* SSB is updated with command * status. */ #define STS_IRQ_RECEIVE_STATUS 0x000A /* SSB is updated with receive * status. */#define STS_IRQ_TRANSMIT_STATUS 0x000C /* SSB is updated with transmit * status */#define STS_IRQ_RECEIVE_PENDING 0x000E /* Not used in MAC-only microcode */#define STS_IRQ_MASK 0x000F /* = STS_ERROR_MASK. *//* TRANSMIT_STATUS completion code: (SSB.Parm[0]) */#define COMMAND_COMPLETE 0x0080 /* TRANSMIT command completed * (avoid this!) issue another transmit * to send additional frames. */#define FRAME_COMPLETE 0x0040 /* Frame has been transmitted; * INTERRUPT_FRAME bit was set in the * CSTAT request; indication of possibly * more than one frame transmissions! * SSB.Parm[0-1]: 32 bit pointer to * TPL of last frame. */#define LIST_ERROR 0x0020 /* Error in one of the TPLs that * compose the frame; TRANSMIT * terminated; Parm[1-2]: 32bit pointer * to TPL which starts the error * frame; error details in bits 8-13. * (14?) */#define FRAME_SIZE_ERROR 0x8000 /* FRAME_SIZE does not equal the sum of * the valid DATA_COUNT fields; * FRAME_SIZE less than header plus * information field. (15 bytes + * routing field) Or if FRAME_SIZE * was specified as zero in one list. */#define TX_THRESHOLD 0x4000 /* FRAME_SIZE greater than (BUFFER_SIZE * - 9) * TX_BUF_MAX. */#define ODD_ADDRESS 0x2000 /* Odd forward pointer value is * read on a list without END_FRAME * indication. */#define FRAME_ERROR 0x1000 /* START_FRAME bit (not) anticipated, * but (not) set. */#define ACCESS_PRIORITY_ERROR 0x0800 /* Access priority requested has not * been allowed. */#define UNENABLED_MAC_FRAME 0x0400 /* MAC frame has source class of zero * or MAC frame PCF ATTN field is * greater than one. */#define ILLEGAL_FRAME_FORMAT 0x0200 /* Bit 0 or FC field was set to one. *//* * Since we need to support some functions even if the adapter is in a * CLOSED state, we have a (pseudo-) command queue which holds commands * that are outstandig to be executed. * * Each time a command completes, an interrupt occurs and the next * command is executed. The command queue is actually a simple word with * a bit for each outstandig command. Therefore the commands will not be * executed in the order they have been queued. * * The following defines the command code bits and the command queue: */#define OC_OPEN 0x0001 /* OPEN command */#define OC_TRANSMIT 0x0002 /* TRANSMIT command */#define OC_TRANSMIT_HALT 0x0004 /* TRANSMIT_HALT command */#define OC_RECEIVE 0x0008 /* RECEIVE command */#define OC_CLOSE 0x0010 /* CLOSE command */#define OC_SET_GROUP_ADDR 0x0020 /* SET_GROUP_ADDR command */#define OC_SET_FUNCT_ADDR 0x0040 /* SET_FUNCT_ADDR command */#define OC_READ_ERROR_LOG 0x0080 /* READ_ERROR_LOG command */#define OC_READ_ADAPTER 0x0100 /* READ_ADAPTER command */#define OC_MODIFY_OPEN_PARMS 0x0400 /* MODIFY_OPEN_PARMS command */#define OC_RESTORE_OPEN_PARMS 0x0800 /* RESTORE_OPEN_PARMS command */#define OC_SET_FIRST_16_GROUP 0x1000 /* SET_FIRST_16_GROUP command */#define OC_SET_BRIDGE_PARMS 0x2000 /* SET_BRIDGE_PARMS command */#define OC_CONFIG_BRIDGE_PARMS 0x4000 /* CONFIG_BRIDGE_PARMS command */#define OPEN 0x0300 /* C: open command. S: completion. */#define TRANSMIT 0x0400 /* C: transmit command. S: completion * status. (reject: COMMAND_REJECT if * adapter not opened, TRANSMIT already * issued or address passed in the SCB * not word aligned) */#define TRANSMIT_HALT 0x0500 /* C: interrupt TX TPL chain; if no * TRANSMIT command issued, the command * is ignored (completion with TRANSMIT * status (0x0400)!) */#define RECEIVE 0x0600 /* C: receive command. S: completion * status. (reject: COMMAND_REJECT if * adapter not opened, RECEIVE already * issued or address passed in the SCB * not word aligned) */#define CLOSE 0x0700 /* C: close adapter. S: completion. * (COMMAND_REJECT if adapter not open) */#define SET_GROUP_ADDR 0x0800 /* C: alter adapter group address after * OPEN. S: completion. (COMMAND_REJECT * if adapter not open) */#define SET_FUNCT_ADDR 0x0900 /* C: alter adapter functional address * after OPEN. S: completion. * (COMMAND_REJECT if adapter not open) */#define READ_ERROR_LOG 0x0A00 /* C: read adapter error counters. * S: completion. (command ignored * if adapter not open!) */#define READ_ADAPTER 0x0B00 /* C: read data from adapter memory. * (important: after init and before * open!) S: completion. (ADAPTER_CHECK * interrupt if undefined storage area * read) */#define MODIFY_OPEN_PARMS 0x0D00 /* C: modify some adapter operational * parameters. (bit correspondend to * WRAP_INTERFACE is ignored) * S: completion. (reject: * COMMAND_REJECT) */#define RESTORE_OPEN_PARMS 0x0E00 /* C: modify some adapter operational * parameters. (bit correspondend * to WRAP_INTERFACE is ignored) * S: completion. (reject: * COMMAND_REJECT) */#define SET_FIRST_16_GROUP 0x0F00 /* C: alter the first two bytes in * adapter group address. * S: completion. (reject: * COMMAND_REJECT) */#define SET_BRIDGE_PARMS 0x1000 /* C: values and conditions for the * adapter hardware to use when frames * are copied for forwarding. * S: completion. (reject: * COMMAND_REJECT) */#define CONFIG_BRIDGE_PARMS 0x1100 /* C: .. * S: completion. (reject: * COMMAND_REJECT) */#define SPEED_4 4#define SPEED_16 16 /* Default transmission speed *//* Initialization Parameter Block (IPB); word alignment necessary! */#define BURST_SIZE 0x0018 /* Default burst size */#define BURST_MODE 0x9F00 /* Burst mode enable */#define DMA_RETRIES 0x0505 /* Magic DMA retry number... */#define CYCLE_TIME 3 /* Default AT-bus cycle time: 500 ns * (later adapter version: fix cycle time!) */#define LINE_SPEED_BIT 0x80/* Macro definition for the wait function. */#define ONE_SECOND_TICKS 1000000#define HALF_SECOND (ONE_SECOND_TICKS / 2)#define ONE_SECOND (ONE_SECOND_TICKS)#define TWO_SECONDS (ONE_SECOND_TICKS * 2)#define THREE_SECONDS (ONE_SECOND_TICKS * 3)#define FOUR_SECONDS (ONE_SECOND_TICKS * 4)#define FIVE_SECONDS (ONE_SECOND_TICKS * 5)#define BUFFER_SIZE 2048 /* Buffers on Adapter */#pragma pack(1)typedef struct { unsigned short Init_Options; /* Initialize with burst mode; * LLC disabled. (MAC only) */ /* Interrupt vectors the adapter places on attached system bus. */ u_int8_t CMD_Status_IV; /* Interrupt vector: command status. */ u_int8_t TX_IV; /* Interrupt vector: transmit. */ u_int8_t RX_IV; /* Interrupt vector: receive. */ u_int8_t Ring_Status_IV; /* Interrupt vector: ring status. */ u_int8_t SCB_Clear_IV; /* Interrupt vector: SCB clear. */ u_int8_t Adapter_CHK_IV; /* Interrupt vector: adapter check. */ u_int16_t RX_Burst_Size; /* Max. number of transfer cycles. */ u_int16_t TX_Burst_Size; /* During DMA burst; even value! */ u_int16_t DMA_Abort_Thrhld; /* Number of DMA retries. */ u_int32_t SCB_Addr; /* SCB address: even, word aligned, high-low */ u_int32_t SSB_Addr; /* SSB address: even, word aligned, high-low */} IPB, *IPB_Ptr;#pragma pack()
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