📄 qla_dbg.c
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qla_uprintf(&uiter, "\nHost Interface Registers"); for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) { if (cnt % 8 == 0) qla_uprintf(&uiter, "\n"); qla_uprintf(&uiter, "%08x ", fw->host_reg[cnt]); } qla_uprintf(&uiter, "\n\nMailbox Registers"); for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) { if (cnt % 8 == 0) qla_uprintf(&uiter, "\n"); qla_uprintf(&uiter, "%08x ", fw->mailbox_reg[cnt]); } qla_uprintf(&uiter, "\n\nXSEQ GP Registers"); for (cnt = 0; cnt < sizeof(fw->xseq_gp_reg) / 4; cnt++) { if (cnt % 8 == 0) qla_uprintf(&uiter, "\n"); qla_uprintf(&uiter, "%08x ", fw->xseq_gp_reg[cnt]); } qla_uprintf(&uiter, "\n\nXSEQ-0 Registers"); for (cnt = 0; cnt < sizeof(fw->xseq_0_reg) / 4; cnt++) { if (cnt % 8 == 0) qla_uprintf(&uiter, "\n"); qla_uprintf(&uiter, "%08x ", fw->xseq_0_reg[cnt]); } qla_uprintf(&uiter, "\n\nXSEQ-1 Registers"); for (cnt = 0; cnt < sizeof(fw->xseq_1_reg) / 4; cnt++) { if (cnt % 8 == 0) qla_uprintf(&uiter, "\n"); qla_uprintf(&uiter, "%08x ", fw->xseq_1_reg[cnt]); } qla_uprintf(&uiter, "\n\nRSEQ GP Registers"); for (cnt = 0; cnt < sizeof(fw->rseq_gp_reg) / 4; cnt++) { if (cnt % 8 == 0) qla_uprintf(&uiter, "\n"); qla_uprintf(&uiter, "%08x ", fw->rseq_gp_reg[cnt]); } qla_uprintf(&uiter, "\n\nRSEQ-0 Registers"); for (cnt = 0; cnt < sizeof(fw->rseq_0_reg) / 4; cnt++) { if (cnt % 8 == 0) qla_uprintf(&uiter, "\n"); qla_uprintf(&uiter, "%08x ", fw->rseq_0_reg[cnt]); } qla_uprintf(&uiter, "\n\nRSEQ-1 Registers"); for (cnt = 0; cnt < sizeof(fw->rseq_1_reg) / 4; cnt++) { if (cnt % 8 == 0) qla_uprintf(&uiter, "\n"); qla_uprintf(&uiter, "%08x ", fw->rseq_1_reg[cnt]); } qla_uprintf(&uiter, "\n\nRSEQ-2 Registers"); for (cnt = 0; cnt < sizeof(fw->rseq_2_reg) / 4; cnt++) { if (cnt % 8 == 0) qla_uprintf(&uiter, "\n"); qla_uprintf(&uiter, "%08x ", fw->rseq_2_reg[cnt]); } qla_uprintf(&uiter, "\n\nCommand DMA Registers"); for (cnt = 0; cnt < sizeof(fw->cmd_dma_reg) / 4; cnt++) { if (cnt % 8 == 0) qla_uprintf(&uiter, "\n"); qla_uprintf(&uiter, "%08x ", fw->cmd_dma_reg[cnt]); } qla_uprintf(&uiter, "\n\nRequest0 Queue DMA Channel Registers"); for (cnt = 0; cnt < sizeof(fw->req0_dma_reg) / 4; cnt++) { if (cnt % 8 == 0) qla_uprintf(&uiter, "\n"); qla_uprintf(&uiter, "%08x ", fw->req0_dma_reg[cnt]); } qla_uprintf(&uiter, "\n\nResponse0 Queue DMA Channel Registers"); for (cnt = 0; cnt < sizeof(fw->resp0_dma_reg) / 4; cnt++) { if (cnt % 8 == 0) qla_uprintf(&uiter, "\n"); qla_uprintf(&uiter, "%08x ", fw->resp0_dma_reg[cnt]); } qla_uprintf(&uiter, "\n\nRequest1 Queue DMA Channel Registers"); for (cnt = 0; cnt < sizeof(fw->req1_dma_reg) / 4; cnt++) { if (cnt % 8 == 0) qla_uprintf(&uiter, "\n"); qla_uprintf(&uiter, "%08x ", fw->req1_dma_reg[cnt]); } qla_uprintf(&uiter, "\n\nXMT0 Data DMA Registers"); for (cnt = 0; cnt < sizeof(fw->xmt0_dma_reg) / 4; cnt++) { if (cnt % 8 == 0) qla_uprintf(&uiter, "\n"); qla_uprintf(&uiter, "%08x ", fw->xmt0_dma_reg[cnt]); } qla_uprintf(&uiter, "\n\nXMT1 Data DMA Registers"); for (cnt = 0; cnt < sizeof(fw->xmt1_dma_reg) / 4; cnt++) { if (cnt % 8 == 0) qla_uprintf(&uiter, "\n"); qla_uprintf(&uiter, "%08x ", fw->xmt1_dma_reg[cnt]); } qla_uprintf(&uiter, "\n\nXMT2 Data DMA Registers"); for (cnt = 0; cnt < sizeof(fw->xmt2_dma_reg) / 4; cnt++) { if (cnt % 8 == 0) qla_uprintf(&uiter, "\n"); qla_uprintf(&uiter, "%08x ", fw->xmt2_dma_reg[cnt]); } qla_uprintf(&uiter, "\n\nXMT3 Data DMA Registers"); for (cnt = 0; cnt < sizeof(fw->xmt3_dma_reg) / 4; cnt++) { if (cnt % 8 == 0) qla_uprintf(&uiter, "\n"); qla_uprintf(&uiter, "%08x ", fw->xmt3_dma_reg[cnt]); } qla_uprintf(&uiter, "\n\nXMT4 Data DMA Registers"); for (cnt = 0; cnt < sizeof(fw->xmt4_dma_reg) / 4; cnt++) { if (cnt % 8 == 0) qla_uprintf(&uiter, "\n"); qla_uprintf(&uiter, "%08x ", fw->xmt4_dma_reg[cnt]); } qla_uprintf(&uiter, "\n\nXMT Data DMA Common Registers"); for (cnt = 0; cnt < sizeof(fw->xmt_data_dma_reg) / 4; cnt++) { if (cnt % 8 == 0) qla_uprintf(&uiter, "\n"); qla_uprintf(&uiter, "%08x ", fw->xmt_data_dma_reg[cnt]); } qla_uprintf(&uiter, "\n\nRCV Thread 0 Data DMA Registers"); for (cnt = 0; cnt < sizeof(fw->rcvt0_data_dma_reg) / 4; cnt++) { if (cnt % 8 == 0) qla_uprintf(&uiter, "\n"); qla_uprintf(&uiter, "%08x ", fw->rcvt0_data_dma_reg[cnt]); } qla_uprintf(&uiter, "\n\nRCV Thread 1 Data DMA Registers"); for (cnt = 0; cnt < sizeof(fw->rcvt1_data_dma_reg) / 4; cnt++) { if (cnt % 8 == 0) qla_uprintf(&uiter, "\n"); qla_uprintf(&uiter, "%08x ", fw->rcvt1_data_dma_reg[cnt]); } qla_uprintf(&uiter, "\n\nRISC GP Registers"); for (cnt = 0; cnt < sizeof(fw->risc_gp_reg) / 4; cnt++) { if (cnt % 8 == 0) qla_uprintf(&uiter, "\n"); qla_uprintf(&uiter, "%08x ", fw->risc_gp_reg[cnt]); } qla_uprintf(&uiter, "\n\nShadow Registers"); for (cnt = 0; cnt < sizeof(fw->shadow_reg) / 4; cnt++) { if (cnt % 8 == 0) qla_uprintf(&uiter, "\n"); qla_uprintf(&uiter, "%08x ", fw->shadow_reg[cnt]); } qla_uprintf(&uiter, "\n\nLMC Registers"); for (cnt = 0; cnt < sizeof(fw->lmc_reg) / 4; cnt++) { if (cnt % 8 == 0) qla_uprintf(&uiter, "\n"); qla_uprintf(&uiter, "%08x ", fw->lmc_reg[cnt]); } qla_uprintf(&uiter, "\n\nFPM Hardware Registers"); for (cnt = 0; cnt < sizeof(fw->fpm_hdw_reg) / 4; cnt++) { if (cnt % 8 == 0) qla_uprintf(&uiter, "\n"); qla_uprintf(&uiter, "%08x ", fw->fpm_hdw_reg[cnt]); } qla_uprintf(&uiter, "\n\nFB Hardware Registers"); for (cnt = 0; cnt < sizeof(fw->fb_hdw_reg) / 4; cnt++) { if (cnt % 8 == 0) qla_uprintf(&uiter, "\n"); qla_uprintf(&uiter, "%08x ", fw->fb_hdw_reg[cnt]); } qla_uprintf(&uiter, "\n\nCode RAM"); for (cnt = 0; cnt < sizeof (fw->code_ram) / 4; cnt++) { if (cnt % 8 == 0) { qla_uprintf(&uiter, "\n%08x: ", cnt + 0x20000); } qla_uprintf(&uiter, "%08x ", fw->code_ram[cnt]); } qla_uprintf(&uiter, "\n\nExternal Memory"); ext_mem_cnt = ha->fw_memory_size - 0x100000 + 1; for (cnt = 0; cnt < ext_mem_cnt; cnt++) { if (cnt % 8 == 0) { qla_uprintf(&uiter, "\n%08x: ", cnt + 0x100000); } qla_uprintf(&uiter, "%08x ", fw->ext_mem[cnt]); } qla_uprintf(&uiter, "\n[<==END] ISP Debug Dump");}/****************************************************************************//* Driver Debug Functions. *//****************************************************************************/voidqla2x00_dump_regs(scsi_qla_host_t *ha){ struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; printk("Mailbox registers:\n"); printk("scsi(%ld): mbox 0 0x%04x \n", ha->host_no, RD_MAILBOX_REG(ha, reg, 0)); printk("scsi(%ld): mbox 1 0x%04x \n", ha->host_no, RD_MAILBOX_REG(ha, reg, 1)); printk("scsi(%ld): mbox 2 0x%04x \n", ha->host_no, RD_MAILBOX_REG(ha, reg, 2)); printk("scsi(%ld): mbox 3 0x%04x \n", ha->host_no, RD_MAILBOX_REG(ha, reg, 3)); printk("scsi(%ld): mbox 4 0x%04x \n", ha->host_no, RD_MAILBOX_REG(ha, reg, 4)); printk("scsi(%ld): mbox 5 0x%04x \n", ha->host_no, RD_MAILBOX_REG(ha, reg, 5));}voidqla2x00_dump_buffer(uint8_t * b, uint32_t size){ uint32_t cnt; uint8_t c; printk(" 0 1 2 3 4 5 6 7 8 9 " "Ah Bh Ch Dh Eh Fh\n"); printk("----------------------------------------" "----------------------\n"); for (cnt = 0; cnt < size;) { c = *b++; printk("%02x",(uint32_t) c); cnt++; if (!(cnt % 16)) printk("\n"); else printk(" "); } if (cnt % 16) printk("\n");}/************************************************************************** * qla2x00_print_scsi_cmd * Dumps out info about the scsi cmd and srb. * Input * cmd : struct scsi_cmnd **************************************************************************/voidqla2x00_print_scsi_cmd(struct scsi_cmnd * cmd){ int i; struct scsi_qla_host *ha; srb_t *sp; ha = (struct scsi_qla_host *)cmd->device->host->hostdata; sp = (srb_t *) cmd->SCp.ptr; printk("SCSI Command @=0x%p, Handle=0x%p\n", cmd, cmd->host_scribble); printk(" chan=0x%02x, target=0x%02x, lun=0x%02x, cmd_len=0x%02x\n", cmd->device->channel, cmd->device->id, cmd->device->lun, cmd->cmd_len); printk(" CDB: "); for (i = 0; i < cmd->cmd_len; i++) { printk("0x%02x ", cmd->cmnd[i]); } printk("\n seg_cnt=%d, allowed=%d, retries=%d\n", cmd->use_sg, cmd->allowed, cmd->retries); printk(" request buffer=0x%p, request buffer len=0x%x\n", cmd->request_buffer, cmd->request_bufflen); printk(" tag=%d, transfersize=0x%x\n", cmd->tag, cmd->transfersize); printk(" serial_number=%lx, SP=%p\n", cmd->serial_number, sp); printk(" data direction=%d\n", cmd->sc_data_direction); if (!sp) return; printk(" sp flags=0x%x\n", sp->flags); printk(" state=%d\n", sp->state);}voidqla2x00_dump_pkt(void *pkt){ uint32_t i; uint8_t *data = (uint8_t *) pkt; for (i = 0; i < 64; i++) { if (!(i % 4)) printk("\n%02x: ", i); printk("%02x ", data[i]); } printk("\n");}#if defined(QL_DEBUG_ROUTINES)/* * qla2x00_formatted_dump_buffer * Prints string plus buffer. * * Input: * string = Null terminated string (no newline at end). * buffer = buffer address. * wd_size = word size 8, 16, 32 or 64 bits * count = number of words. */voidqla2x00_formatted_dump_buffer(char *string, uint8_t * buffer, uint8_t wd_size, uint32_t count){ uint32_t cnt; uint16_t *buf16; uint32_t *buf32; if (strcmp(string, "") != 0) printk("%s\n",string); switch (wd_size) { case 8: printk(" 0 1 2 3 4 5 6 7 " "8 9 Ah Bh Ch Dh Eh Fh\n"); printk("-----------------------------------------" "-------------------------------------\n"); for (cnt = 1; cnt <= count; cnt++, buffer++) { printk("%02x",*buffer); if (cnt % 16 == 0) printk("\n"); else printk(" "); } if (cnt % 16 != 0) printk("\n"); break; case 16: printk(" 0 2 4 6 8 Ah " " Ch Eh\n"); printk("-----------------------------------------" "-------------\n"); buf16 = (uint16_t *) buffer; for (cnt = 1; cnt <= count; cnt++, buf16++) { printk("%4x",*buf16); if (cnt % 8 == 0) printk("\n"); else if (*buf16 < 10) printk(" "); else printk(" "); } if (cnt % 8 != 0) printk("\n"); break; case 32: printk(" 0 4 8 Ch\n"); printk("------------------------------------------\n"); buf32 = (uint32_t *) buffer; for (cnt = 1; cnt <= count; cnt++, buf32++) { printk("%8x", *buf32); if (cnt % 4 == 0) printk("\n"); else if (*buf32 < 10) printk(" "); else printk(" "); } if (cnt % 4 != 0) printk("\n"); break; default: break; }}#endif
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