qla_dbg.c

linux-2.6.15.6

	for (cnt = 0; cnt < sizeof (fw->risc_hdw_reg) / 2; cnt++) {
		if (cnt % 8 == 0) {
			qla_uprintf(&uiter, "\n");
		}
		qla_uprintf(&uiter, "%04x ", fw->risc_hdw_reg[cnt]);
	}

	qla_uprintf(&uiter, "\n\nRISC GP0 Registers:");
	for (cnt = 0; cnt < sizeof (fw->risc_gp0_reg) / 2; cnt++) {
		if (cnt % 8 == 0) {
			qla_uprintf(&uiter, "\n");
		}
		qla_uprintf(&uiter, "%04x ", fw->risc_gp0_reg[cnt]);
	}

	qla_uprintf(&uiter, "\n\nRISC GP1 Registers:");
	for (cnt = 0; cnt < sizeof (fw->risc_gp1_reg) / 2; cnt++) {
		if (cnt % 8 == 0) {
			qla_uprintf(&uiter, "\n");
		}
		qla_uprintf(&uiter, "%04x ", fw->risc_gp1_reg[cnt]);
	}

	qla_uprintf(&uiter, "\n\nRISC GP2 Registers:");
	for (cnt = 0; cnt < sizeof (fw->risc_gp2_reg) / 2; cnt++) {
		if (cnt % 8 == 0) {
			qla_uprintf(&uiter, "\n");
		}
		qla_uprintf(&uiter, "%04x ", fw->risc_gp2_reg[cnt]);
	}

	qla_uprintf(&uiter, "\n\nRISC GP3 Registers:");
	for (cnt = 0; cnt < sizeof (fw->risc_gp3_reg) / 2; cnt++) {
		if (cnt % 8 == 0) {
			qla_uprintf(&uiter, "\n");
		}
		qla_uprintf(&uiter, "%04x ", fw->risc_gp3_reg[cnt]);
	}

	qla_uprintf(&uiter, "\n\nRISC GP4 Registers:");
	for (cnt = 0; cnt < sizeof (fw->risc_gp4_reg) / 2; cnt++) {
		if (cnt % 8 == 0) {
			qla_uprintf(&uiter, "\n");
		}
		qla_uprintf(&uiter, "%04x ", fw->risc_gp4_reg[cnt]);
	}

	qla_uprintf(&uiter, "\n\nRISC GP5 Registers:");
	for (cnt = 0; cnt < sizeof (fw->risc_gp5_reg) / 2; cnt++) {
		if (cnt % 8 == 0) {
			qla_uprintf(&uiter, "\n");
		}
		qla_uprintf(&uiter, "%04x ", fw->risc_gp5_reg[cnt]);
	}

	qla_uprintf(&uiter, "\n\nRISC GP6 Registers:");
	for (cnt = 0; cnt < sizeof (fw->risc_gp6_reg) / 2; cnt++) {
		if (cnt % 8 == 0) {
			qla_uprintf(&uiter, "\n");
		}
		qla_uprintf(&uiter, "%04x ", fw->risc_gp6_reg[cnt]);
	}

	qla_uprintf(&uiter, "\n\nRISC GP7 Registers:");
	for (cnt = 0; cnt < sizeof (fw->risc_gp7_reg) / 2; cnt++) {
		if (cnt % 8 == 0) {
			qla_uprintf(&uiter, "\n");
		}
		qla_uprintf(&uiter, "%04x ", fw->risc_gp7_reg[cnt]);
	}

	qla_uprintf(&uiter, "\n\nFrame Buffer Hardware Registers:");
	for (cnt = 0; cnt < sizeof (fw->frame_buf_hdw_reg) / 2; cnt++) {
		if (cnt % 8 == 0) {
			qla_uprintf(&uiter, "\n");
		}
		qla_uprintf(&uiter, "%04x ", fw->frame_buf_hdw_reg[cnt]);
	}

	qla_uprintf(&uiter, "\n\nFPM B0 Registers:");
	for (cnt = 0; cnt < sizeof (fw->fpm_b0_reg) / 2; cnt++) {
		if (cnt % 8 == 0) {
			qla_uprintf(&uiter, "\n");
		}
		qla_uprintf(&uiter, "%04x ", fw->fpm_b0_reg[cnt]);
	}

	qla_uprintf(&uiter, "\n\nFPM B1 Registers:");
	for (cnt = 0; cnt < sizeof (fw->fpm_b1_reg) / 2; cnt++) {
		if (cnt % 8 == 0) {
			qla_uprintf(&uiter, "\n");
		}
		qla_uprintf(&uiter, "%04x ", fw->fpm_b1_reg[cnt]);
	}

	qla_uprintf(&uiter, "\n\nRISC SRAM:");
	for (cnt = 0; cnt < sizeof (fw->risc_ram) / 2; cnt++) {
		if (cnt % 8 == 0) {
			qla_uprintf(&uiter, "\n%04x: ", cnt + 0x1000);
		}
		qla_uprintf(&uiter, "%04x ", fw->risc_ram[cnt]);
	}

	qla_uprintf(&uiter, "\n\n[<==END] ISP Debug Dump.");

	return;
}

static int
qla_uprintf(char **uiter, char *fmt, ...)
{
	int	iter, len;
	char	buf[128];
	va_list	args;

	va_start(args, fmt);
	len = vsprintf(buf, fmt, args);
	va_end(args);

	for (iter = 0; iter < len; iter++, *uiter += 1)
		*uiter[0] = buf[iter];

	return (len);
}


void
qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
{
	int		rval;
	uint32_t	cnt, timer;
	uint32_t	risc_address;
	uint16_t	mb[4], wd;

	uint32_t	stat;
	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
	uint32_t __iomem *dmp_reg;
	uint32_t	*iter_reg;
	uint16_t __iomem *mbx_reg;
	unsigned long	flags;
	struct qla24xx_fw_dump *fw;
	uint32_t	ext_mem_cnt;

	risc_address = ext_mem_cnt = 0;
	memset(mb, 0, sizeof(mb));
	flags = 0;

	if (!hardware_locked)
		spin_lock_irqsave(&ha->hardware_lock, flags);

	if (!ha->fw_dump24) {
		qla_printk(KERN_WARNING, ha,
		    "No buffer available for dump!!!\n");
		goto qla24xx_fw_dump_failed;
	}

	if (ha->fw_dumped) {
		qla_printk(KERN_WARNING, ha,
		    "Firmware has been previously dumped (%p) -- ignoring "
		    "request...\n", ha->fw_dump24);
		goto qla24xx_fw_dump_failed;
	}
	fw = (struct qla24xx_fw_dump *) ha->fw_dump24;

	rval = QLA_SUCCESS;
	fw->hccr = RD_REG_DWORD(&reg->hccr);

	/* Pause RISC. */
	if ((fw->hccr & HCCRX_RISC_PAUSE) == 0) {
		WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET |
		    HCCRX_CLR_HOST_INT);
		RD_REG_DWORD(&reg->hccr);		/* PCI Posting. */
		WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_PAUSE);
		for (cnt = 30000;
		    (RD_REG_DWORD(&reg->hccr) & HCCRX_RISC_PAUSE) == 0 &&
		    rval == QLA_SUCCESS; cnt--) {
			if (cnt)
				udelay(100);
			else
				rval = QLA_FUNCTION_TIMEOUT;
		}
	}

	/* Disable interrupts. */
	WRT_REG_DWORD(&reg->ictrl, 0);
	RD_REG_DWORD(&reg->ictrl);

	if (rval == QLA_SUCCESS) {
		/* Host interface registers. */
		dmp_reg = (uint32_t __iomem *)(reg + 0);
		for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
			fw->host_reg[cnt] = RD_REG_DWORD(dmp_reg++);

		/* Mailbox registers. */
		mbx_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
		for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
			fw->mailbox_reg[cnt] = RD_REG_WORD(mbx_reg++);

		/* Transfer sequence registers. */
		iter_reg = fw->xseq_gp_reg;
		WRT_REG_DWORD(&reg->iobase_addr, 0xBF00);
		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
		for (cnt = 0; cnt < 16; cnt++)
			*iter_reg++ = RD_REG_DWORD(dmp_reg++);

		WRT_REG_DWORD(&reg->iobase_addr, 0xBF10);
		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
		for (cnt = 0; cnt < 16; cnt++)
			*iter_reg++ = RD_REG_DWORD(dmp_reg++);

		WRT_REG_DWORD(&reg->iobase_addr, 0xBF20);
		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
		for (cnt = 0; cnt < 16; cnt++)
			*iter_reg++ = RD_REG_DWORD(dmp_reg++);

		WRT_REG_DWORD(&reg->iobase_addr, 0xBF30);
		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
		for (cnt = 0; cnt < 16; cnt++)
			*iter_reg++ = RD_REG_DWORD(dmp_reg++);

		WRT_REG_DWORD(&reg->iobase_addr, 0xBF40);
		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
		for (cnt = 0; cnt < 16; cnt++)
			*iter_reg++ = RD_REG_DWORD(dmp_reg++);

		WRT_REG_DWORD(&reg->iobase_addr, 0xBF50);
		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
		for (cnt = 0; cnt < 16; cnt++)
			*iter_reg++ = RD_REG_DWORD(dmp_reg++);

		WRT_REG_DWORD(&reg->iobase_addr, 0xBF60);
		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
		for (cnt = 0; cnt < 16; cnt++)
			*iter_reg++ = RD_REG_DWORD(dmp_reg++);

		WRT_REG_DWORD(&reg->iobase_addr, 0xBF70);
		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
		for (cnt = 0; cnt < 16; cnt++)
			*iter_reg++ = RD_REG_DWORD(dmp_reg++);

		WRT_REG_DWORD(&reg->iobase_addr, 0xBFE0);
		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
		for (cnt = 0; cnt < sizeof(fw->xseq_0_reg) / 4; cnt++)
			fw->xseq_0_reg[cnt] = RD_REG_DWORD(dmp_reg++);

		WRT_REG_DWORD(&reg->iobase_addr, 0xBFF0);
		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
		for (cnt = 0; cnt < sizeof(fw->xseq_1_reg) / 4; cnt++)
			fw->xseq_1_reg[cnt] = RD_REG_DWORD(dmp_reg++);

		/* Receive sequence registers. */
		iter_reg = fw->rseq_gp_reg;
		WRT_REG_DWORD(&reg->iobase_addr, 0xFF00);
		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
		for (cnt = 0; cnt < 16; cnt++)
			*iter_reg++ = RD_REG_DWORD(dmp_reg++);

		WRT_REG_DWORD(&reg->iobase_addr, 0xFF10);
		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
		for (cnt = 0; cnt < 16; cnt++)
			*iter_reg++ = RD_REG_DWORD(dmp_reg++);

		WRT_REG_DWORD(&reg->iobase_addr, 0xFF20);
		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
		for (cnt = 0; cnt < 16; cnt++)
			*iter_reg++ = RD_REG_DWORD(dmp_reg++);

		WRT_REG_DWORD(&reg->iobase_addr, 0xFF30);
		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
		for (cnt = 0; cnt < 16; cnt++)
			*iter_reg++ = RD_REG_DWORD(dmp_reg++);

		WRT_REG_DWORD(&reg->iobase_addr, 0xFF40);
		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
		for (cnt = 0; cnt < 16; cnt++)
			*iter_reg++ = RD_REG_DWORD(dmp_reg++);

		WRT_REG_DWORD(&reg->iobase_addr, 0xFF50);
		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
		for (cnt = 0; cnt < 16; cnt++)
			*iter_reg++ = RD_REG_DWORD(dmp_reg++);

		WRT_REG_DWORD(&reg->iobase_addr, 0xFF60);
		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
		for (cnt = 0; cnt < 16; cnt++)
			*iter_reg++ = RD_REG_DWORD(dmp_reg++);

		WRT_REG_DWORD(&reg->iobase_addr, 0xFF70);
		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
		for (cnt = 0; cnt < 16; cnt++)
			*iter_reg++ = RD_REG_DWORD(dmp_reg++);

		WRT_REG_DWORD(&reg->iobase_addr, 0xFFD0);
		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
		for (cnt = 0; cnt < sizeof(fw->rseq_0_reg) / 4; cnt++)
			fw->rseq_0_reg[cnt] = RD_REG_DWORD(dmp_reg++);

		WRT_REG_DWORD(&reg->iobase_addr, 0xFFE0);
		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
		for (cnt = 0; cnt < sizeof(fw->rseq_1_reg) / 4; cnt++)
			fw->rseq_1_reg[cnt] = RD_REG_DWORD(dmp_reg++);

		WRT_REG_DWORD(&reg->iobase_addr, 0xFFF0);
		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
		for (cnt = 0; cnt < sizeof(fw->rseq_2_reg) / 4; cnt++)
			fw->rseq_2_reg[cnt] = RD_REG_DWORD(dmp_reg++);

		/* Command DMA registers. */
		WRT_REG_DWORD(&reg->iobase_addr, 0x7100);
		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
		for (cnt = 0; cnt < sizeof(fw->cmd_dma_reg) / 4; cnt++)
			fw->cmd_dma_reg[cnt] = RD_REG_DWORD(dmp_reg++);

		/* Queues. */
		iter_reg = fw->req0_dma_reg;
		WRT_REG_DWORD(&reg->iobase_addr, 0x7200);
		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
		for (cnt = 0; cnt < 8; cnt++)
			*iter_reg++ = RD_REG_DWORD(dmp_reg++);

		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xE4);
		for (cnt = 0; cnt < 7; cnt++)
			*iter_reg++ = RD_REG_DWORD(dmp_reg++);

		iter_reg = fw->resp0_dma_reg;
		WRT_REG_DWORD(&reg->iobase_addr, 0x7300);
		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
		for (cnt = 0; cnt < 8; cnt++)
			*iter_reg++ = RD_REG_DWORD(dmp_reg++);

		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xE4);
		for (cnt = 0; cnt < 7; cnt++)
			*iter_reg++ = RD_REG_DWORD(dmp_reg++);

		iter_reg = fw->req1_dma_reg;
		WRT_REG_DWORD(&reg->iobase_addr, 0x7400);
		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
		for (cnt = 0; cnt < 8; cnt++)
			*iter_reg++ = RD_REG_DWORD(dmp_reg++);

		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xE4);
		for (cnt = 0; cnt < 7; cnt++)
			*iter_reg++ = RD_REG_DWORD(dmp_reg++);

		/* Transmit DMA registers. */
		iter_reg = fw->xmt0_dma_reg;
		WRT_REG_DWORD(&reg->iobase_addr, 0x7600);
		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
		for (cnt = 0; cnt < 16; cnt++)
			*iter_reg++ = RD_REG_DWORD(dmp_reg++);

		WRT_REG_DWORD(&reg->iobase_addr, 0x7610);
		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
		for (cnt = 0; cnt < 16; cnt++)
			*iter_reg++ = RD_REG_DWORD(dmp_reg++);

		iter_reg = fw->xmt1_dma_reg;
		WRT_REG_DWORD(&reg->iobase_addr, 0x7620);
		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
		for (cnt = 0; cnt < 16; cnt++)
			*iter_reg++ = RD_REG_DWORD(dmp_reg++);

		WRT_REG_DWORD(&reg->iobase_addr, 0x7630);
		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
		for (cnt = 0; cnt < 16; cnt++)
			*iter_reg++ = RD_REG_DWORD(dmp_reg++);

		iter_reg = fw->xmt2_dma_reg;
		WRT_REG_DWORD(&reg->iobase_addr, 0x7640);
		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
		for (cnt = 0; cnt < 16; cnt++)
			*iter_reg++ = RD_REG_DWORD(dmp_reg++);

		WRT_REG_DWORD(&reg->iobase_addr, 0x7650);
		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
		for (cnt = 0; cnt < 16; cnt++)
			*iter_reg++ = RD_REG_DWORD(dmp_reg++);

		iter_reg = fw->xmt3_dma_reg;
		WRT_REG_DWORD(&reg->iobase_addr, 0x7660);
		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
		for (cnt = 0; cnt < 16; cnt++)
			*iter_reg++ = RD_REG_DWORD(dmp_reg++);

		WRT_REG_DWORD(&reg->iobase_addr, 0x7670);
		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
		for (cnt = 0; cnt < 16; cnt++)
			*iter_reg++ = RD_REG_DWORD(dmp_reg++);

		iter_reg = fw->xmt4_dma_reg;
		WRT_REG_DWORD(&reg->iobase_addr, 0x7680);
		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
		for (cnt = 0; cnt < 16; cnt++)
			*iter_reg++ = RD_REG_DWORD(dmp_reg++);

		WRT_REG_DWORD(&reg->iobase_addr, 0x7690);
		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
		for (cnt = 0; cnt < 16; cnt++)
			*iter_reg++ = RD_REG_DWORD(dmp_reg++);

		WRT_REG_DWORD(&reg->iobase_addr, 0x76A0);
		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
		for (cnt = 0; cnt < sizeof(fw->xmt_data_dma_reg) / 4; cnt++)
			fw->xmt_data_dma_reg[cnt] = RD_REG_DWORD(dmp_reg++);

		/* Receive DMA registers. */
		iter_reg = fw->rcvt0_data_dma_reg;
		WRT_REG_DWORD(&reg->iobase_addr, 0x7700);
		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
		for (cnt = 0; cnt < 16; cnt++)
			*iter_reg++ = RD_REG_DWORD(dmp_reg++);

		WRT_REG_DWORD(&reg->iobase_addr, 0x7710);
		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
		for (cnt = 0; cnt < 16; cnt++)
			*iter_reg++ = RD_REG_DWORD(dmp_reg++);

		iter_reg = fw->rcvt1_data_dma_reg;
		WRT_REG_DWORD(&reg->iobase_addr, 0x7720);
		dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);