📄 aic79xx.reg
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address 0x03D access_mode RW modes M_SCSI field BITBUCKET 0x80 field ENSACHK 0x40 field ENSPCHK 0x20 field STIMESEL 0x18 field ENSTIMER 0x04 field ACTNEGEN 0x02 field STPWEN 0x01}/* * SCSI Transfer Control 2 */register SXFRCTL2 { address 0x03E access_mode RW modes M_SCSI field AUTORSTDIS 0x10 field CMDDMAEN 0x08 field ASU 0x07}/* * SCSI Bus Initiator IDs * Bitmask of observed initiators on the bus. */register BUSINITID { address 0x03C access_mode RW modes M_CFG size 2}/* * Data Length Counters * Packet byte counter. */register DLCOUNT { address 0x03C access_mode RW modes M_DFF0, M_DFF1 size 3}/* * Data FIFO Status */register DFFSTAT { address 0x03F access_mode RW modes M_SCSI field FIFO1FREE 0x20 field FIFO0FREE 0x10 /* * On the B, this enum only works * in the read direction. For writes, * you must use the B version of the * CURRFIFO_0 definition which is defined * as a constant outside of this register * definition to avoid confusing the * register pretty printing code. */ enum CURRFIFO 0x03 { CURRFIFO_0, CURRFIFO_1, CURRFIFO_NONE 0x3 }}const B_CURRFIFO_0 0x2/* * SCSI Bus Target IDs * Bitmask of observed targets on the bus. */register BUSTARGID { address 0x03E access_mode RW modes M_CFG size 2}/* * SCSI Control Signal Out */register SCSISIGO { address 0x040 access_mode RW modes M_DFF0, M_DFF1, M_SCSI field CDO 0x80 field IOO 0x40 field MSGO 0x20 field ATNO 0x10 field SELO 0x08 field BSYO 0x04 field REQO 0x02 field ACKO 0x01/* * Possible phases to write into SCSISIG0 */ enum PHASE_MASK CDO|IOO|MSGO { P_DATAOUT 0x0, P_DATAIN IOO, P_DATAOUT_DT P_DATAOUT|MSGO, P_DATAIN_DT P_DATAIN|MSGO, P_COMMAND CDO, P_MESGOUT CDO|MSGO, P_STATUS CDO|IOO, P_MESGIN CDO|IOO|MSGO }}register SCSISIGI { address 0x041 access_mode RO modes M_DFF0, M_DFF1, M_SCSI field CDI 0x80 field IOI 0x40 field MSGI 0x20 field ATNI 0x10 field SELI 0x08 field BSYI 0x04 field REQI 0x02 field ACKI 0x01/* * Possible phases in SCSISIGI */ enum PHASE_MASK CDO|IOO|MSGO { P_DATAOUT 0x0, P_DATAIN IOO, P_DATAOUT_DT P_DATAOUT|MSGO, P_DATAIN_DT P_DATAIN|MSGO, P_COMMAND CDO, P_MESGOUT CDO|MSGO, P_STATUS CDO|IOO, P_MESGIN CDO|IOO|MSGO }}/* * Multiple Target IDs * Bitmask of ids to respond as a target. */register MULTARGID { address 0x040 access_mode RW modes M_CFG size 2}/* * SCSI Phase */register SCSIPHASE { address 0x042 access_mode RO modes M_DFF0, M_DFF1, M_SCSI field STATUS_PHASE 0x20 field COMMAND_PHASE 0x10 field MSG_IN_PHASE 0x08 field MSG_OUT_PHASE 0x04 field DATA_PHASE_MASK 0x03 { DATA_OUT_PHASE 0x01, DATA_IN_PHASE 0x02 }}/* * SCSI Data 0 Image */register SCSIDAT0_IMG { address 0x043 access_mode RW modes M_DFF0, M_DFF1, M_SCSI}/* * SCSI Latched Data */register SCSIDAT { address 0x044 access_mode RW modes M_DFF0, M_DFF1, M_SCSI size 2}/* * SCSI Data Bus */register SCSIBUS { address 0x046 access_mode RW modes M_DFF0, M_DFF1, M_SCSI size 2}/* * Target ID In */register TARGIDIN { address 0x048 access_mode RO modes M_DFF0, M_DFF1, M_SCSI field CLKOUT 0x80 field TARGID 0x0F}/* * Selection/Reselection ID * Upper four bits are the device id. The ONEBIT is set when the re/selecting * device did not set its own ID. */register SELID { address 0x049 access_mode RW modes M_DFF0, M_DFF1, M_SCSI field SELID_MASK 0xf0 field ONEBIT 0x08}/* * SCSI Block Control * Controls Bus type and channel selection. SELWIDE allows for the * coexistence of 8bit and 16bit devices on a wide bus. */register SBLKCTL { address 0x04A access_mode RW modes M_DFF0, M_DFF1, M_SCSI field DIAGLEDEN 0x80 field DIAGLEDON 0x40 field ENAB40 0x08 /* LVD transceiver active */ field ENAB20 0x04 /* SE/HVD transceiver active */ field SELWIDE 0x02}/* * Option Mode */register OPTIONMODE { address 0x04A access_mode RW modes M_CFG field BIOSCANCTL 0x80 field AUTOACKEN 0x40 field BIASCANCTL 0x20 field BUSFREEREV 0x10 field ENDGFORMCHK 0x04 field AUTO_MSGOUT_DE 0x02 mask OPTIONMODE_DEFAULTS AUTO_MSGOUT_DE}/* * SCSI Status 0 */register SSTAT0 { address 0x04B access_mode RO modes M_DFF0, M_DFF1, M_SCSI field TARGET 0x80 /* Board acting as target */ field SELDO 0x40 /* Selection Done */ field SELDI 0x20 /* Board has been selected */ field SELINGO 0x10 /* Selection In Progress */ field IOERR 0x08 /* LVD Tranceiver mode changed */ field OVERRUN 0x04 /* SCSI Offset overrun detected */ field SPIORDY 0x02 /* SCSI PIO Ready */ field ARBDO 0x01 /* Arbitration Done Out */}/* * Clear SCSI Interrupt 0 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT0. */register CLRSINT0 { address 0x04B access_mode WO modes M_DFF0, M_DFF1, M_SCSI field CLRSELDO 0x40 field CLRSELDI 0x20 field CLRSELINGO 0x10 field CLRIOERR 0x08 field CLROVERRUN 0x04 field CLRSPIORDY 0x02 field CLRARBDO 0x01}/* * SCSI Interrupt Mode 0 * Setting any bit will enable the corresponding function * in SIMODE0 to interrupt via the IRQ pin. */register SIMODE0 { address 0x04B access_mode RW modes M_CFG field ENSELDO 0x40 field ENSELDI 0x20 field ENSELINGO 0x10 field ENIOERR 0x08 field ENOVERRUN 0x04 field ENSPIORDY 0x02 field ENARBDO 0x01}/* * SCSI Status 1 */register SSTAT1 { address 0x04C access_mode RO modes M_DFF0, M_DFF1, M_SCSI field SELTO 0x80 field ATNTARG 0x40 field SCSIRSTI 0x20 field PHASEMIS 0x10 field BUSFREE 0x08 field SCSIPERR 0x04 field STRB2FAST 0x02 field REQINIT 0x01}/* * Clear SCSI Interrupt 1 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1. */register CLRSINT1 { address 0x04C access_mode WO modes M_DFF0, M_DFF1, M_SCSI field CLRSELTIMEO 0x80 field CLRATNO 0x40 field CLRSCSIRSTI 0x20 field CLRBUSFREE 0x08 field CLRSCSIPERR 0x04 field CLRSTRB2FAST 0x02 field CLRREQINIT 0x01}/* * SCSI Status 2 */register SSTAT2 { address 0x04d access_mode RO modes M_DFF0, M_DFF1, M_SCSI field BUSFREETIME 0xc0 { BUSFREE_LQO 0x40, BUSFREE_DFF0 0x80, BUSFREE_DFF1 0xC0 } field NONPACKREQ 0x20 field EXP_ACTIVE 0x10 /* SCSI Expander Active */ field BSYX 0x08 /* Busy Expander */ field WIDE_RES 0x04 /* Modes 0 and 1 only */ field SDONE 0x02 /* Modes 0 and 1 only */ field DMADONE 0x01 /* Modes 0 and 1 only */}/* * Clear SCSI Interrupt 2 */register CLRSINT2 { address 0x04D access_mode WO modes M_DFF0, M_DFF1, M_SCSI field CLRNONPACKREQ 0x20 field CLRWIDE_RES 0x04 /* Modes 0 and 1 only */ field CLRSDONE 0x02 /* Modes 0 and 1 only */ field CLRDMADONE 0x01 /* Modes 0 and 1 only */}/* * SCSI Interrupt Mode 2 */register SIMODE2 { address 0x04D access_mode RW modes M_CFG field ENWIDE_RES 0x04 field ENSDONE 0x02 field ENDMADONE 0x01}/* * Physical Error Diagnosis */register PERRDIAG { address 0x04E access_mode RO modes M_DFF0, M_DFF1, M_SCSI field HIZERO 0x80 field HIPERR 0x40 field PREVPHASE 0x20 field PARITYERR 0x10 field AIPERR 0x08 field CRCERR 0x04 field DGFORMERR 0x02 field DTERR 0x01}/* * LQI Manager Current State */register LQISTATE { address 0x04E access_mode RO modes M_CFG}/* * SCSI Offset Count */register SOFFCNT { address 0x04F access_mode RO modes M_DFF0, M_DFF1, M_SCSI}/* * LQO Manager Current State */register LQOSTATE { address 0x04F access_mode RO modes M_CFG}/* * LQI Manager Status */register LQISTAT0 { address 0x050 access_mode RO modes M_DFF0, M_DFF1, M_SCSI field LQIATNQAS 0x20 field LQICRCT1 0x10 field LQICRCT2 0x08 field LQIBADLQT 0x04 field LQIATNLQ 0x02 field LQIATNCMD 0x01}/* * Clear LQI Interrupts 0 */register CLRLQIINT0 { address 0x050 access_mode WO modes M_DFF0, M_DFF1, M_SCSI field CLRLQIATNQAS 0x20 field CLRLQICRCT1 0x10 field CLRLQICRCT2 0x08 field CLRLQIBADLQT 0x04 field CLRLQIATNLQ 0x02 field CLRLQIATNCMD 0x01}/* * LQI Manager Interrupt Mode 0 */register LQIMODE0 { address 0x050 access_mode RW modes M_CFG field ENLQIATNQASK 0x20 field ENLQICRCT1 0x10 field ENLQICRCT2 0x08 field ENLQIBADLQT 0x04 field ENLQIATNLQ 0x02 field ENLQIATNCMD 0x01}/* * LQI Manager Status 1 */register LQISTAT1 { address 0x051 access_mode RO modes M_DFF0, M_DFF1, M_SCSI field LQIPHASE_LQ 0x80 field LQIPHASE_NLQ 0x40 field LQIABORT 0x20 field LQICRCI_LQ 0x10 field LQICRCI_NLQ 0x08 field LQIBADLQI 0x04 field LQIOVERI_LQ 0x02 field LQIOVERI_NLQ 0x01}/* * Clear LQI Manager Interrupts1 */register CLRLQIINT1 { address 0x051 access_mode WO modes M_DFF0, M_DFF1, M_SCSI field CLRLQIPHASE_LQ 0x80 field CLRLQIPHASE_NLQ 0x40 field CLRLIQABORT 0x20 field CLRLQICRCI_LQ 0x10 field CLRLQICRCI_NLQ 0x08 field CLRLQIBADLQI 0x04 field CLRLQIOVERI_LQ 0x02 field CLRLQIOVERI_NLQ 0x01}/* * LQI Manager Interrupt Mode 1 */register LQIMODE1 { address 0x051 access_mode RW modes M_CFG field ENLQIPHASE_LQ 0x80 /* LQIPHASE1 */ field ENLQIPHASE_NLQ 0x40 /* LQIPHASE2 */ field ENLIQABORT 0x20 field ENLQICRCI_LQ 0x10 /* LQICRCI1 */ field ENLQICRCI_NLQ 0x08 /* LQICRCI2 */ field ENLQIBADLQI 0x04 field ENLQIOVERI_LQ 0x02 /* LQIOVERI1 */ field ENLQIOVERI_NLQ 0x01 /* LQIOVERI2 */}/* * LQI Manager Status 2 */register LQISTAT2 { address 0x052 access_mode RO modes M_DFF0, M_DFF1, M_SCSI field PACKETIZED 0x80 field LQIPHASE_OUTPKT 0x40 field LQIWORKONLQ 0x20 field LQIWAITFIFO 0x10 field LQISTOPPKT 0x08 field LQISTOPLQ 0x04 field LQISTOPCMD 0x02 field LQIGSAVAIL 0x01}/* * SCSI Status 3 */register SSTAT3 { address 0x053 access_mode RO modes M_DFF0, M_DFF1, M_SCSI field NTRAMPERR 0x02 field OSRAMPERR 0x01}/* * Clear SCSI Status 3 */register CLRSINT3 { address 0x053 access_mode WO modes M_DFF0, M_DFF1, M_SCSI field CLRNTRAMPERR 0x02 field CLROSRAMPERR 0x01}/* * SCSI Interrupt Mode 3 */register SIMODE3 { address 0x053 access_mode RW modes M_CFG field ENNTRAMPERR 0x02 field ENOSRAMPERR 0x01}/* * LQO Manager Status 0 */register LQOSTAT0 { address 0x054 access_mode RO modes M_DFF0, M_DFF1, M_SCSI field LQOTARGSCBPERR 0x10 field LQOSTOPT2 0x08 field LQOATNLQ 0x04 field LQOATNPKT 0x02 field LQOTCRC 0x01}/* * Clear LQO Manager interrupt 0 */register CLRLQOINT0 { address 0x054 access_mode WO modes M_DFF0, M_DFF1, M_SCSI field CLRLQOTARGSCBPERR 0x10 field CLRLQOSTOPT2 0x08 field CLRLQOATNLQ 0x04 field CLRLQOATNPKT 0x02 field CLRLQOTCRC 0x01}/* * LQO Manager Interrupt Mode 0 */register LQOMODE0 { address 0x054 access_mode RW modes M_CFG field ENLQOTARGSCBPERR 0x10 field ENLQOSTOPT2 0x08 field ENLQOATNLQ 0x04 field ENLQOATNPKT 0x02 field ENLQOTCRC 0x01}/* * LQO Manager Status 1 */register LQOSTAT1 { address 0x055 access_mode RO modes M_DFF0, M_DFF1, M_SCSI field LQOINITSCBPERR 0x10 field LQOSTOPI2 0x08 field LQOBADQAS 0x04 field LQOBUSFREE 0x02 field LQOPHACHGINPKT 0x01}/* * Clear LOQ Interrupt 1 */register CLRLQOINT1 { address 0x055 access_mode WO modes M_DFF0, M_DFF1, M_SCSI field CLRLQOINITSCBPERR 0x10 field CLRLQOSTOPI2 0x08 field CLRLQOBADQAS 0x04 field CLRLQOBUSFREE 0x02 field CLRLQOPHACHGINPKT 0x01}/* * LQO Manager Interrupt Mode 1 */register LQOMODE1 { address 0x055 access_mode RW modes M_CFG field ENLQOINITSCBPERR 0x10 field ENLQOSTOPI2 0x08 field ENLQOBADQAS 0x04 field ENLQOBUSFREE 0x02 field ENLQOPHACHGINPKT 0x01}/* * LQO Manager Status 2 */register LQOSTAT2 { address 0x056 access_mode RO modes M_DFF0, M_DFF1, M_SCSI field LQOPKT 0xE0 field LQOWAITFIFO 0x10 field LQOPHACHGOUTPKT 0x02 /* outside of packet boundaries. */ field LQOSTOP0 0x01 /* Stopped after sending all packets */}/* * Output Synchronizer Space Count */register OS_SPACE_CNT { address 0x056 access_mode RO modes M_CFG}/* * SCSI Interrupt Mode 1 * Setting any bit will enable the corresponding function * in SIMODE1 to interrupt via the IRQ pin. */register SIMODE1 { address 0x057 access_mode RW modes M_DFF0, M_DFF1, M_SCSI field ENSELTIMO 0x80 field ENATNTARG 0x40 field ENSCSIRST 0x20 field ENPHASEMIS 0x10 field ENBUSFREE 0x08 field ENSCSIPERR 0x04 field ENSTRB2FAST 0x02 field ENREQINIT 0x01}/* * Good Status FIFO */register GSFIFO { address 0x058 access_mode RO size 2 modes M_DFF0, M_DFF1, M_SCSI}/* * Data FIFO SCSI Transfer Control */register DFFSXFRCTL { address 0x05A access_mode RW modes M_DFF0, M_DFF1 field DFFBITBUCKET 0x08 field CLRSHCNT 0x04 field CLRCHN 0x02 field RSTCHN 0x01}/* * Next SCSI Control Block */register NEXTSCB { address 0x05A access_mode RW size 2 modes M_SCSI}/* Rev B only. */register LQOSCSCTL { address 0x05A access_mode RW size 1 modes M_CFG field LQOH2A_VERSION 0x80 field LQONOCHKOVER 0x01}/* * SEQ Interrupts */register SEQINTSRC { address 0x05B access_mode RO modes M_DFF0, M_DFF1 field CTXTDONE 0x40 field SAVEPTRS 0x20 field CFG4DATA 0x10 field CFG4ISTAT 0x08 field CFG4TSTAT 0x04 field CFG4ICMD 0x02 field CFG4TCMD 0x01}/* * Clear Arp Interrupts */register CLRSEQINTSRC { address 0x05B access_mode WO modes M_DFF0, M_DFF1 field CLRCTXTDONE 0x40 field CLRSAVEPTRS 0x20 field CLRCFG4DATA 0x10 field CLRCFG4ISTAT 0x08 field CLRCFG4TSTAT 0x04 field CLRCFG4ICMD 0x02 field CLRCFG4TCMD 0x01}/* * SEQ Interrupt Enabled (Shared) */register SEQIMODE { address 0x05C access_mode RW⌨️ 快捷键说明
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