aic7xxx_reg.h_shipped

linux-2.6.15.6

#endif

#if AIC_DEBUG_REGISTERS
ahc_reg_print_t ahc_scb_scsioffset_print;
#else
#define ahc_scb_scsioffset_print(regvalue, cur_col, wrap) \
    ahc_print_register(NULL, 0, "SCB_SCSIOFFSET", 0xbe, regvalue, cur_col, wrap)
#endif

#if AIC_DEBUG_REGISTERS
ahc_reg_print_t ahc_scb_next_print;
#else
#define ahc_scb_next_print(regvalue, cur_col, wrap) \
    ahc_print_register(NULL, 0, "SCB_NEXT", 0xbf, regvalue, cur_col, wrap)
#endif

#if AIC_DEBUG_REGISTERS
ahc_reg_print_t ahc_scb_64_spare_print;
#else
#define ahc_scb_64_spare_print(regvalue, cur_col, wrap) \
    ahc_print_register(NULL, 0, "SCB_64_SPARE", 0xc0, regvalue, cur_col, wrap)
#endif

#if AIC_DEBUG_REGISTERS
ahc_reg_print_t ahc_seectl_2840_print;
#else
#define ahc_seectl_2840_print(regvalue, cur_col, wrap) \
    ahc_print_register(NULL, 0, "SEECTL_2840", 0xc0, regvalue, cur_col, wrap)
#endif

#if AIC_DEBUG_REGISTERS
ahc_reg_print_t ahc_status_2840_print;
#else
#define ahc_status_2840_print(regvalue, cur_col, wrap) \
    ahc_print_register(NULL, 0, "STATUS_2840", 0xc1, regvalue, cur_col, wrap)
#endif

#if AIC_DEBUG_REGISTERS
ahc_reg_print_t ahc_scb_64_btt_print;
#else
#define ahc_scb_64_btt_print(regvalue, cur_col, wrap) \
    ahc_print_register(NULL, 0, "SCB_64_BTT", 0xd0, regvalue, cur_col, wrap)
#endif

#if AIC_DEBUG_REGISTERS
ahc_reg_print_t ahc_cchaddr_print;
#else
#define ahc_cchaddr_print(regvalue, cur_col, wrap) \
    ahc_print_register(NULL, 0, "CCHADDR", 0xe0, regvalue, cur_col, wrap)
#endif

#if AIC_DEBUG_REGISTERS
ahc_reg_print_t ahc_cchcnt_print;
#else
#define ahc_cchcnt_print(regvalue, cur_col, wrap) \
    ahc_print_register(NULL, 0, "CCHCNT", 0xe8, regvalue, cur_col, wrap)
#endif

#if AIC_DEBUG_REGISTERS
ahc_reg_print_t ahc_ccsgram_print;
#else
#define ahc_ccsgram_print(regvalue, cur_col, wrap) \
    ahc_print_register(NULL, 0, "CCSGRAM", 0xe9, regvalue, cur_col, wrap)
#endif

#if AIC_DEBUG_REGISTERS
ahc_reg_print_t ahc_ccsgaddr_print;
#else
#define ahc_ccsgaddr_print(regvalue, cur_col, wrap) \
    ahc_print_register(NULL, 0, "CCSGADDR", 0xea, regvalue, cur_col, wrap)
#endif

#if AIC_DEBUG_REGISTERS
ahc_reg_print_t ahc_ccsgctl_print;
#else
#define ahc_ccsgctl_print(regvalue, cur_col, wrap) \
    ahc_print_register(NULL, 0, "CCSGCTL", 0xeb, regvalue, cur_col, wrap)
#endif

#if AIC_DEBUG_REGISTERS
ahc_reg_print_t ahc_ccscbram_print;
#else
#define ahc_ccscbram_print(regvalue, cur_col, wrap) \
    ahc_print_register(NULL, 0, "CCSCBRAM", 0xec, regvalue, cur_col, wrap)
#endif

#if AIC_DEBUG_REGISTERS
ahc_reg_print_t ahc_ccscbaddr_print;
#else
#define ahc_ccscbaddr_print(regvalue, cur_col, wrap) \
    ahc_print_register(NULL, 0, "CCSCBADDR", 0xed, regvalue, cur_col, wrap)
#endif

#if AIC_DEBUG_REGISTERS
ahc_reg_print_t ahc_ccscbctl_print;
#else
#define ahc_ccscbctl_print(regvalue, cur_col, wrap) \
    ahc_print_register(NULL, 0, "CCSCBCTL", 0xee, regvalue, cur_col, wrap)
#endif

#if AIC_DEBUG_REGISTERS
ahc_reg_print_t ahc_ccscbcnt_print;
#else
#define ahc_ccscbcnt_print(regvalue, cur_col, wrap) \
    ahc_print_register(NULL, 0, "CCSCBCNT", 0xef, regvalue, cur_col, wrap)
#endif

#if AIC_DEBUG_REGISTERS
ahc_reg_print_t ahc_scbbaddr_print;
#else
#define ahc_scbbaddr_print(regvalue, cur_col, wrap) \
    ahc_print_register(NULL, 0, "SCBBADDR", 0xf0, regvalue, cur_col, wrap)
#endif

#if AIC_DEBUG_REGISTERS
ahc_reg_print_t ahc_ccscbptr_print;
#else
#define ahc_ccscbptr_print(regvalue, cur_col, wrap) \
    ahc_print_register(NULL, 0, "CCSCBPTR", 0xf1, regvalue, cur_col, wrap)
#endif

#if AIC_DEBUG_REGISTERS
ahc_reg_print_t ahc_hnscb_qoff_print;
#else
#define ahc_hnscb_qoff_print(regvalue, cur_col, wrap) \
    ahc_print_register(NULL, 0, "HNSCB_QOFF", 0xf4, regvalue, cur_col, wrap)
#endif

#if AIC_DEBUG_REGISTERS
ahc_reg_print_t ahc_snscb_qoff_print;
#else
#define ahc_snscb_qoff_print(regvalue, cur_col, wrap) \
    ahc_print_register(NULL, 0, "SNSCB_QOFF", 0xf6, regvalue, cur_col, wrap)
#endif

#if AIC_DEBUG_REGISTERS
ahc_reg_print_t ahc_sdscb_qoff_print;
#else
#define ahc_sdscb_qoff_print(regvalue, cur_col, wrap) \
    ahc_print_register(NULL, 0, "SDSCB_QOFF", 0xf8, regvalue, cur_col, wrap)
#endif

#if AIC_DEBUG_REGISTERS
ahc_reg_print_t ahc_qoff_ctlsta_print;
#else
#define ahc_qoff_ctlsta_print(regvalue, cur_col, wrap) \
    ahc_print_register(NULL, 0, "QOFF_CTLSTA", 0xfa, regvalue, cur_col, wrap)
#endif

#if AIC_DEBUG_REGISTERS
ahc_reg_print_t ahc_dff_thrsh_print;
#else
#define ahc_dff_thrsh_print(regvalue, cur_col, wrap) \
    ahc_print_register(NULL, 0, "DFF_THRSH", 0xfb, regvalue, cur_col, wrap)
#endif

#if AIC_DEBUG_REGISTERS
ahc_reg_print_t ahc_sg_cache_shadow_print;
#else
#define ahc_sg_cache_shadow_print(regvalue, cur_col, wrap) \
    ahc_print_register(NULL, 0, "SG_CACHE_SHADOW", 0xfc, regvalue, cur_col, wrap)
#endif

#if AIC_DEBUG_REGISTERS
ahc_reg_print_t ahc_sg_cache_pre_print;
#else
#define ahc_sg_cache_pre_print(regvalue, cur_col, wrap) \
    ahc_print_register(NULL, 0, "SG_CACHE_PRE", 0xfc, regvalue, cur_col, wrap)
#endif


#define	SCSISEQ         		0x00
#define		TEMODE          	0x80
#define		SCSIRSTO        	0x01

#define	SXFRCTL0        		0x01
#define		DFON            	0x80
#define		DFPEXP          	0x40
#define		FAST20          	0x20
#define		CLRSTCNT        	0x10
#define		SPIOEN          	0x08
#define		SCAMEN          	0x04
#define		CLRCHN          	0x02

#define	SXFRCTL1        		0x02
#define		STIMESEL        	0x18
#define		BITBUCKET       	0x80
#define		SWRAPEN         	0x40
#define		ENSTIMER        	0x04
#define		ACTNEGEN        	0x02
#define		STPWEN          	0x01

#define	SCSISIGO        		0x03
#define		CDO             	0x80
#define		IOO             	0x40
#define		MSGO            	0x20
#define		ATNO            	0x10
#define		SELO            	0x08
#define		BSYO            	0x04
#define		REQO            	0x02
#define		ACKO            	0x01

#define	SCSISIGI        		0x03
#define		P_DATAIN_DT     	0x60
#define		P_DATAOUT_DT    	0x20
#define		ATNI            	0x10
#define		SELI            	0x08
#define		BSYI            	0x04
#define		REQI            	0x02
#define		ACKI            	0x01

#define	SCSIRATE        		0x04
#define		SXFR            	0x70
#define		SOFS            	0x0f
#define		SXFR_ULTRA2     	0x0f
#define		WIDEXFER        	0x80
#define		ENABLE_CRC      	0x40
#define		SINGLE_EDGE     	0x10

#define	SCSIID          		0x05
#define	SCSIOFFSET      		0x05
#define		SOFS_ULTRA2     	0x7f

#define	SCSIDATL        		0x06

#define	SCSIDATH        		0x07

#define	STCNT           		0x08

#define	OPTIONMODE      		0x08
#define		OPTIONMODE_DEFAULTS	0x03
#define		AUTORATEEN      	0x80
#define		AUTOACKEN       	0x40
#define		ATNMGMNTEN      	0x20
#define		BUSFREEREV      	0x10
#define		EXPPHASEDIS     	0x08
#define		SCSIDATL_IMGEN  	0x04
#define		AUTO_MSGOUT_DE  	0x02
#define		DIS_MSGIN_DUALEDGE	0x01

#define	TARGCRCCNT      		0x0a

#define	CLRSINT0        		0x0b
#define		CLRSELDO        	0x40
#define		CLRSELDI        	0x20
#define		CLRSELINGO      	0x10
#define		CLRIOERR        	0x08
#define		CLRSWRAP        	0x08
#define		CLRSPIORDY      	0x02

#define	SSTAT0          		0x0b
#define		TARGET          	0x80
#define		SELDO           	0x40
#define		SELDI           	0x20
#define		SELINGO         	0x10
#define		SWRAP           	0x08
#define		IOERR           	0x08
#define		SDONE           	0x04
#define		SPIORDY         	0x02
#define		DMADONE         	0x01

#define	CLRSINT1        		0x0c
#define		CLRSELTIMEO     	0x80
#define		CLRATNO         	0x40
#define		CLRSCSIRSTI     	0x20
#define		CLRBUSFREE      	0x08
#define		CLRSCSIPERR     	0x04
#define		CLRPHASECHG     	0x02
#define		CLRREQINIT      	0x01

#define	SSTAT1          		0x0c
#define		SELTO           	0x80
#define		ATNTARG         	0x40
#define		SCSIRSTI        	0x20
#define		PHASEMIS        	0x10
#define		BUSFREE         	0x08
#define		SCSIPERR        	0x04
#define		PHASECHG        	0x02
#define		REQINIT         	0x01

#define	SSTAT2          		0x0d
#define		SFCNT           	0x1f
#define		OVERRUN         	0x80
#define		SHVALID         	0x40
#define		EXP_ACTIVE      	0x10
#define		CRCVALERR       	0x08
#define		CRCENDERR       	0x04
#define		CRCREQERR       	0x02
#define		DUAL_EDGE_ERR   	0x01

#define	SSTAT3          		0x0e
#define		SCSICNT         	0xf0
#define		U2OFFCNT        	0x7f
#define		OFFCNT          	0x0f

#define	SCSIID_ULTRA2   		0x0f

#define	SIMODE0         		0x10
#define		ENSELDO         	0x40
#define		ENSELDI         	0x20
#define		ENSELINGO       	0x10
#define		ENIOERR         	0x08
#define		ENSWRAP         	0x08
#define		ENSDONE         	0x04
#define		ENSPIORDY       	0x02
#define		ENDMADONE       	0x01

#define	SIMODE1         		0x11
#define		ENSELTIMO       	0x80
#define		ENATNTARG       	0x40
#define		ENSCSIRST       	0x20
#define		ENPHASEMIS      	0x10
#define		ENBUSFREE       	0x08
#define		ENSCSIPERR      	0x04
#define		ENPHASECHG      	0x02
#define		ENREQINIT       	0x01

#define	SCSIBUSL        		0x12

#define	SCSIBUSH        		0x13

#define	SXFRCTL2        		0x13
#define		ASYNC_SETUP     	0x07
#define		AUTORSTDIS      	0x10
#define		CMDDMAEN        	0x08

#define	SHADDR          		0x14

#define	SELTIMER        		0x18
#define	TARGIDIN        		0x18
#define		STAGE6          	0x20
#define		STAGE5          	0x10
#define		STAGE4          	0x08
#define		STAGE3          	0x04
#define		STAGE2          	0x02
#define		STAGE1          	0x01

#define	SELID           		0x19
#define		SELID_MASK      	0xf0
#define		ONEBIT          	0x08

#define	SCAMCTL         		0x1a
#define		SCAMLVL         	0x03
#define		ENSCAMSELO      	0x80
#define		CLRSCAMSELID    	0x40
#define		ALTSTIM         	0x20
#define		DFLTTID         	0x10

#define	TARGID          		0x1b

#define	SPIOCAP         		0x1b
#define		SOFT1           	0x80
#define		SOFT0           	0x40
#define		SOFTCMDEN       	0x20
#define		EXT_BRDCTL      	0x10
#define		SEEPROM         	0x08
#define		EEPROM          	0x04
#define		ROM             	0x02
#define		SSPIOCPS        	0x01

#define	BRDCTL          		0x1d
#define		BRDDAT7         	0x80
#define		BRDDAT6         	0x40
#define		BRDDAT5         	0x20
#define		BRDDAT4         	0x10
#define		BRDSTB          	0x10
#define		BRDDAT3         	0x08
#define		BRDCS           	0x08
#define		BRDDAT2         	0x04
#define		BRDRW           	0x04
#define		BRDRW_ULTRA2    	0x02
#define		BRDCTL1         	0x02
#define		BRDCTL0         	0x01
#define		BRDSTB_ULTRA2   	0x01

#define	SEECTL          		0x1e
#define		EXTARBACK       	0x80
#define		EXTARBREQ       	0x40
#define		SEEMS           	0x20
#define		SEERDY          	0x10
#define		SEECS           	0x08
#define		SEECK           	0x04
#define		SEEDO           	0x02
#define		SEEDI           	0x01

#define	SBLKCTL         		0x1f
#define		DIAGLEDEN       	0x80
#define		DIAGLEDON       	0x40
#define		AUTOFLUSHDIS    	0x20
#define		ENAB40          	0x08
#define		SELBUSB         	0x08
#define		ENAB20          	0x04
#define		SELWIDE         	0x02
#define		XCVR            	0x01

#define	BUSY_TARGETS    		0x20
#define	TARG_SCSIRATE   		0x20

#define	ULTRA_ENB       		0x30
#define	CMDSIZE_TABLE   		0x30

#define	DISC_DSB        		0x32

#define	CMDSIZE_TABLE_TAIL		0x34

#define	MWI_RESIDUAL    		0x38

#define	NEXT_QUEUED_SCB 		0x39

#define	MSG_OUT         		0x3a

#define	DMAPARAMS       		0x3b
#define		PRELOADEN       	0x80
#define		WIDEODD         	0x40
#define		SCSIEN          	0x20
#define		SDMAEN          	0x10
#define		SDMAENACK       	0x10
#define		HDMAEN          	0x08
#define		HDMAENACK       	0x08
#define		DIRECTION       	0x04
#define		FIFOFLUSH       	0x02
#define		FIFORESET       	0x01

#define	SEQ_FLAGS       		0x3c
#define		NOT_IDENTIFIED  	0x80
#define		NO_CDB_SENT     	0x40
#define		TARGET_CMD_IS_TAGGED	0x40
#define		DPHASE          	0x20
#define		TARG_CMD_PENDING	0x10
#define		CMDPHASE_PENDING	0x08
#define		DPHASE_PENDING  	0x04
#define		SPHASE_PENDING  	0x02
#define		NO_DISCONNECT   	0x01

#define	SAVED_SCSIID    		0x3d

#define	SAVED_LUN       		0x3e

#define	LASTPHASE       		0x3f
#define		P_MESGIN        	0xe0
#define		PHASE_MASK      	0xe0
#define		P_STATUS        	0xc0
#define		P_MESGOUT       	0xa0
#define		P_COMMAND       	0x80
#define		P_DATAIN        	0x40
#define		P_BUSFREE       	0x01
#define		P_DATAOUT       	0x00