aic7xxx.reg

linux-2.6.15.6

						 * (command was null), so tell
						 * it that it can fill the
						 * message buffer.
						 */
	mask	SEQ_SG_FIXUP	0xb0|SEQINT	/* need help with fixing up
						 * the sg array pointer after
						 * a phasemis with no valid
						 * sg elements in the shadow
						 * pipeline.
						 */
	mask	TRACEPOINT2	0xc0|SEQINT
	mask	MSGIN_PHASEMIS	0xd0|SEQINT	/*
						 * Target changed phase on us
						 * when we were expecting
						 * another msgin byte.
						 */
	mask	DATA_OVERRUN	0xe0|SEQINT	/*
						 * Target attempted to write
						 * beyond the bounds of its
						 * command.
						 */

	mask	SEQINT_MASK	0xf0|SEQINT	/* SEQINT Status Codes */
	mask	INT_PEND  (BRKADRINT|SEQINT|SCSIINT|CMDCMPLT)
}

/*
 * Hard Error (p. 3-53)
 * Reporting of catastrophic errors.  You usually cannot recover from
 * these without a full board reset.
 */
register ERROR {
	address			0x092
	access_mode RO
	bit	CIOPARERR	0x80	/* Ultra2 only */
	bit	PCIERRSTAT	0x40	/* PCI only */
	bit	MPARERR		0x20	/* PCI only */
	bit	DPARERR		0x10	/* PCI only */
	bit	SQPARERR	0x08
	bit	ILLOPCODE	0x04
	bit	ILLSADDR	0x02
	bit	DSCTMOUT	0x02	/* Ultra3 only */
	bit	ILLHADDR	0x01
}

/*
 * Clear Interrupt Status (p. 3-52)
 */
register CLRINT {
	address			0x092
	access_mode WO
	bit	CLRPARERR	0x10	/* PCI only */
	bit	CLRBRKADRINT	0x08
	bit	CLRSCSIINT      0x04
	bit	CLRCMDINT 	0x02
	bit	CLRSEQINT 	0x01
}

register DFCNTRL {
	address			0x093
	access_mode RW
	bit	PRELOADEN	0x80	/* aic7890 only */
	bit	WIDEODD		0x40
	bit	SCSIEN		0x20
	bit	SDMAEN		0x10
	bit	SDMAENACK	0x10
	bit	HDMAEN		0x08
	bit	HDMAENACK	0x08
	bit	DIRECTION	0x04
	bit	FIFOFLUSH	0x02
	bit	FIFORESET	0x01
}

register DFSTATUS {
	address			0x094
	access_mode RO
	bit	PRELOAD_AVAIL	0x80
	bit	DWORDEMP	0x20
	bit	MREQPEND	0x10
	bit	HDONE		0x08
	bit	DFTHRESH	0x04
	bit	FIFOFULL	0x02
	bit	FIFOEMP		0x01
}

register DFDAT {
	address			0x099
	access_mode RW
}

/*
 * SCB Auto Increment (p. 3-59)
 * Byte offset into the SCB Array and an optional bit to allow auto
 * incrementing of the address during download and upload operations
 */
register SCBCNT {
	address			0x09a
	access_mode RW
	bit	SCBAUTO		0x80
	mask	SCBCNT_MASK	0x1f
}

/*
 * Queue In FIFO (p. 3-60)
 * Input queue for queued SCBs (commands that the seqencer has yet to start)
 */
register QINFIFO {
	address			0x09b
	access_mode RW
}

/*
 * Queue In Count (p. 3-60)
 * Number of queued SCBs
 */
register QINCNT	{
	address			0x09c
	access_mode RO
}

/*
 * SCSIDATL IMAGE Register (p. 5-104)
 * Write to this register also go to SCSIDATL but this register will preserve
 * the data for later reading as long as the SCSIDATL_IMGEN bit in the
 * OPTIONMODE register is set.
 */
register SCSIDATL_IMG {
	address			0x09c
	access_mode RW
}

/*
 * Queue Out FIFO (p. 3-61)
 * Queue of SCBs that have completed and await the host
 */
register QOUTFIFO {
	address			0x09d
	access_mode WO
}

/*
 * CRC Control 1 Register (p. 5-105)
 * Control bits for the Ultra 160/m CRC facilities
 */
register CRCCONTROL1 {
	address			0x09d
	access_mode RW
	bit	CRCONSEEN	0x80 /* CRC ON Single Edge ENable */
	bit	CRCVALCHKEN	0x40 /* CRC Value Check Enable */
	bit	CRCENDCHKEN	0x20 /* CRC End Check Enable */
	bit	CRCREQCHKEN	0x10
	bit	TARGCRCENDEN	0x08 /* Enable End CRC transfer when target */
	bit	TARGCRCCNTEN	0x04 /* Enable CRC transfer when target */
}

/*
 * Queue Out Count (p. 3-61)
 * Number of queued SCBs in the Out FIFO
 */
register QOUTCNT {
	address			0x09e
	access_mode RO
}

/*
 * SCSI Phase Register (p. 5-106)
 * Current bus phase
 */
register SCSIPHASE {
	address			0x09e
	access_mode RO
	bit	SP_STATUS		0x20
	bit	SP_COMMAND		0x10
	bit	SP_MSG_IN		0x08
	bit	SP_MSG_OUT		0x04
	bit	SP_DATA_IN		0x02
	bit	SP_DATA_OUT	0x01
}

/*
 * Special Function
 */
register SFUNCT {
	address			0x09f
	access_mode RW
	bit	ALT_MODE	0x80
}

/*
 * SCB Definition (p. 5-4)
 */
scb {
	address			0x0a0
	SCB_CONTROL {
		size	1
		bit	MK_MESSAGE      0x80
		bit	DISCENB         0x40
		bit	TAG_ENB		0x20
		bit	DISCONNECTED	0x04
		mask	SCB_TAG_TYPE	0x03
	}
	SCB_TCL {
		size	1
		bit	SELBUSB		0x08
		mask	TID		0xf0
		mask	LID		0x07
	}
	SCB_TARGET_STATUS {
		size	1
	}
	SCB_SGCOUNT {
		size	1
	}
	SCB_SGPTR {
		size	4
	}
	SCB_RESID_SGCNT {
		size	1
	}
	SCB_RESID_DCNT	{
		size	3
	}
	SCB_DATAPTR {
		size	4
	}
	SCB_DATACNT {
		/*
		 * Really only 3 bytes, but padded to make
		 * the kernel's job easier.
		 */
		size	4
	}
	SCB_CMDPTR {
		size	4
	}
	SCB_CMDLEN {
		size	1
	}
	SCB_TAG {
		size	1
	}
	SCB_NEXT {
		size	1
	}
	SCB_PREV {
		size	1
	}
	SCB_BUSYTARGETS {
		size	4
	}
}

const	SG_SIZEOF	0x08		/* sizeof(struct ahc_dma) */

/* --------------------- AHA-2840-only definitions -------------------- */

register SEECTL_2840 {
	address			0x0c0
	access_mode RW
	bit	CS_2840		0x04
	bit	CK_2840		0x02
	bit	DO_2840		0x01
}

register STATUS_2840 {
	address			0x0c1
	access_mode RW
	bit	EEPROM_TF	0x80
	mask	BIOS_SEL	0x60
	mask	ADSEL		0x1e
	bit	DI_2840		0x01
}

/* --------------------- AIC-7870-only definitions -------------------- */

register DSPCISTATUS {
	address			0x086
	mask	DFTHRSH_100	0xc0
}

register CCHADDR {
	address			0x0E0
	size 8
}

register CCHCNT {
	address			0x0E8
}

register CCSGRAM {
	address			0x0E9
}

register CCSGADDR {
	address			0x0EA
}

register CCSGCTL {
	address			0x0EB
	bit	CCSGDONE	0x80
	bit	CCSGEN		0x08
	bit	FLAG		0x02
	bit	CCSGRESET	0x01
}

register CCSCBCNT {
	address			0xEF
}

register CCSCBCTL {
	address			0x0EE
	bit	CCSCBDONE	0x80
	bit	ARRDONE		0x40	/* SCB Array prefetch done */
	bit	CCARREN		0x10
	bit	CCSCBEN		0x08
	bit	CCSCBDIR	0x04
	bit	CCSCBRESET	0x01
}

register CCSCBADDR {
	address			0x0ED
}

register CCSCBRAM {
	address			0xEC
}

register CCSCBPTR {
	address			0x0F1
}

register HNSCB_QOFF {
	address			0x0F4
}

register HESCB_QOFF {
	address			0x0F5
}

register SNSCB_QOFF {
	address			0x0F6
}

register SESCB_QOFF {
	address			0x0F7
}

register SDSCB_QOFF {
	address			0x0F8
}

register QOFF_CTLSTA {
	address			0x0FA
	bit	ESTABLISH_SCB_AVAIL	0x80
	bit	SCB_AVAIL	0x40
	bit	SNSCB_ROLLOVER	0x20
	bit	SDSCB_ROLLOVER	0x10
	bit	SESCB_ROLLOVER	0x08
	mask	SCB_QSIZE	0x07
	mask	SCB_QSIZE_256	0x06
}

register DFF_THRSH {
	address			0x0FB
	mask	WR_DFTHRSH	0x70
	mask	RD_DFTHRSH	0x07
	mask	RD_DFTHRSH_MIN	0x00
	mask	RD_DFTHRSH_25	0x01
	mask	RD_DFTHRSH_50	0x02
	mask	RD_DFTHRSH_63	0x03
	mask	RD_DFTHRSH_75	0x04
	mask	RD_DFTHRSH_85	0x05
	mask	RD_DFTHRSH_90	0x06
	mask	RD_DFTHRSH_MAX	0x07
	mask	WR_DFTHRSH_MIN	0x00
	mask	WR_DFTHRSH_25	0x10
	mask	WR_DFTHRSH_50	0x20
	mask	WR_DFTHRSH_63	0x30
	mask	WR_DFTHRSH_75	0x40
	mask	WR_DFTHRSH_85	0x50
	mask	WR_DFTHRSH_90	0x60
	mask	WR_DFTHRSH_MAX	0x70
}

register SG_CACHEPTR {
	access_mode RW
	address			0x0fc
	mask	SG_USER_DATA	0xfc
	bit	LAST_SEG	0x02
	bit	LAST_SEG_DONE	0x01
}

register BRDCTL	{
	address			0x01d
	bit	BRDDAT7		0x80
	bit	BRDDAT6		0x40
	bit	BRDDAT5		0x20
	bit	BRDSTB		0x10
	bit	BRDCS		0x08
	bit	BRDRW		0x04
	bit	BRDCTL1		0x02
	bit	BRDCTL0		0x01
	/* 7890 Definitions */
	bit	BRDDAT4		0x10
	bit	BRDDAT3		0x08
	bit	BRDDAT2		0x04
	bit	BRDRW_ULTRA2	0x02
	bit	BRDSTB_ULTRA2	0x01
}

/*
 * Serial EEPROM Control (p. 4-92 in 7870 Databook)
 * Controls the reading and writing of an external serial 1-bit
 * EEPROM Device.  In order to access the serial EEPROM, you must
 * first set the SEEMS bit that generates a request to the memory
 * port for access to the serial EEPROM device.  When the memory
 * port is not busy servicing another request, it reconfigures
 * to allow access to the serial EEPROM.  When this happens, SEERDY
 * gets set high to verify that the memory port access has been
 * granted.  
 *
 * After successful arbitration for the memory port, the SEECS bit of 
 * the SEECTL register is connected to the chip select.  The SEECK, 
 * SEEDO, and SEEDI are connected to the clock, data out, and data in 
 * lines respectively.  The SEERDY bit of SEECTL is useful in that it 
 * gives us an 800 nsec timer.  After a write to the SEECTL register, 
 * the SEERDY goes high 800 nsec later.  The one exception to this is 
 * when we first request access to the memory port.  The SEERDY goes 
 * high to signify that access has been granted and, for this case, has 
 * no implied timing.
 *
 * See 93cx6.c for detailed information on the protocol necessary to 
 * read the serial EEPROM.
 */
register SEECTL {
	address			0x01e
	bit	EXTARBACK	0x80
	bit	EXTARBREQ	0x40
	bit	SEEMS		0x20
	bit	SEERDY		0x10
	bit	SEECS		0x08
	bit	SEECK		0x04
	bit	SEEDO		0x02
	bit	SEEDI		0x01
}
/* ---------------------- Scratch RAM Offsets ------------------------- */
/* These offsets are either to values that are initialized by the board's
 * BIOS or are specified by the sequencer code.
 *
 * The host adapter card (at least the BIOS) uses 20-2f for SCSI
 * device information, 32-33 and 5a-5f as well. As it turns out, the
 * BIOS trashes 20-2f, writing the synchronous negotiation results
 * on top of the BIOS values, so we re-use those for our per-target
 * scratchspace (actually a value that can be copied directly into
 * SCSIRATE).  The kernel driver will enable synchronous negotiation
 * for all targets that have a value other than 0 in the lower four
 * bits of the target scratch space.  This should work regardless of
 * whether the bios has been installed.
 */

scratch_ram {
	address			0x020

	/*
	 * 1 byte per target starting at this address for configuration values
	 */
	TARG_SCSIRATE {
		size		16
	}
	/*
	 * Bit vector of targets that have ULTRA enabled.
	 */
	ULTRA_ENB {
		size		2
	}
	/*
	 * Bit vector of targets that have disconnection disabled.
	 */
	DISC_DSB {
		size		2
	}
	/*
	 * Single byte buffer used to designate the type or message
	 * to send to a target.
	 */
	MSG_OUT {
		size		1
	}
	/* Parameters for DMA Logic */
	DMAPARAMS {
		size		1
		bit	PRELOADEN	0x80
		bit	WIDEODD		0x40
		bit	SCSIEN		0x20
		bit	SDMAEN		0x10
		bit	SDMAENACK	0x10
		bit	HDMAEN		0x08
		bit	HDMAENACK	0x08
		bit	DIRECTION	0x04
		bit	FIFOFLUSH	0x02
		bit	FIFORESET	0x01
	}
	SEQ_FLAGS {
		size		1
		bit	IDENTIFY_SEEN	0x80
		bit	SCBPTR_VALID	0x20
		bit	DPHASE		0x10
		bit	AMTARGET	0x08
		bit	WIDE_BUS	0x02
		bit	TWIN_BUS	0x01
	}
	/*
	 * Temporary storage for the
	 * target/channel/lun of a
	 * reconnecting target
	 */
	SAVED_TCL {
		size		1
	}
	/* Working value of the number of SG segments left */
	SG_COUNT {
		size		1
	}
	/* Working value of SG pointer */
	SG_NEXT	{
		size		4
	}
	/*
	 * The last bus phase as seen by the sequencer. 
	 */
	LASTPHASE {
		size		1
		bit	CDI		0x80
		bit	IOI		0x40
		bit	MSGI		0x20
		mask	PHASE_MASK	CDI|IOI|MSGI
		mask	P_DATAOUT	0x00
		mask	P_DATAIN	IOI
		mask	P_COMMAND	CDI
		mask	P_MESGOUT	CDI|MSGI
		mask	P_STATUS	CDI|IOI
		mask	P_MESGIN	CDI|IOI|MSGI
		mask	P_BUSFREE	0x01
	}
	/*
	 * head of list of SCBs awaiting
	 * selection
	 */
	WAITING_SCBH {
		size		1
	}
	/*
	 * head of list of SCBs that are
	 * disconnected.  Used for SCB
	 * paging.
	 */
	DISCONNECTED_SCBH {
		size		1
	}
	/*
	 * head of list of SCBs that are
	 * not in use.  Used for SCB paging.
	 */
	FREE_SCBH {
		size		1
	}
	/*
	 * Address of the hardware scb array in the host.
	 */
	HSCB_ADDR {
		size		4
	}
	/*
	 * Address of the 256 byte array storing the SCBID of outstanding
	 * untagged SCBs indexed by TCL.
	 */
	SCBID_ADDR {
		size		4
	}
	/*
	 * Address of the array of command descriptors used to store
	 * information about incoming selections.
	 */
	TMODE_CMDADDR {
		size		4
	}
	KERNEL_QINPOS {
		size		1
	}
	QINPOS {
		size		1
	}
	QOUTPOS {
		size		1
	}
	/*
	 * Offset into the command descriptor array for the next
	 * available desciptor to use.
	 */
	TMODE_CMDADDR_NEXT {
		size		1
	}
	ARG_1 {
		size		1
		mask	SEND_MSG	0x80
		mask	SEND_SENSE	0x40
		mask	SEND_REJ	0x20
		mask	MSGOUT_PHASEMIS	0x10
		alias	RETURN_1
	}
	ARG_2 {
		size		1
		alias	RETURN_2
	}

	/*
	 * Snapshot of MSG_OUT taken after each message is sent.
	 */
	LAST_MSG {
		size		1
	}

	/*
	 * Number of times we have filled the CCSGRAM with prefetched
	 * SG elements.
	 */
	PREFETCH_CNT {
		size		1
	}


	/*
	 * These are reserved registers in the card's scratch ram.  Some of
	 * the values are specified in the AHA2742 technical reference manual
	 * and are initialized by the BIOS at boot time.
	 */
	SCSICONF {
		address		0x05a
		size		1
		bit	TERM_ENB	0x80
		bit	RESET_SCSI	0x40
		mask	HSCSIID		0x07	/* our SCSI ID */
		mask	HWSCSIID	0x0f	/* our SCSI ID if Wide Bus */
	}
	HOSTCONF {
		address		0x05d
		size		1
	}
	HA_274_BIOSCTRL	{
		address		0x05f
		size		1
		mask	BIOSMODE		0x30
		mask	BIOSDISABLED		0x30	
		bit	CHANNEL_B_PRIMARY	0x08
	}
	/*
	 * Per target SCSI offset values for Ultra2 controllers.
	 */
	TARG_OFFSET {
		address		0x070
		size		16
	}
}

const SCB_LIST_NULL	0xff

const CCSGADDR_MAX	0x80
const CCSGRAM_MAXSEGS	16

/* Offsets into the SCBID array where different data is stored */
const UNTAGGEDSCB_OFFSET	0
const QOUTFIFO_OFFSET		1
const QINFIFO_OFFSET		2

/* WDTR Message values */
const BUS_8_BIT			0x00
const BUS_16_BIT		0x01
const BUS_32_BIT		0x02

/* Offset maximums */
const MAX_OFFSET_8BIT		0x0f
const MAX_OFFSET_16BIT		0x08
const MAX_OFFSET_ULTRA2		0x7f
const HOST_MSG			0xff

/* Target mode command processing constants */
const CMD_GROUP_CODE_SHIFT	0x05
const CMD_GROUP0_BYTE_DELTA	-4
const CMD_GROUP2_BYTE_DELTA	-6
const CMD_GROUP4_BYTE_DELTA	4
const CMD_GROUP5_BYTE_DELTA	11

/*
 * Downloaded (kernel inserted) constants
 */

/*
 * Number of command descriptors in the command descriptor array.
 */
const TMODE_NUMCMDS	download