📄 drm.h
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* Block until buffer dispatched. * * \note The buffer may not yet have * been processed by the hardware -- * getting a hardware lock with the * hardware quiescent will ensure * that the buffer has been * processed. */ _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */ _DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */ /* Flags for DMA buffer request */ _DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */ _DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */ _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */} drm_dma_flags_t;/** * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type. * * \sa drmAddBufs(). */typedef struct drm_buf_desc { int count; /**< Number of buffers of this size */ int size; /**< Size in bytes */ int low_mark; /**< Low water mark */ int high_mark; /**< High water mark */ enum { _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */ _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */ _DRM_SG_BUFFER = 0x04, /**< Scatter/gather memory buffer */ _DRM_FB_BUFFER = 0x08 /**< Buffer is in frame buffer */ } flags; unsigned long agp_start; /**< * Start address of where the AGP buffers are * in the AGP aperture */} drm_buf_desc_t;/** * DRM_IOCTL_INFO_BUFS ioctl argument type. */typedef struct drm_buf_info { int count; /**< Entries in list */ drm_buf_desc_t __user *list;} drm_buf_info_t;/** * DRM_IOCTL_FREE_BUFS ioctl argument type. */typedef struct drm_buf_free { int count; int __user *list;} drm_buf_free_t;/** * Buffer information * * \sa drm_buf_map. */typedef struct drm_buf_pub { int idx; /**< Index into the master buffer list */ int total; /**< Buffer size */ int used; /**< Amount of buffer in use (for DMA) */ void __user *address; /**< Address of buffer */} drm_buf_pub_t;/** * DRM_IOCTL_MAP_BUFS ioctl argument type. */typedef struct drm_buf_map { int count; /**< Length of the buffer list */ void __user *virtual; /**< Mmap'd area in user-virtual */ drm_buf_pub_t __user *list; /**< Buffer information */} drm_buf_map_t;/** * DRM_IOCTL_DMA ioctl argument type. * * Indices here refer to the offset into the buffer list in drm_buf_get. * * \sa drmDMA(). */typedef struct drm_dma { int context; /**< Context handle */ int send_count; /**< Number of buffers to send */ int __user *send_indices; /**< List of handles to buffers */ int __user *send_sizes; /**< Lengths of data to send */ drm_dma_flags_t flags; /**< Flags */ int request_count; /**< Number of buffers requested */ int request_size; /**< Desired size for buffers */ int __user *request_indices; /**< Buffer information */ int __user *request_sizes; int granted_count; /**< Number of buffers granted */} drm_dma_t;typedef enum { _DRM_CONTEXT_PRESERVED = 0x01, _DRM_CONTEXT_2DONLY = 0x02} drm_ctx_flags_t;/** * DRM_IOCTL_ADD_CTX ioctl argument type. * * \sa drmCreateContext() and drmDestroyContext(). */typedef struct drm_ctx { drm_context_t handle; drm_ctx_flags_t flags;} drm_ctx_t;/** * DRM_IOCTL_RES_CTX ioctl argument type. */typedef struct drm_ctx_res { int count; drm_ctx_t __user *contexts;} drm_ctx_res_t;/** * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type. */typedef struct drm_draw { drm_drawable_t handle;} drm_draw_t;/** * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type. */typedef struct drm_auth { drm_magic_t magic;} drm_auth_t;/** * DRM_IOCTL_IRQ_BUSID ioctl argument type. * * \sa drmGetInterruptFromBusID(). */typedef struct drm_irq_busid { int irq; /**< IRQ number */ int busnum; /**< bus number */ int devnum; /**< device number */ int funcnum; /**< function number */} drm_irq_busid_t;typedef enum { _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */ _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */ _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking */} drm_vblank_seq_type_t;#define _DRM_VBLANK_FLAGS_MASK _DRM_VBLANK_SIGNALstruct drm_wait_vblank_request { drm_vblank_seq_type_t type; unsigned int sequence; unsigned long signal;};struct drm_wait_vblank_reply { drm_vblank_seq_type_t type; unsigned int sequence; long tval_sec; long tval_usec;};/** * DRM_IOCTL_WAIT_VBLANK ioctl argument type. * * \sa drmWaitVBlank(). */typedef union drm_wait_vblank { struct drm_wait_vblank_request request; struct drm_wait_vblank_reply reply;} drm_wait_vblank_t;/** * DRM_IOCTL_AGP_ENABLE ioctl argument type. * * \sa drmAgpEnable(). */typedef struct drm_agp_mode { unsigned long mode; /**< AGP mode */} drm_agp_mode_t;/** * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type. * * \sa drmAgpAlloc() and drmAgpFree(). */typedef struct drm_agp_buffer { unsigned long size; /**< In bytes -- will round to page boundary */ unsigned long handle; /**< Used for binding / unbinding */ unsigned long type; /**< Type of memory to allocate */ unsigned long physical; /**< Physical used by i810 */} drm_agp_buffer_t;/** * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type. * * \sa drmAgpBind() and drmAgpUnbind(). */typedef struct drm_agp_binding { unsigned long handle; /**< From drm_agp_buffer */ unsigned long offset; /**< In bytes -- will round to page boundary */} drm_agp_binding_t;/** * DRM_IOCTL_AGP_INFO ioctl argument type. * * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(), * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(), * drmAgpVendorId() and drmAgpDeviceId(). */typedef struct drm_agp_info { int agp_version_major; int agp_version_minor; unsigned long mode; unsigned long aperture_base; /* physical address */ unsigned long aperture_size; /* bytes */ unsigned long memory_allowed; /* bytes */ unsigned long memory_used; /* PCI information */ unsigned short id_vendor; unsigned short id_device;} drm_agp_info_t;/** * DRM_IOCTL_SG_ALLOC ioctl argument type. */typedef struct drm_scatter_gather { unsigned long size; /**< In bytes -- will round to page boundary */ unsigned long handle; /**< Used for mapping / unmapping */} drm_scatter_gather_t;/** * DRM_IOCTL_SET_VERSION ioctl argument type. */typedef struct drm_set_version { int drm_di_major; int drm_di_minor; int drm_dd_major; int drm_dd_minor;} drm_set_version_t;#define DRM_IOCTL_BASE 'd'#define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr)#define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type)#define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type)#define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type)#define DRM_IOCTL_VERSION DRM_IOWR(0x00, drm_version_t)#define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, drm_unique_t)#define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, drm_auth_t)#define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, drm_irq_busid_t)#define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, drm_map_t)#define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, drm_client_t)#define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, drm_stats_t)#define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, drm_set_version_t)#define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, drm_unique_t)#define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, drm_auth_t)#define DRM_IOCTL_BLOCK DRM_IOWR(0x12, drm_block_t)#define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, drm_block_t)#define DRM_IOCTL_CONTROL DRM_IOW( 0x14, drm_control_t)#define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, drm_map_t)#define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, drm_buf_desc_t)#define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, drm_buf_desc_t)#define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, drm_buf_info_t)#define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, drm_buf_map_t)#define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, drm_buf_free_t)#define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, drm_map_t)#define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, drm_ctx_priv_map_t)#define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, drm_ctx_priv_map_t)#define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, drm_ctx_t)#define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, drm_ctx_t)#define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, drm_ctx_t)#define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, drm_ctx_t)#define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, drm_ctx_t)#define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, drm_ctx_t)#define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, drm_ctx_res_t)#define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, drm_draw_t)#define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, drm_draw_t)#define DRM_IOCTL_DMA DRM_IOWR(0x29, drm_dma_t)#define DRM_IOCTL_LOCK DRM_IOW( 0x2a, drm_lock_t)#define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, drm_lock_t)#define DRM_IOCTL_FINISH DRM_IOW( 0x2c, drm_lock_t)#define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30)#define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31)#define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, drm_agp_mode_t)#define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, drm_agp_info_t)#define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, drm_agp_buffer_t)#define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, drm_agp_buffer_t)#define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, drm_agp_binding_t)#define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, drm_agp_binding_t)#define DRM_IOCTL_SG_ALLOC DRM_IOW( 0x38, drm_scatter_gather_t)#define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, drm_scatter_gather_t)#define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, drm_wait_vblank_t)/** * Device specific ioctls should only be in their respective headers * The device specific ioctl range is from 0x40 to 0x79. * * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and * drmCommandReadWrite(). */#define DRM_COMMAND_BASE 0x40#endif
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