radeon_cp.c

linux-2.6.15.6

	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
};

static u32 R300_cp_microcode[][2] = {
	{0x4200e000, 0000000000},
	{0x4000e000, 0000000000},
	{0x000000af, 0x00000008},
	{0x000000b3, 0x00000008},
	{0x6c5a504f, 0000000000},
	{0x4f4f497a, 0000000000},
	{0x5a578288, 0000000000},
	{0x4f91906a, 0000000000},
	{0x4f4f4f4f, 0000000000},
	{0x4fe24f44, 0000000000},
	{0x4f9c9c9c, 0000000000},
	{0xdc4f4fde, 0000000000},
	{0xa1cd4f4f, 0000000000},
	{0xd29d9d9d, 0000000000},
	{0x4f0f9fd7, 0000000000},
	{0x000ca000, 0x00000004},
	{0x000d0012, 0x00000038},
	{0x0000e8b4, 0x00000004},
	{0x000d0014, 0x00000038},
	{0x0000e8b6, 0x00000004},
	{0x000d0016, 0x00000038},
	{0x0000e854, 0x00000004},
	{0x000d0018, 0x00000038},
	{0x0000e855, 0x00000004},
	{0x000d001a, 0x00000038},
	{0x0000e856, 0x00000004},
	{0x000d001c, 0x00000038},
	{0x0000e857, 0x00000004},
	{0x000d001e, 0x00000038},
	{0x0000e824, 0x00000004},
	{0x000d0020, 0x00000038},
	{0x0000e825, 0x00000004},
	{0x000d0022, 0x00000038},
	{0x0000e830, 0x00000004},
	{0x000d0024, 0x00000038},
	{0x0000f0c0, 0x00000004},
	{0x000d0026, 0x00000038},
	{0x0000f0c1, 0x00000004},
	{0x000d0028, 0x00000038},
	{0x0000f041, 0x00000004},
	{0x000d002a, 0x00000038},
	{0x0000f184, 0x00000004},
	{0x000d002c, 0x00000038},
	{0x0000f185, 0x00000004},
	{0x000d002e, 0x00000038},
	{0x0000f186, 0x00000004},
	{0x000d0030, 0x00000038},
	{0x0000f187, 0x00000004},
	{0x000d0032, 0x00000038},
	{0x0000f180, 0x00000004},
	{0x000d0034, 0x00000038},
	{0x0000f393, 0x00000004},
	{0x000d0036, 0x00000038},
	{0x0000f38a, 0x00000004},
	{0x000d0038, 0x00000038},
	{0x0000f38e, 0x00000004},
	{0x0000e821, 0x00000004},
	{0x0140a000, 0x00000004},
	{0x00000043, 0x00000018},
	{0x00cce800, 0x00000004},
	{0x001b0001, 0x00000004},
	{0x08004800, 0x00000004},
	{0x001b0001, 0x00000004},
	{0x08004800, 0x00000004},
	{0x001b0001, 0x00000004},
	{0x08004800, 0x00000004},
	{0x0000003a, 0x00000008},
	{0x0000a000, 0000000000},
	{0x02c0a000, 0x00000004},
	{0x000ca000, 0x00000004},
	{0x00130000, 0x00000004},
	{0x000c2000, 0x00000004},
	{0xc980c045, 0x00000008},
	{0x2000451d, 0x00000004},
	{0x0000e580, 0x00000004},
	{0x000ce581, 0x00000004},
	{0x08004580, 0x00000004},
	{0x000ce581, 0x00000004},
	{0x0000004c, 0x00000008},
	{0x0000a000, 0000000000},
	{0x000c2000, 0x00000004},
	{0x0000e50e, 0x00000004},
	{0x00032000, 0x00000004},
	{0x00022056, 0x00000028},
	{0x00000056, 0x00000024},
	{0x0800450f, 0x00000004},
	{0x0000a050, 0x00000008},
	{0x0000e565, 0x00000004},
	{0x0000e566, 0x00000004},
	{0x00000057, 0x00000008},
	{0x03cca5b4, 0x00000004},
	{0x05432000, 0x00000004},
	{0x00022000, 0x00000004},
	{0x4ccce063, 0x00000030},
	{0x08274565, 0x00000004},
	{0x00000063, 0x00000030},
	{0x08004564, 0x00000004},
	{0x0000e566, 0x00000004},
	{0x0000005a, 0x00000008},
	{0x00802066, 0x00000010},
	{0x00202000, 0x00000004},
	{0x001b00ff, 0x00000004},
	{0x01000069, 0x00000010},
	{0x001f2000, 0x00000004},
	{0x001c00ff, 0x00000004},
	{0000000000, 0x0000000c},
	{0x00000085, 0x00000030},
	{0x0000005a, 0x00000008},
	{0x0000e576, 0x00000004},
	{0x000ca000, 0x00000004},
	{0x00012000, 0x00000004},
	{0x00082000, 0x00000004},
	{0x1800650e, 0x00000004},
	{0x00092000, 0x00000004},
	{0x000a2000, 0x00000004},
	{0x000f0000, 0x00000004},
	{0x00400000, 0x00000004},
	{0x00000079, 0x00000018},
	{0x0000e563, 0x00000004},
	{0x00c0e5f9, 0x000000c2},
	{0x0000006e, 0x00000008},
	{0x0000a06e, 0x00000008},
	{0x0000e576, 0x00000004},
	{0x0000e577, 0x00000004},
	{0x0000e50e, 0x00000004},
	{0x0000e50f, 0x00000004},
	{0x0140a000, 0x00000004},
	{0x0000007c, 0x00000018},
	{0x00c0e5f9, 0x000000c2},
	{0x0000007c, 0x00000008},
	{0x0014e50e, 0x00000004},
	{0x0040e50f, 0x00000004},
	{0x00c0007f, 0x00000008},
	{0x0000e570, 0x00000004},
	{0x0000e571, 0x00000004},
	{0x0000e572, 0x0000000c},
	{0x0000a000, 0x00000004},
	{0x0140a000, 0x00000004},
	{0x0000e568, 0x00000004},
	{0x000c2000, 0x00000004},
	{0x00000089, 0x00000018},
	{0x000b0000, 0x00000004},
	{0x18c0e562, 0x00000004},
	{0x0000008b, 0x00000008},
	{0x00c0008a, 0x00000008},
	{0x000700e4, 0x00000004},
	{0x00000097, 0x00000038},
	{0x000ca099, 0x00000030},
	{0x080045bb, 0x00000004},
	{0x000c209a, 0x00000030},
	{0x0800e5bc, 0000000000},
	{0x0000e5bb, 0x00000004},
	{0x0000e5bc, 0000000000},
	{0x00120000, 0x0000000c},
	{0x00120000, 0x00000004},
	{0x001b0002, 0x0000000c},
	{0x0000a000, 0x00000004},
	{0x0000e821, 0x00000004},
	{0x0000e800, 0000000000},
	{0x0000e821, 0x00000004},
	{0x0000e82e, 0000000000},
	{0x02cca000, 0x00000004},
	{0x00140000, 0x00000004},
	{0x000ce1cc, 0x00000004},
	{0x050de1cd, 0x00000004},
	{0x000000a7, 0x00000020},
	{0x4200e000, 0000000000},
	{0x000000ae, 0x00000038},
	{0x000ca000, 0x00000004},
	{0x00140000, 0x00000004},
	{0x000c2000, 0x00000004},
	{0x00160000, 0x00000004},
	{0x700ce000, 0x00000004},
	{0x001400aa, 0x00000008},
	{0x4000e000, 0000000000},
	{0x02400000, 0x00000004},
	{0x400ee000, 0x00000004},
	{0x02400000, 0x00000004},
	{0x4000e000, 0000000000},
	{0x000c2000, 0x00000004},
	{0x0240e51b, 0x00000004},
	{0x0080e50a, 0x00000005},
	{0x0080e50b, 0x00000005},
	{0x00220000, 0x00000004},
	{0x000700e4, 0x00000004},
	{0x000000c1, 0x00000038},
	{0x000c209a, 0x00000030},
	{0x0880e5bd, 0x00000005},
	{0x000c2099, 0x00000030},
	{0x0800e5bb, 0x00000005},
	{0x000c209a, 0x00000030},
	{0x0880e5bc, 0x00000005},
	{0x000000c4, 0x00000008},
	{0x0080e5bd, 0x00000005},
	{0x0000e5bb, 0x00000005},
	{0x0080e5bc, 0x00000005},
	{0x00210000, 0x00000004},
	{0x02800000, 0x00000004},
	{0x00c000c8, 0x00000018},
	{0x4180e000, 0x00000040},
	{0x000000ca, 0x00000024},
	{0x01000000, 0x0000000c},
	{0x0100e51d, 0x0000000c},
	{0x000045bb, 0x00000004},
	{0x000080c4, 0x00000008},
	{0x0000f3ce, 0x00000004},
	{0x0140a000, 0x00000004},
	{0x00cc2000, 0x00000004},
	{0x08c053cf, 0x00000040},
	{0x00008000, 0000000000},
	{0x0000f3d2, 0x00000004},
	{0x0140a000, 0x00000004},
	{0x00cc2000, 0x00000004},
	{0x08c053d3, 0x00000040},
	{0x00008000, 0000000000},
	{0x0000f39d, 0x00000004},
	{0x0140a000, 0x00000004},
	{0x00cc2000, 0x00000004},
	{0x08c0539e, 0x00000040},
	{0x00008000, 0000000000},
	{0x03c00830, 0x00000004},
	{0x4200e000, 0000000000},
	{0x0000a000, 0x00000004},
	{0x200045e0, 0x00000004},
	{0x0000e5e1, 0000000000},
	{0x00000001, 0000000000},
	{0x000700e1, 0x00000004},
	{0x0800e394, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
};

static int RADEON_READ_PLL(drm_device_t * dev, int addr)
{
	drm_radeon_private_t *dev_priv = dev->dev_private;

	RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
	return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
}

static int RADEON_READ_PCIE(drm_radeon_private_t * dev_priv, int addr)
{
	RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
	return RADEON_READ(RADEON_PCIE_DATA);
}

#if RADEON_FIFO_DEBUG
static void radeon_status(drm_radeon_private_t * dev_priv)
{
	printk("%s:\n", __FUNCTION__);
	printk("RBBM_STATUS = 0x%08x\n",
	       (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
	printk("CP_RB_RTPR = 0x%08x\n",
	       (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
	printk("CP_RB_WTPR = 0x%08x\n",
	       (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
	printk("AIC_CNTL = 0x%08x\n",
	       (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
	printk("AIC_STAT = 0x%08x\n",
	       (unsigned int)RADEON_READ(RADEON_AIC_STAT));
	printk("AIC_PT_BASE = 0x%08x\n",
	       (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
	printk("TLB_ADDR = 0x%08x\n",
	       (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
	printk("TLB_DATA = 0x%08x\n",
	       (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
}
#endif

/* ================================================================
 * Engine, FIFO control
 */

static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
{
	u32 tmp;
	int i;

	dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;

	tmp = RADEON_READ(RADEON_RB2D_DSTCACHE_CTLSTAT);
	tmp |= RADEON_RB2D_DC_FLUSH_ALL;
	RADEON_WRITE(RADEON_RB2D_DSTCACHE_CTLSTAT, tmp);

	for (i = 0; i < dev_priv->usec_timeout; i++) {
		if (!(RADEON_READ(RADEON_RB2D_DSTCACHE_CTLSTAT)
		      & RADEON_RB2D_DC_BUSY)) {
			return 0;
		}
		DRM_UDELAY(1);
	}

#if RADEON_FIFO_DEBUG
	DRM_ERROR("failed!\n");
	radeon_status(dev_priv);
#endif
	return DRM_ERR(EBUSY);
}

static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
{
	int i;

	dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;

	for (i = 0; i < dev_priv->usec_timeout; i++) {
		int slots = (RADEON_READ(RADEON_RBBM_STATUS)
			     & RADEON_RBBM_FIFOCNT_MASK);
		if (slots >= entries)
			return 0;
		DRM_UDELAY(1);
	}

#if RADEON_FIFO_DEBUG
	DRM_ERROR("failed!\n");
	radeon_status(dev_priv);
#endif
	return DRM_ERR(EBUSY);
}

static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
{
	int i, ret;

	dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;

	ret = radeon_do_wait_for_fifo(dev_priv, 64);
	if (ret)
		return ret;

	for (i = 0; i < dev_priv->usec_timeout; i++) {
		if (!(RADEON_READ(RADEON_RBBM_STATUS)
		      & RADEON_RBBM_ACTIVE)) {
			radeon_do_pixcache_flush(dev_priv);
			return 0;
		}
		DRM_UDELAY(1);
	}

#if RADEON_FIFO_DEBUG
	DRM_ERROR("failed!\n");
	radeon_status(dev_priv);
#endif
	return DRM_ERR(EBUSY);
}

/* ================================================================
 * CP control, initialization
 */

/* Load the microcode for the CP */
static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
{
	int i;
	DRM_DEBUG("\n");

	radeon_do_wait_for_idle(dev_priv);

	RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);

	if (dev_priv->microcode_version == UCODE_R200) {
		DRM_INFO("Loading R200 Microcode\n");
		for (i = 0; i < 256; i++) {
			RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
				     R200_cp_microcode[i][1]);
			RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
				     R200_cp_microcode[i][0]);
		}
	} else if (dev_priv->microcode_version == UCODE_R300) {
		DRM_INFO("Loading R300 Microcode\n");
		for (i = 0; i < 256; i++) {
			RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
				     R300_cp_microcode[i][1]);
			RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
				     R300_cp_microcode[i][0]);
		}
	} else {
		for (i = 0; i < 256; i++) {
			RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
				     radeon_cp_microcode[i][1]);
			RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
				     radeon_cp_microcode[i][0]);
		}
	}
}

/* Flush any pending commands to the CP.  This should only be used just
 * prior to a wait for idle, as it informs the engine that the command
 * stream is ending.
 */
static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
{
	DRM_DEBUG("\n");
#if 0
	u32 tmp;

	tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
	RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
#endif
}

/* Wait for the CP to go idle.
 */
int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
{
	RING_LOCALS;
	DRM_DEBUG("\n");

	BEGIN_RING(6);

	RADEON_PURGE_CACHE();
	RADEON_PURGE_ZCACHE();
	RADEON_WAIT_UNTIL_IDLE();

	ADVANCE_RING();
	COMMIT_RING();

	return radeon_do_wait_for_idle(dev_priv);
}

/* Start the Command Processor.
 */
static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
{
	RING_LOCALS;
	DRM_DEBUG("\n");

	radeon_do_wait_for_idle(dev_priv);

	RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);

	dev_priv->cp_running = 1;

	BEGIN_RING(6);

	RADEON_PURGE_CACHE();
	RADEON_PURGE_ZCACHE();
	RADEON_WAIT_UNTIL_IDLE();

	ADVANCE_RING();
	COMMIT_RING();
}

/* Reset the Command Processor.  This will not flush any pending
 * commands, so you must wait for the CP command stream to complete
 * before calling this routine.
 */
static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
{
	u32 cur_read_ptr;
	DRM_DEBUG("\n");

	cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
	RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
	SET_RING_HEAD(dev_priv, cur_read_ptr);
	dev_priv->ring.tail = cur_read_ptr;
}

/* Stop the Command Processor.  This will not flush any pending
 * commands, so you must flush the command stream and wait for the CP
 * to go idle before calling this routine.
 */
static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
{
	DRM_DEBUG("\n");

	RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);

	dev_priv->cp_running = 0;
}

/* Reset the engine.  This will stop the CP if it is running.
 */
static int radeon_do_engine_reset(drm_device_t * dev)
{
	drm_radeon_private_t *dev_priv = dev->dev_private;
	u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
	DRM_DEBUG("\n");

	radeon_do_pixcache_flush(dev_priv);

	clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
	mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);

	RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
					    RADEON_FORCEON_MCLKA |
					    RADEON_FORCEON_MCLKB |
					    RADEON_FORCEON_YCLKA |
					    RADEON_FORCEON_YCLKB |
					    RADEON_FORCEON_MC |
					    RADEON_FORCEON_AIC));

	rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);

	RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
					      RADEON_SOFT_RESET_CP |
					      RADEON_SOFT_RESET_HI |
					      RADEON_SOFT_RESET_SE |
					      RADEON_SOFT_RESET_RE |
					      RADEON_SOFT_RESET_PP |
					      RADEON_SOFT_RESET_E2 |
					      RADEON_SOFT_RESET_RB));