i2hw.h

linux-2.6.15.6

/*******************************************************************************
*
*   (c) 1999 by Computone Corporation
*
********************************************************************************
*
*
*   PACKAGE:     Linux tty Device Driver for IntelliPort II family of multiport
*                serial I/O controllers.
*
*   DESCRIPTION: Definitions limited to properties of the hardware or the
*                bootstrap firmware. As such, they are applicable regardless of
*                operating system or loadware (standard or diagnostic).
*
*******************************************************************************/
#ifndef I2HW_H
#define I2HW_H 1
//------------------------------------------------------------------------------
// Revision History:
//
// 23 September 1991 MAG   First Draft Started...through...
// 11 October 1991   ...   Continuing development...
//  6 August 1993          Added support for ISA-4 (asic) which is architected
//                         as an ISA-CEX with a single 4-port box.
//
// 20 December 1996  AKM   Version for Linux
//
//------------------------------------------------------------------------------
/*------------------------------------------------------------------------------

HARDWARE DESCRIPTION:

Introduction:

The IntelliPort-II and IntelliPort-IIEX products occupy a block of eight (8)
addresses in the host's I/O space.

Some addresses are used to transfer data to/from the board, some to transfer
so-called "mailbox" messages, and some to read bit-mapped status information.
While all the products in the line are functionally similar, some use a 16-bit
data path to transfer data while others use an 8-bit path. Also, the use of
command /status/mailbox registers differs slightly between the II and IIEX
branches of the family.

The host determines what type of board it is dealing with by reading a string of
sixteen characters from the board. These characters are always placed in the
fifo by the board's local processor whenever the board is reset (either from
power-on or under software control) and are known as the "Power-on Reset
Message." In order that this message can be read from either type of board, the
hardware registers used in reading this message are the same. Once this message
has been read by the host, then it has the information required to operate.

General Differences between boards:

The greatest structural difference is between the -II and -IIEX families of
product. The -II boards use the Am4701 dual 512x8 bidirectional fifo to support
the data path, mailbox registers, and status registers. This chip contains some
features which are not used in the IntelliPort-II products; a description of
these is omitted here. Because of these many features, it contains many
registers, too many to access directly within a small address space. They are
accessed by first writing a value to a "pointer" register. This value selects
the register to be accessed.  The next read or write to that address accesses
the selected register rather than the pointer register.

The -IIEX boards use a proprietary design similar to the Am4701 in function. But
because of a simpler, more streamlined design it doesn't require so many
registers. This means they can be accessed directly in single operations rather
than through a pointer register.

Besides these differences, there are differences in whether 8-bit or 16-bit
transfers are used to move data to the board.

The -II boards are capable only of 8-bit data transfers, while the -IIEX boards
may be configured for either 8-bit or 16-bit data transfers. If the on-board DIP
switch #8 is ON, and the card has been installed in a 16-bit slot, 16-bit
transfers are supported (and will be expected by the standard loadware). The
on-board firmware can determine the position of the switch, and whether the
board is installed in a 16-bit slot; it supplies this information to the host as
part of the power-up reset message.

The configuration switch (#8) and slot selection do not directly configure the
hardware. It is up to the on-board loadware and host-based drivers to act
according to the selected options. That is, loadware and drivers could be
written to perform 8-bit transfers regardless of the state of the DIP switch or
slot (and in a diagnostic environment might well do so). Likewise, 16-bit
transfers could be performed as long as the card is in a 16-bit slot.

Note the slot selection and DIP switch selection are provided separately: a
board running in 8-bit mode in a 16-bit slot has a greater range of possible
interrupts to choose from; information of potential use to the host.

All 8-bit data transfers are done in the same way, regardless of whether on a
-II board or a -IIEX board.

The host must consider two things then: 1) whether a -II or -IIEX product is
being used, and 2) whether an 8-bit or 16-bit data path is used.

A further difference is that -II boards always have a 512-byte fifo operating in
each direction. -IIEX boards may use fifos of varying size; this size is
reported as part of the power-up message.

I/O Map Of IntelliPort-II and IntelliPort-IIEX boards:
(Relative to the chosen base address)

Addr  R/W      IntelliPort-II    IntelliPort-IIEX
----  ---      --------------    ----------------
0     R/W      Data Port (byte)  Data Port (byte or word)
1     R/W      (Not used)        (MSB of word-wide data written to Data Port)
2     R        Status Register   Status Register
2     W        Pointer Register  Interrupt Mask Register
3     R/W      (Not used)        Mailbox Registers (6 bits: 11111100)
4,5   --       Reserved for future products
6     --       Reserved for future products
7     R        Guaranteed to have no effect
7     W        Hardware reset of board.


Rules:
All data transfers are performed using the even i/o address. If byte-wide data
transfers are being used, do INB/OUTB operations on the data port. If word-wide
transfers are used, do INW/OUTW operations. In some circumstances (such as
reading the power-up message) you will do INB from the data port, but in this
case the MSB of each word read is lost. When accessing all other unreserved
registers, use byte operations only.
------------------------------------------------------------------------------*/

//------------------------------------------------
// Mandatory Includes:
//------------------------------------------------
//
#include "ip2types.h"
#include "i2os.h"    /* For any o.s., compiler, or host-related issues */

//-------------------------------------------------------------------------
// Manifests for the I/O map:
//-------------------------------------------------------------------------
// R/W: Data port (byte) for IntelliPort-II,
// R/W: Data port (byte or word) for IntelliPort-IIEX
// Incoming or outgoing data passes through a FIFO, the status of which is
// available in some of the bits in FIFO_STATUS. This (bidirectional) FIFO is
// the primary means of transferring data, commands, flow-control, and status
// information between the host and board.
//
#define FIFO_DATA 0

// Another way of passing information between the board and the host is
// through "mailboxes". Unlike a FIFO, a mailbox holds only a single byte of
// data.  Writing data to the mailbox causes a status bit to be set, and
// potentially interrupting the intended receiver. The sender has some way to
// determine whether the data has been read yet; as soon as it has, it may send
// more. The mailboxes are handled differently on -II and -IIEX products, as
// suggested below.
//------------------------------------------------------------------------------
// Read: Status Register for IntelliPort-II or -IIEX
// The presence of any bit set here will cause an interrupt to the host,
// provided the corresponding bit has been unmasked in the interrupt mask
// register. Furthermore, interrupts to the host are disabled globally until the
// loadware selects the irq line to use. With the exception of STN_MR, the bits
// remain set so long as the associated condition is true.
//
#define FIFO_STATUS 2

// Bit map of status bits which are identical for -II and -IIEX
//
#define ST_OUT_FULL  0x40  // Outbound FIFO full
#define ST_IN_EMPTY  0x20  // Inbound FIFO empty
#define ST_IN_MAIL   0x04  // Inbound Mailbox full

// The following exists only on the Intelliport-IIEX, and indicates that the
// board has not read the last outgoing mailbox data yet. In the IntelliPort-II,
// the outgoing mailbox may be read back: a zero indicates the board has read
// the data.
//
#define STE_OUT_MAIL 0x80  // Outbound mailbox full (!)

// The following bits are defined differently for -II and -IIEX boards. Code
// which relies on these bits will need to be functionally different for the two
// types of boards and should be generally avoided because of the additional
// complexity this creates:

// Bit map of status bits only on -II

// Fifo has been RESET (cleared when the status register is read). Note that
// this condition cannot be masked and would always interrupt the host, except
// that the hardware reset also disables interrupts globally from the board
// until re-enabled by loadware. This could also arise from the
// Am4701-supported command to reset the chip, but this command is generally not
// used here.
//
#define STN_MR       0x80

// See the AMD Am4701 data sheet for details on the following four bits. They
// are not presently used by Computone drivers.
//
#define STN_OUT_AF  0x10  // Outbound FIFO almost full (programmable)
#define STN_IN_AE   0x08  // Inbound FIFO almost empty (programmable)
#define STN_BD      0x02  // Inbound byte detected
#define STN_PE      0x01  // Parity/Framing condition detected

// Bit-map of status bits only on -IIEX
//
#define STE_OUT_HF  0x10  // Outbound FIFO half full
#define STE_IN_HF   0x08  // Inbound FIFO half full
#define STE_IN_FULL 0x02  // Inbound FIFO full
#define STE_OUT_MT  0x01  // Outbound FIFO empty

//------------------------------------------------------------------------------

// Intelliport-II -- Write Only: the pointer register.
// Values are written to this register to select the Am4701 internal register to
// be accessed on the next operation.
//
#define FIFO_PTR    0x02

// Values for the pointer register
//
#define SEL_COMMAND 0x1    // Selects the Am4701 command register

// Some possible commands:
//
#define SEL_CMD_MR  0x80	// Am4701 command to reset the chip
#define SEL_CMD_SH  0x40	// Am4701 command to map the "other" port into the
							// status register.
#define SEL_CMD_UNSH   0	// Am4701 command to "unshift": port maps into its
							// own status register.
#define SEL_MASK     0x2	// Selects the Am4701 interrupt mask register. The
							// interrupt mask register is bit-mapped to match 
							// the status register (FIFO_STATUS) except for
							// STN_MR. (See above.)
#define SEL_BYTE_DET 0x3	// Selects the Am4701 byte-detect register. (Not
							// normally used except in diagnostics.)
#define SEL_OUTMAIL  0x4	// Selects the outbound mailbox (R/W). Reading back
							// a value of zero indicates that the mailbox has
							// been read by the board and is available for more
							// data./ Writing to the mailbox optionally
							// interrupts the board, depending on the loadware's
							// setting of its interrupt mask register.
#define SEL_AEAF     0x5	// Selects AE/AF threshold register.
#define SEL_INMAIL   0x6	// Selects the inbound mailbox (Read)

//------------------------------------------------------------------------------
// IntelliPort-IIEX --  Write Only: interrupt mask (and misc flags) register:
// Unlike IntelliPort-II, bit assignments do NOT match those of the status
// register.
//
#define FIFO_MASK    0x2

// Mailbox readback select:
// If set, reads to FIFO_MAIL will read the OUTBOUND mailbox (host to board). If
// clear (default on reset) reads to FIFO_MAIL will read the INBOUND mailbox.
// This is the normal situation. The clearing of a mailbox is determined on
// -IIEX boards by waiting for the STE_OUT_MAIL bit to clear. Readback
// capability is provided for diagnostic purposes only.
//
#define  MX_OUTMAIL_RSEL   0x80

#define  MX_IN_MAIL  0x40	// Enables interrupts when incoming mailbox goes
							// full (ST_IN_MAIL set).
#define  MX_IN_FULL  0x20	// Enables interrupts when incoming FIFO goes full
							// (STE_IN_FULL).
#define  MX_IN_MT    0x08	// Enables interrupts when incoming FIFO goes empty
							// (ST_IN_MT).
#define  MX_OUT_FULL 0x04	// Enables interrupts when outgoing FIFO goes full
							// (ST_OUT_FULL).
#define  MX_OUT_MT   0x01	// Enables interrupts when outgoing FIFO goes empty
							// (STE_OUT_MT).

// Any remaining bits are reserved, and should be written to ZERO for
// compatibility with future Computone products.

//------------------------------------------------------------------------------
// IntelliPort-IIEX: -- These are only 6-bit mailboxes !!! -- 11111100 (low two
// bits always read back 0).
// Read:  One of the mailboxes, usually Inbound.
//        Inbound Mailbox (MX_OUTMAIL_RSEL = 0)
//        Outbound Mailbox (MX_OUTMAIL_RSEL = 1)
// Write: Outbound Mailbox
// For the IntelliPort-II boards, the outbound mailbox is read back to determine
// whether the board has read the data (0 --> data has been read). For the
// IntelliPort-IIEX, this is done by reading a status register. To determine
// whether mailbox is available for more outbound data, use the STE_OUT_MAIL bit
// in FIFO_STATUS. Moreover, although the Outbound Mailbox can be read back by
// setting MX_OUTMAIL_RSEL, it is NOT cleared when the board reads it, as is the
// case with the -II boards. For this reason, FIFO_MAIL is normally used to read
// the inbound FIFO, and MX_OUTMAIL_RSEL kept clear. (See above for
// MX_OUTMAIL_RSEL description.)
//
#define  FIFO_MAIL   0x3

//------------------------------------------------------------------------------
// WRITE ONLY:  Resets the board. (Data doesn't matter).
//
#define  FIFO_RESET  0x7

//------------------------------------------------------------------------------
// READ ONLY:  Will have no effect. (Data is undefined.)
// Actually, there will be an effect, in that the operation is sure to generate
// a bus cycle: viz., an I/O byte Read. This fact can be used to enforce short
// delays when no comparable time constant is available.
//
#define  FIFO_NOP    0x7

//------------------------------------------------------------------------------
// RESET & POWER-ON RESET MESSAGE
/*------------------------------------------------------------------------------
RESET:

The IntelliPort-II and -IIEX boards are reset in three ways: Power-up, channel
reset, and via a write to the reset register described above. For products using
the ISA bus, these three sources of reset are equvalent. For MCA and EISA buses,
the Power-up and channel reset sources cause additional hardware initialization
which should only occur at system startup time.

The third type of reset, called a "command reset", is done by writing any data
to the FIFO_RESET address described above. This resets the on-board processor,
FIFO, UARTS, and associated hardware.

This passes control of the board to the bootstrap firmware, which performs a
Power-On Self Test and which detects its current configuration. For example,
-IIEX products determine the size of FIFO which has been installed, and the
number and type of expansion boxes attached.

This and other information is then written to the FIFO in a 16-byte data block
to be read by the host. This block is guaranteed to be present within two (2)
seconds of having received the command reset. The firmware is now ready to