📄 mpi_cnfg.h
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U32 Reserved5; /* 10h */ U32 Reserved6; /* 14h */ U32 Reserved7; /* 18h */ U32 Reserved8; /* 1Ch */ U32 Reserved9; /* 20h */ U32 Reserved10; /* 24h */ U32 Reserved11; /* 28h */ U32 Reserved12; /* 2Ch */ U32 Reserved13; /* 30h */ U32 Reserved14; /* 34h */ U32 Reserved15; /* 38h */ U32 Reserved16; /* 3Ch */ U32 Reserved17; /* 40h */} MPI_BOOT_DEVICE_ADAPTER_ORDER, MPI_POINTER PTR_MPI_BOOT_DEVICE_ADAPTER_ORDER;typedef struct _MPI_BOOT_DEVICE_ADAPTER_NUMBER{ U8 TargetID; /* 00h */ U8 Bus; /* 01h */ U8 AdapterNumber; /* 02h */ U8 Reserved1; /* 03h */ U32 Reserved2; /* 04h */ U32 Reserved3; /* 08h */ U32 Reserved4; /* 0Ch */ U8 LUN[8]; /* 10h */ U32 Reserved5; /* 18h */ U32 Reserved6; /* 1Ch */ U32 Reserved7; /* 20h */ U32 Reserved8; /* 24h */ U32 Reserved9; /* 28h */ U32 Reserved10; /* 2Ch */ U32 Reserved11; /* 30h */ U32 Reserved12; /* 34h */ U32 Reserved13; /* 38h */ U32 Reserved14; /* 3Ch */ U32 Reserved15; /* 40h */} MPI_BOOT_DEVICE_ADAPTER_NUMBER, MPI_POINTER PTR_MPI_BOOT_DEVICE_ADAPTER_NUMBER;typedef struct _MPI_BOOT_DEVICE_PCI_ADDRESS{ U8 TargetID; /* 00h */ U8 Bus; /* 01h */ U16 PCIAddress; /* 02h */ U32 Reserved1; /* 04h */ U32 Reserved2; /* 08h */ U32 Reserved3; /* 0Ch */ U8 LUN[8]; /* 10h */ U32 Reserved4; /* 18h */ U32 Reserved5; /* 1Ch */ U32 Reserved6; /* 20h */ U32 Reserved7; /* 24h */ U32 Reserved8; /* 28h */ U32 Reserved9; /* 2Ch */ U32 Reserved10; /* 30h */ U32 Reserved11; /* 34h */ U32 Reserved12; /* 38h */ U32 Reserved13; /* 3Ch */ U32 Reserved14; /* 40h */} MPI_BOOT_DEVICE_PCI_ADDRESS, MPI_POINTER PTR_MPI_BOOT_DEVICE_PCI_ADDRESS;typedef struct _MPI_BOOT_DEVICE_SLOT_NUMBER{ U8 TargetID; /* 00h */ U8 Bus; /* 01h */ U8 PCISlotNumber; /* 02h */ U8 Reserved1; /* 03h */ U32 Reserved2; /* 04h */ U32 Reserved3; /* 08h */ U32 Reserved4; /* 0Ch */ U8 LUN[8]; /* 10h */ U32 Reserved5; /* 18h */ U32 Reserved6; /* 1Ch */ U32 Reserved7; /* 20h */ U32 Reserved8; /* 24h */ U32 Reserved9; /* 28h */ U32 Reserved10; /* 2Ch */ U32 Reserved11; /* 30h */ U32 Reserved12; /* 34h */ U32 Reserved13; /* 38h */ U32 Reserved14; /* 3Ch */ U32 Reserved15; /* 40h */} MPI_BOOT_DEVICE_PCI_SLOT_NUMBER, MPI_POINTER PTR_MPI_BOOT_DEVICE_PCI_SLOT_NUMBER;typedef struct _MPI_BOOT_DEVICE_FC_WWN{ U64 WWPN; /* 00h */ U32 Reserved1; /* 08h */ U32 Reserved2; /* 0Ch */ U8 LUN[8]; /* 10h */ U32 Reserved3; /* 18h */ U32 Reserved4; /* 1Ch */ U32 Reserved5; /* 20h */ U32 Reserved6; /* 24h */ U32 Reserved7; /* 28h */ U32 Reserved8; /* 2Ch */ U32 Reserved9; /* 30h */ U32 Reserved10; /* 34h */ U32 Reserved11; /* 38h */ U32 Reserved12; /* 3Ch */ U32 Reserved13; /* 40h */} MPI_BOOT_DEVICE_FC_WWN, MPI_POINTER PTR_MPI_BOOT_DEVICE_FC_WWN;typedef struct _MPI_BOOT_DEVICE_SAS_WWN{ U64 SASAddress; /* 00h */ U32 Reserved1; /* 08h */ U32 Reserved2; /* 0Ch */ U8 LUN[8]; /* 10h */ U32 Reserved3; /* 18h */ U32 Reserved4; /* 1Ch */ U32 Reserved5; /* 20h */ U32 Reserved6; /* 24h */ U32 Reserved7; /* 28h */ U32 Reserved8; /* 2Ch */ U32 Reserved9; /* 30h */ U32 Reserved10; /* 34h */ U32 Reserved11; /* 38h */ U32 Reserved12; /* 3Ch */ U32 Reserved13; /* 40h */} MPI_BOOT_DEVICE_SAS_WWN, MPI_POINTER PTR_MPI_BOOT_DEVICE_SAS_WWN;typedef struct _MPI_BOOT_DEVICE_ENCLOSURE_SLOT{ U64 EnclosureLogicalID; /* 00h */ U32 Reserved1; /* 08h */ U32 Reserved2; /* 0Ch */ U8 LUN[8]; /* 10h */ U16 SlotNumber; /* 18h */ U16 Reserved3; /* 1Ah */ U32 Reserved4; /* 1Ch */ U32 Reserved5; /* 20h */ U32 Reserved6; /* 24h */ U32 Reserved7; /* 28h */ U32 Reserved8; /* 2Ch */ U32 Reserved9; /* 30h */ U32 Reserved10; /* 34h */ U32 Reserved11; /* 38h */ U32 Reserved12; /* 3Ch */ U32 Reserved13; /* 40h */} MPI_BOOT_DEVICE_ENCLOSURE_SLOT, MPI_POINTER PTR_MPI_BOOT_DEVICE_ENCLOSURE_SLOT;typedef union _MPI_BIOSPAGE2_BOOT_DEVICE{ MPI_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder; MPI_BOOT_DEVICE_ADAPTER_NUMBER AdapterNumber; MPI_BOOT_DEVICE_PCI_ADDRESS PCIAddress; MPI_BOOT_DEVICE_PCI_SLOT_NUMBER PCISlotNumber; MPI_BOOT_DEVICE_FC_WWN FcWwn; MPI_BOOT_DEVICE_SAS_WWN SasWwn; MPI_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot;} MPI_BIOSPAGE2_BOOT_DEVICE, MPI_POINTER PTR_MPI_BIOSPAGE2_BOOT_DEVICE;typedef struct _CONFIG_PAGE_BIOS_2{ CONFIG_PAGE_HEADER Header; /* 00h */ U32 Reserved1; /* 04h */ U32 Reserved2; /* 08h */ U32 Reserved3; /* 0Ch */ U32 Reserved4; /* 10h */ U32 Reserved5; /* 14h */ U32 Reserved6; /* 18h */ U8 BootDeviceForm; /* 1Ch */ U8 Reserved7; /* 1Dh */ U16 Reserved8; /* 1Eh */ MPI_BIOSPAGE2_BOOT_DEVICE BootDevice; /* 20h */} CONFIG_PAGE_BIOS_2, MPI_POINTER PTR_CONFIG_PAGE_BIOS_2, BIOSPage2_t, MPI_POINTER pBIOSPage2_t;#define MPI_BIOSPAGE2_PAGEVERSION (0x01)#define MPI_BIOSPAGE2_FORM_MASK (0x0F)#define MPI_BIOSPAGE2_FORM_ADAPTER_ORDER (0x00)#define MPI_BIOSPAGE2_FORM_ADAPTER_NUMBER (0x01)#define MPI_BIOSPAGE2_FORM_PCI_ADDRESS (0x02)#define MPI_BIOSPAGE2_FORM_PCI_SLOT_NUMBER (0x03)#define MPI_BIOSPAGE2_FORM_FC_WWN (0x04)#define MPI_BIOSPAGE2_FORM_SAS_WWN (0x05)#define MPI_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06)/***************************************************************************** SCSI Port Config Pages****************************************************************************/typedef struct _CONFIG_PAGE_SCSI_PORT_0{ CONFIG_PAGE_HEADER Header; /* 00h */ U32 Capabilities; /* 04h */ U32 PhysicalInterface; /* 08h */} CONFIG_PAGE_SCSI_PORT_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_0, SCSIPortPage0_t, MPI_POINTER pSCSIPortPage0_t;#define MPI_SCSIPORTPAGE0_PAGEVERSION (0x02)#define MPI_SCSIPORTPAGE0_CAP_IU (0x00000001)#define MPI_SCSIPORTPAGE0_CAP_DT (0x00000002)#define MPI_SCSIPORTPAGE0_CAP_QAS (0x00000004)#define MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK (0x0000FF00)#define MPI_SCSIPORTPAGE0_SYNC_ASYNC (0x00)#define MPI_SCSIPORTPAGE0_SYNC_5 (0x32)#define MPI_SCSIPORTPAGE0_SYNC_10 (0x19)#define MPI_SCSIPORTPAGE0_SYNC_20 (0x0C)#define MPI_SCSIPORTPAGE0_SYNC_33_33 (0x0B)#define MPI_SCSIPORTPAGE0_SYNC_40 (0x0A)#define MPI_SCSIPORTPAGE0_SYNC_80 (0x09)#define MPI_SCSIPORTPAGE0_SYNC_160 (0x08)#define MPI_SCSIPORTPAGE0_SYNC_UNKNOWN (0xFF)#define MPI_SCSIPORTPAGE0_CAP_SHIFT_MIN_SYNC_PERIOD (8)#define MPI_SCSIPORTPAGE0_CAP_GET_MIN_SYNC_PERIOD(Cap) \ ( ((Cap) & MPI_SCSIPORTPAGE0_CAP_MASK_MIN_SYNC_PERIOD) \ >> MPI_SCSIPORTPAGE0_CAP_SHIFT_MIN_SYNC_PERIOD \ )#define MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK (0x00FF0000)#define MPI_SCSIPORTPAGE0_CAP_SHIFT_MAX_SYNC_OFFSET (16)#define MPI_SCSIPORTPAGE0_CAP_GET_MAX_SYNC_OFFSET(Cap) \ ( ((Cap) & MPI_SCSIPORTPAGE0_CAP_MASK_MAX_SYNC_OFFSET) \ >> MPI_SCSIPORTPAGE0_CAP_SHIFT_MAX_SYNC_OFFSET \ )#define MPI_SCSIPORTPAGE0_CAP_IDP (0x08000000)#define MPI_SCSIPORTPAGE0_CAP_WIDE (0x20000000)#define MPI_SCSIPORTPAGE0_CAP_AIP (0x80000000)#define MPI_SCSIPORTPAGE0_PHY_SIGNAL_TYPE_MASK (0x00000003)#define MPI_SCSIPORTPAGE0_PHY_SIGNAL_HVD (0x01)#define MPI_SCSIPORTPAGE0_PHY_SIGNAL_SE (0x02)#define MPI_SCSIPORTPAGE0_PHY_SIGNAL_LVD (0x03)#define MPI_SCSIPORTPAGE0_PHY_MASK_CONNECTED_ID (0xFF000000)#define MPI_SCSIPORTPAGE0_PHY_SHIFT_CONNECTED_ID (24)#define MPI_SCSIPORTPAGE0_PHY_BUS_FREE_CONNECTED_ID (0xFE)#define MPI_SCSIPORTPAGE0_PHY_UNKNOWN_CONNECTED_ID (0xFF)typedef struct _CONFIG_PAGE_SCSI_PORT_1{ CONFIG_PAGE_HEADER Header; /* 00h */ U32 Configuration; /* 04h */ U32 OnBusTimerValue; /* 08h */ U8 TargetConfig; /* 0Ch */ U8 Reserved1; /* 0Dh */ U16 IDConfig; /* 0Eh */} CONFIG_PAGE_SCSI_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_1, SCSIPortPage1_t, MPI_POINTER pSCSIPortPage1_t;#define MPI_SCSIPORTPAGE1_PAGEVERSION (0x03)/* Configuration values */#define MPI_SCSIPORTPAGE1_CFG_PORT_SCSI_ID_MASK (0x000000FF)#define MPI_SCSIPORTPAGE1_CFG_PORT_RESPONSE_ID_MASK (0xFFFF0000)#define MPI_SCSIPORTPAGE1_CFG_SHIFT_PORT_RESPONSE_ID (16)/* TargetConfig values */#define MPI_SCSIPORTPAGE1_TARGCONFIG_TARG_ONLY (0x⌨️ 快捷键说明
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