shpchp_hpc.c

linux-2.6.15.6

{
	struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
	u32 slot_reg;
	u16 slot_status, sec_bus_status;
	u8 m66_cap, pcix_cap, pi;
	int retval = 0;

	DBG_ENTER_ROUTINE 

	if (!slot->ctrl->hpc_ctlr_handle) {
		err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
		return -1;
	}

	if (slot->hp_slot >= php_ctlr->num_slots) {
		err("%s: Invalid HPC slot number!\n", __FUNCTION__);
		return -1;
	}
	
	pi = readb(php_ctlr->creg + PROG_INTERFACE);
	slot_reg = readl(php_ctlr->creg + SLOT1 + 4*(slot->hp_slot));
	dbg("%s: pi = %d, slot_reg = %x\n", __FUNCTION__, pi, slot_reg);
	slot_status = (u16) slot_reg;
	dbg("%s: slot_status = %x\n", __FUNCTION__, slot_status);
	sec_bus_status = readw(php_ctlr->creg + SEC_BUS_CONFIG);

	pcix_cap = (u8) ((slot_status & 0x3000) >> 12);
	dbg("%s:  pcix_cap = %x\n", __FUNCTION__, pcix_cap);
	m66_cap = (u8) ((slot_status & 0x0200) >> 9);
	dbg("%s:  m66_cap = %x\n", __FUNCTION__, m66_cap);


	if (pi == 2) {
		switch (pcix_cap) {
		case 0:
			*value = m66_cap ? PCI_SPEED_66MHz : PCI_SPEED_33MHz;
			break;
		case 1:
			*value = PCI_SPEED_66MHz_PCIX;
			break;
		case 3:
			*value = PCI_SPEED_133MHz_PCIX;
			break;
		case 4:
			*value = PCI_SPEED_133MHz_PCIX_266;	
			break;
		case 5:
			*value = PCI_SPEED_133MHz_PCIX_533;	
			break;
		case 2:	/* Reserved */
		default:
			*value = PCI_SPEED_UNKNOWN;
			retval = -ENODEV;
			break;
		}
	} else {
		switch (pcix_cap) {
		case 0:
			*value = m66_cap ? PCI_SPEED_66MHz : PCI_SPEED_33MHz;
			break;
		case 1:
			*value = PCI_SPEED_66MHz_PCIX;
			break;
		case 3:
			*value = PCI_SPEED_133MHz_PCIX;	
			break;
		case 2:	/* Reserved */
		default:
			*value = PCI_SPEED_UNKNOWN;
			retval = -ENODEV;
			break;
		}
	}

	dbg("Adapter speed = %d\n", *value);
	
	DBG_LEAVE_ROUTINE 
	return retval;
}

static int hpc_get_mode1_ECC_cap(struct slot *slot, u8 *mode)
{
	struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
	u16 sec_bus_status;
	u8 pi;
	int retval = 0;

	DBG_ENTER_ROUTINE 

	if (!slot->ctrl->hpc_ctlr_handle) {
		err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
		return -1;
	}

	pi = readb(php_ctlr->creg + PROG_INTERFACE);
	sec_bus_status = readw(php_ctlr->creg + SEC_BUS_CONFIG);

	if (pi == 2) {
		*mode = (sec_bus_status & 0x0100) >> 7;
	} else {
		retval = -1;
	}

	dbg("Mode 1 ECC cap = %d\n", *mode);
	
	DBG_LEAVE_ROUTINE 
	return retval;
}

static int hpc_query_power_fault(struct slot * slot)
{
	struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
	u32 slot_reg;
	u16 slot_status;
	u8 pwr_fault_state, status;

	DBG_ENTER_ROUTINE 

	if (!slot->ctrl->hpc_ctlr_handle) {
		err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
		return -1;
	}

	slot_reg = readl(php_ctlr->creg + SLOT1 + 4*(slot->hp_slot));
	slot_status = (u16) slot_reg;
	pwr_fault_state = (slot_status & 0x0040) >> 7;
	status = (pwr_fault_state == 1) ? 0 : 1;

	DBG_LEAVE_ROUTINE
	/* Note: Logic 0 => fault */
	return status;
}

static int hpc_set_attention_status(struct slot *slot, u8 value)
{
	struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
	u8 slot_cmd = 0;
	int rc = 0;

	if (!slot->ctrl->hpc_ctlr_handle) {
		err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
		return -1;
	}

	if (slot->hp_slot >= php_ctlr->num_slots) {
		err("%s: Invalid HPC slot number!\n", __FUNCTION__);
		return -1;
	}

	switch (value) {
		case 0 :	
			slot_cmd = 0x30;	/* OFF */
			break;
		case 1:
			slot_cmd = 0x10;	/* ON */
			break;
		case 2:
			slot_cmd = 0x20;	/* BLINK */
			break;
		default:
			return -1;
	}

	shpc_write_cmd(slot, slot->hp_slot, slot_cmd);
	
	return rc;
}


static void hpc_set_green_led_on(struct slot *slot)
{
	struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
	u8 slot_cmd;

	if (!slot->ctrl->hpc_ctlr_handle) {
		err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
		return ;
	}

	if (slot->hp_slot >= php_ctlr->num_slots) {
		err("%s: Invalid HPC slot number!\n", __FUNCTION__);
		return ;
	}

	slot_cmd = 0x04;

	shpc_write_cmd(slot, slot->hp_slot, slot_cmd);

	return;
}

static void hpc_set_green_led_off(struct slot *slot)
{
	struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
	u8 slot_cmd;

	if (!slot->ctrl->hpc_ctlr_handle) {
		err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
		return ;
	}

	if (slot->hp_slot >= php_ctlr->num_slots) {
		err("%s: Invalid HPC slot number!\n", __FUNCTION__);
		return ;
	}

	slot_cmd = 0x0C;

	shpc_write_cmd(slot, slot->hp_slot, slot_cmd);

	return;
}

static void hpc_set_green_led_blink(struct slot *slot)
{
	struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
	u8 slot_cmd;

	if (!slot->ctrl->hpc_ctlr_handle) {
		err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
		return ;
	}

	if (slot->hp_slot >= php_ctlr->num_slots) {
		err("%s: Invalid HPC slot number!\n", __FUNCTION__);
		return ;
	}

	slot_cmd = 0x08;

	shpc_write_cmd(slot, slot->hp_slot, slot_cmd);

	return;
}

int shpc_get_ctlr_slot_config(struct controller *ctrl,
	int *num_ctlr_slots,	/* number of slots in this HPC			*/
	int *first_device_num,	/* PCI dev num of the first slot in this SHPC	*/
	int *physical_slot_num,	/* phy slot num of the first slot in this SHPC	*/
	int *updown,		/* physical_slot_num increament: 1 or -1	*/
	int *flags)
{
	struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle;

	DBG_ENTER_ROUTINE 

	if (!ctrl->hpc_ctlr_handle) {
		err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
		return -1;
	}

	*first_device_num = php_ctlr->slot_device_offset;	/* Obtained in shpc_init() */
	*num_ctlr_slots = php_ctlr->num_slots;			/* Obtained in shpc_init() */

	*physical_slot_num = (readl(php_ctlr->creg + SLOT_CONFIG) & PSN) >> 16;
	dbg("%s: physical_slot_num = %x\n", __FUNCTION__, *physical_slot_num);
	*updown = ((readl(php_ctlr->creg + SLOT_CONFIG) & UPDOWN ) >> 29) ? 1 : -1;	

	DBG_LEAVE_ROUTINE 
	return 0;
}

static void hpc_release_ctlr(struct controller *ctrl)
{
	struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle;
	struct php_ctlr_state_s *p, *p_prev;

	DBG_ENTER_ROUTINE 

	if (!ctrl->hpc_ctlr_handle) {
		err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
		return ;
	}

	if (shpchp_poll_mode) {
	    del_timer(&php_ctlr->int_poll_timer);
	} else {	
		if (php_ctlr->irq) {
			free_irq(php_ctlr->irq, ctrl);
			php_ctlr->irq = 0;
			pci_disable_msi(php_ctlr->pci_dev);
		}
	}
	if (php_ctlr->pci_dev) {
		iounmap(php_ctlr->creg);
		release_mem_region(pci_resource_start(php_ctlr->pci_dev, 0), pci_resource_len(php_ctlr->pci_dev, 0));
		php_ctlr->pci_dev = NULL;
	}

	spin_lock(&list_lock);
	p = php_ctlr_list_head;
	p_prev = NULL;
	while (p) {
		if (p == php_ctlr) {
			if (p_prev)
				p_prev->pnext = p->pnext;
			else
				php_ctlr_list_head = p->pnext;
			break;
		} else {
			p_prev = p;
			p = p->pnext;
		}
	}
	spin_unlock(&list_lock);

	kfree(php_ctlr);

DBG_LEAVE_ROUTINE
			  
}

static int hpc_power_on_slot(struct slot * slot)
{
	struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
	u8 slot_cmd;
	int retval = 0;

	DBG_ENTER_ROUTINE 

	if (!slot->ctrl->hpc_ctlr_handle) {
		err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
		return -1;
	}

	if (slot->hp_slot >= php_ctlr->num_slots) {
		err("%s: Invalid HPC slot number!\n", __FUNCTION__);
		return -1;
	}
	slot_cmd = 0x01;

	retval = shpc_write_cmd(slot, slot->hp_slot, slot_cmd);

	if (retval) {
		err("%s: Write command failed!\n", __FUNCTION__);
		return -1;
	}

	DBG_LEAVE_ROUTINE

	return retval;
}

static int hpc_slot_enable(struct slot * slot)
{
	struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
	u8 slot_cmd;
	int retval = 0;

	DBG_ENTER_ROUTINE 

	if (!slot->ctrl->hpc_ctlr_handle) {
		err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
		return -1;
	}

	if (slot->hp_slot >= php_ctlr->num_slots) {
		err("%s: Invalid HPC slot number!\n", __FUNCTION__);
		return -1;
	}
	/* 3A => Slot - Enable, Power Indicator - Blink, Attention Indicator - Off */
	slot_cmd = 0x3A;  

	retval = shpc_write_cmd(slot, slot->hp_slot, slot_cmd);

	if (retval) {
		err("%s: Write command failed!\n", __FUNCTION__);
		return -1;
	}

	DBG_LEAVE_ROUTINE
	return retval;
}

static int hpc_slot_disable(struct slot * slot)
{
	struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
	u8 slot_cmd;
	int retval = 0;

	DBG_ENTER_ROUTINE 

	if (!slot->ctrl->hpc_ctlr_handle) {
		err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
		return -1;
	}

	if (slot->hp_slot >= php_ctlr->num_slots) {
		err("%s: Invalid HPC slot number!\n", __FUNCTION__);
		return -1;
	}

	/* 1F => Slot - Disable, Power Indicator - Off, Attention Indicator - On */
	slot_cmd = 0x1F;

	retval = shpc_write_cmd(slot, slot->hp_slot, slot_cmd);

	if (retval) {
		err("%s: Write command failed!\n", __FUNCTION__);
		return -1;
	}

	DBG_LEAVE_ROUTINE
	return retval;
}

static int hpc_set_bus_speed_mode(struct slot * slot, enum pci_bus_speed value)
{
	u8 slot_cmd;
	u8 pi;
	int retval = 0;
	struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;

	DBG_ENTER_ROUTINE 
	
	if (!slot->ctrl->hpc_ctlr_handle) {
		err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
		return -1;
	}

	pi = readb(php_ctlr->creg + PROG_INTERFACE);
	
	if (pi == 1) {
		switch (value) {
		case 0:
			slot_cmd = SETA_PCI_33MHZ;
			break;
		case 1:
			slot_cmd = SETA_PCI_66MHZ;
			break;
		case 2:
			slot_cmd = SETA_PCIX_66MHZ;
			break;
		case 3:
			slot_cmd = SETA_PCIX_100MHZ;	
			break;
		case 4:
			slot_cmd = SETA_PCIX_133MHZ;	
			break;
		default:
			slot_cmd = PCI_SPEED_UNKNOWN;
			retval = -ENODEV;
			return retval;	
		}
	} else {
		switch (value) {
		case 0:
			slot_cmd = SETB_PCI_33MHZ;
			break;
		case 1:
			slot_cmd = SETB_PCI_66MHZ;
			break;
		case 2:
			slot_cmd = SETB_PCIX_66MHZ_PM;
			break;
		case 3:
			slot_cmd = SETB_PCIX_100MHZ_PM;	
			break;
		case 4:
			slot_cmd = SETB_PCIX_133MHZ_PM;	
			break;
		case 5:
			slot_cmd = SETB_PCIX_66MHZ_EM;	
			break;
		case 6:
			slot_cmd = SETB_PCIX_100MHZ_EM;	
			break;
		case 7:
			slot_cmd = SETB_PCIX_133MHZ_EM;	
			break;
		case 8:
			slot_cmd = SETB_PCIX_66MHZ_266;	
			break;
		case 0x9:
			slot_cmd = SETB_PCIX_100MHZ_266;	
			break;
		case 0xa:
			slot_cmd = SETB_PCIX_133MHZ_266;	
			break;
		case 0xb:
			slot_cmd = SETB_PCIX_66MHZ_533;	
			break;
		case 0xc:
			slot_cmd = SETB_PCIX_100MHZ_533;	
			break;
		case 0xd:
			slot_cmd = SETB_PCIX_133MHZ_533;	
			break;
		default:
			slot_cmd = PCI_SPEED_UNKNOWN;
			retval = -ENODEV;
			return retval;	
		}

	}
	retval = shpc_write_cmd(slot, 0, slot_cmd);
	if (retval) {
		err("%s: Write command failed!\n", __FUNCTION__);
		return -1;
	}

	DBG_LEAVE_ROUTINE
	return retval;
}

static irqreturn_t shpc_isr(int IRQ, void *dev_id, struct pt_regs *regs)
{
	struct controller *ctrl = NULL;