cx88-reg.h

linux-2.6.15.6

#define AUD_IIR3_1_SEL           0x3201c8
#define AUD_IIR3_1_SHIFT         0x3201cc
#define AUD_IIR3_2_SEL           0x3201d0
#define AUD_IIR3_2_SHIFT         0x3201d4
#define AUD_IIR4_0_SEL           0x3201e0
#define AUD_IIR4_0_SHIFT         0x3201e4
#define AUD_IIR4_1_SEL           0x3201e8
#define AUD_IIR4_1_SHIFT         0x3201ec
#define AUD_IIR4_2_SEL           0x3201f0
#define AUD_IIR4_2_SHIFT         0x3201f4
#define AUD_IIR4_0_CA0           0x320200
#define AUD_IIR4_0_CA1           0x320204
#define AUD_IIR4_0_CA2           0x320208
#define AUD_IIR4_0_CB0           0x32020c
#define AUD_IIR4_0_CB1           0x320210
#define AUD_IIR4_1_CA0           0x320214
#define AUD_IIR4_1_CA1           0x320218
#define AUD_IIR4_1_CA2           0x32021c
#define AUD_IIR4_1_CB0           0x320220
#define AUD_IIR4_1_CB1           0x320224
#define AUD_IIR4_2_CA0           0x320228
#define AUD_IIR4_2_CA1           0x32022c
#define AUD_IIR4_2_CA2           0x320230
#define AUD_IIR4_2_CB0           0x320234
#define AUD_IIR4_2_CB1           0x320238
#define AUD_HP_MD_IIR4_1         0x320250
#define AUD_HP_PROG_IIR4_1       0x320254
#define AUD_FM_MODE_ENABLE       0x320258
#define AUD_POLY0_DDS_CONSTANT   0x320270
#define AUD_DN0_FREQ             0x320274
#define AUD_DN1_FREQ             0x320278
#define AUD_DN1_FREQ_SHIFT       0x32027c
#define AUD_DN1_AFC              0x320280
#define AUD_DN1_SRC_SEL          0x320284
#define AUD_DN1_SHFT             0x320288
#define AUD_DN2_FREQ             0x32028c
#define AUD_DN2_FREQ_SHIFT       0x320290
#define AUD_DN2_AFC              0x320294
#define AUD_DN2_SRC_SEL          0x320298
#define AUD_DN2_SHFT             0x32029c
#define AUD_CRDC0_SRC_SEL        0x320300
#define AUD_CRDC0_SHIFT          0x320304
#define AUD_CORDIC_SHIFT_0       0x320308
#define AUD_CRDC1_SRC_SEL        0x32030c
#define AUD_CRDC1_SHIFT          0x320310
#define AUD_CORDIC_SHIFT_1       0x320314
#define AUD_DCOC_0_SRC           0x320320
#define AUD_DCOC0_SHIFT          0x320324
#define AUD_DCOC_0_SHIFT_IN0     0x320328
#define AUD_DCOC_0_SHIFT_IN1     0x32032c
#define AUD_DCOC_1_SRC           0x320330
#define AUD_DCOC1_SHIFT          0x320334
#define AUD_DCOC_1_SHIFT_IN0     0x320338
#define AUD_DCOC_1_SHIFT_IN1     0x32033c
#define AUD_DCOC_2_SRC           0x320340
#define AUD_DCOC2_SHIFT          0x320344
#define AUD_DCOC_2_SHIFT_IN0     0x320348
#define AUD_DCOC_2_SHIFT_IN1     0x32034c
#define AUD_DCOC_PASS_IN         0x320350
#define AUD_PDET_SRC             0x320370
#define AUD_PDET_SHIFT           0x320374
#define AUD_PILOT_BQD_1_K0       0x320380
#define AUD_PILOT_BQD_1_K1       0x320384
#define AUD_PILOT_BQD_1_K2       0x320388
#define AUD_PILOT_BQD_1_K3       0x32038c
#define AUD_PILOT_BQD_1_K4       0x320390
#define AUD_PILOT_BQD_2_K0       0x320394
#define AUD_PILOT_BQD_2_K1       0x320398
#define AUD_PILOT_BQD_2_K2       0x32039c
#define AUD_PILOT_BQD_2_K3       0x3203a0
#define AUD_PILOT_BQD_2_K4       0x3203a4
#define AUD_THR_FR               0x3203c0
#define AUD_X_PROG               0x3203c4
#define AUD_Y_PROG               0x3203c8
#define AUD_HARMONIC_MULT        0x3203cc
#define AUD_C1_UP_THR            0x3203d0
#define AUD_C1_LO_THR            0x3203d4
#define AUD_C2_UP_THR            0x3203d8
#define AUD_C2_LO_THR            0x3203dc
#define AUD_PLL_EN               0x320400
#define AUD_PLL_SRC              0x320404
#define AUD_PLL_SHIFT            0x320408
#define AUD_PLL_IF_SEL           0x32040c
#define AUD_PLL_IF_SHIFT         0x320410
#define AUD_BIQUAD_PLL_K0        0x320414
#define AUD_BIQUAD_PLL_K1        0x320418
#define AUD_BIQUAD_PLL_K2        0x32041c
#define AUD_BIQUAD_PLL_K3        0x320420
#define AUD_BIQUAD_PLL_K4        0x320424
#define AUD_DEEMPH0_SRC_SEL      0x320440
#define AUD_DEEMPH0_SHIFT        0x320444
#define AUD_DEEMPH0_G0           0x320448
#define AUD_DEEMPH0_A0           0x32044c
#define AUD_DEEMPH0_B0           0x320450
#define AUD_DEEMPH0_A1           0x320454
#define AUD_DEEMPH0_B1           0x320458
#define AUD_DEEMPH1_SRC_SEL      0x32045c
#define AUD_DEEMPH1_SHIFT        0x320460
#define AUD_DEEMPH1_G0           0x320464
#define AUD_DEEMPH1_A0           0x320468
#define AUD_DEEMPH1_B0           0x32046c
#define AUD_DEEMPH1_A1           0x320470
#define AUD_DEEMPH1_B1           0x320474
#define AUD_OUT0_SEL             0x320490
#define AUD_OUT0_SHIFT           0x320494
#define AUD_OUT1_SEL             0x320498
#define AUD_OUT1_SHIFT           0x32049c
#define AUD_RDSI_SEL             0x3204a0
#define AUD_RDSI_SHIFT           0x3204a4
#define AUD_RDSQ_SEL             0x3204a8
#define AUD_RDSQ_SHIFT           0x3204ac
#define AUD_DBX_IN_GAIN          0x320500
#define AUD_DBX_WBE_GAIN         0x320504
#define AUD_DBX_SE_GAIN          0x320508
#define AUD_DBX_RMS_WBE          0x32050c
#define AUD_DBX_RMS_SE           0x320510
#define AUD_DBX_SE_BYPASS        0x320514
#define AUD_FAWDETCTL            0x320530
#define AUD_FAWDETWINCTL         0x320534
#define AUD_DEEMPHGAIN_R         0x320538
#define AUD_DEEMPHNUMER1_R       0x32053c
#define AUD_DEEMPHNUMER2_R       0x320540
#define AUD_DEEMPHDENOM1_R       0x320544
#define AUD_DEEMPHDENOM2_R       0x320548
#define AUD_ERRLOGPERIOD_R       0x32054c
#define AUD_ERRINTRPTTHSHLD1_R   0x320550
#define AUD_ERRINTRPTTHSHLD2_R   0x320554
#define AUD_ERRINTRPTTHSHLD3_R   0x320558
#define AUD_NICAM_STATUS1        0x32055c
#define AUD_NICAM_STATUS2        0x320560
#define AUD_ERRLOG1              0x320564
#define AUD_ERRLOG2              0x320568
#define AUD_ERRLOG3              0x32056c
#define AUD_DAC_BYPASS_L         0x320580
#define AUD_DAC_BYPASS_R         0x320584
#define AUD_DAC_BYPASS_CTL       0x320588
#define AUD_CTL                  0x32058c
#define AUD_STATUS               0x320590
#define AUD_VOL_CTL              0x320594
#define AUD_BAL_CTL              0x320598
#define AUD_START_TIMER          0x3205b0
#define AUD_MODE_CHG_TIMER       0x3205b4
#define AUD_POLYPH80SCALEFAC     0x3205b8
#define AUD_DMD_RA_DDS           0x3205bc
#define AUD_I2S_RA_DDS           0x3205c0
#define AUD_RATE_THRES_DMD       0x3205d0
#define AUD_RATE_THRES_I2S       0x3205d4
#define AUD_RATE_ADJ1            0x3205d8
#define AUD_RATE_ADJ2            0x3205dc
#define AUD_RATE_ADJ3            0x3205e0
#define AUD_RATE_ADJ4            0x3205e4
#define AUD_RATE_ADJ5            0x3205e8
#define AUD_APB_IN_RATE_ADJ      0x3205ec
#define AUD_I2SCNTL              0x3205ec
#define AUD_PHASE_FIX_CTL        0x3205f0
#define AUD_PLL_PRESCALE         0x320600
#define AUD_PLL_DDS              0x320604
#define AUD_PLL_INT              0x320608
#define AUD_PLL_FRAC             0x32060c
#define AUD_PLL_JTAG             0x320620
#define AUD_PLL_SPMP             0x320624
#define AUD_AFE_12DB_EN          0x320628

// Audio QAM Register Addresses
#define AUD_PDF_DDS_CNST_BYTE2   0x320d01
#define AUD_PDF_DDS_CNST_BYTE1   0x320d02
#define AUD_PDF_DDS_CNST_BYTE0   0x320d03
#define AUD_PHACC_FREQ_8MSB      0x320d2a
#define AUD_PHACC_FREQ_8LSB      0x320d2b
#define AUD_QAM_MODE             0x320d04


/* ---------------------------------------------------------------------- */
/* transport stream registers                                             */

#define MO_TS_DMA           0x330000 // {64}RWp Transport stream downstream
#define MO_TS_GPCNT         0x33C020 // {16}RO TS general purpose counter
#define MO_TS_GPCNTRL       0x33C030 // {2}WO TS general purpose control
#define MO_TS_DMACNTRL      0x33C040 // {6}RW TS DMA control
#define MO_TS_XFR_STAT      0x33C044 // {1}RO TS transfer status
#define MO_TS_LNGTH         0x33C048 // {12}RW TS line length

#define TS_HW_SOP_CNTRL     0x33C04C
#define TS_GEN_CNTRL        0x33C050
#define TS_BD_PKT_STAT      0x33C054
#define TS_SOP_STAT         0x33C058
#define TS_FIFO_OVFL_STAT   0x33C05C
#define TS_VALERR_CNTRL     0x33C060


/* ---------------------------------------------------------------------- */
/* VIP registers                                                          */

#define MO_VIPD_DMA         0x340000 // {64}RWp VIP downstream
#define MO_VIPU_DMA         0x340008 // {64}RWp VIP upstream
#define MO_VIPD_GPCNT       0x34C020 // {16}RO VIP down general purpose counter
#define MO_VIPU_GPCNT       0x34C024 // {16}RO VIP up general purpose counter
#define MO_VIPD_GPCNTRL     0x34C030 // {2}WO VIP down general purpose control
#define MO_VIPU_GPCNTRL     0x34C034 // {2}WO VIP up general purpose control
#define MO_VIP_DMACNTRL     0x34C040 // {6}RW VIP DMA control
#define MO_VIP_XFR_STAT     0x34C044 // {1}RO VIP transfer status
#define MO_VIP_CFG          0x340048 // VIP configuration
#define MO_VIPU_CNTRL       0x34004C // VIP upstream control #1
#define MO_VIPD_CNTRL       0x340050 // VIP downstream control #2
#define MO_VIPD_LNGTH       0x340054 // VIP downstream line length
#define MO_VIP_BRSTLN       0x340058 // VIP burst length
#define MO_VIP_INTCNTRL     0x34C05C // VIP Interrupt Control
#define MO_VIP_XFTERM       0x340060 // VIP transfer terminate


/* ---------------------------------------------------------------------- */
/* misc registers                                                         */

#define MO_M2M_DMA          0x350000 // {64}RWp Mem2Mem DMA Bfr
#define MO_GP0_IO           0x350010 // {32}RW* GPIOoutput enablesdata I/O
#define MO_GP1_IO           0x350014 // {32}RW* GPIOoutput enablesdata I/O
#define MO_GP2_IO           0x350018 // {32}RW* GPIOoutput enablesdata I/O
#define MO_GP3_IO           0x35001C // {32}RW* GPIO Mode/Ctrloutput enables
#define MO_GPIO             0x350020 // {32}RW* GPIO I2C Ctrldata I/O
#define MO_GPOE             0x350024 // {32}RW  GPIO I2C Ctrloutput enables
#define MO_GP_ISM           0x350028 // {16}WO  GPIO Intr Sens/Pol

#define MO_PLL_B            0x35C008 // {32}RW* PLL Control for ASB bus clks
#define MO_M2M_CNT          0x35C024 // {32}RW  Mem2Mem DMA Cnt
#define MO_M2M_XSUM         0x35C028 // {32}RO  M2M XOR-Checksum
#define MO_CRC              0x35C02C // {16}RW  CRC16 init/result
#define MO_CRC_D            0x35C030 // {32}WO  CRC16 new data in
#define MO_TM_CNT_LDW       0x35C034 // {32}RO  Timer : Counter low dword
#define MO_TM_CNT_UW        0x35C038 // {16}RO  Timer : Counter high word
#define MO_TM_LMT_LDW       0x35C03C // {32}RW  Timer : Limit low dword
#define MO_TM_LMT_UW        0x35C040 // {32}RW  Timer : Limit high word
#define MO_PINMUX_IO        0x35C044 // {8}RW  Pin Mux Control
#define MO_TSTSEL_IO        0x35C048 // {2}RW  Pin Mux Control
#define MO_AFECFG_IO        0x35C04C // AFE configuration reg
#define MO_DDS_IO           0x35C050 // DDS Increment reg
#define MO_DDSCFG_IO        0x35C054 // DDS Configuration reg
#define MO_SAMPLE_IO        0x35C058 // IRIn sample reg
#define MO_SRST_IO          0x35C05C // Output system reset reg

#define MO_INT1_MSK         0x35C060 // DMA RISC interrupt mask
#define MO_INT1_STAT        0x35C064 // DMA RISC interrupt status
#define MO_INT1_MSTAT       0x35C068 // DMA RISC interrupt masked status


/* ---------------------------------------------------------------------- */
/* i2c bus registers                                                      */

#define MO_I2C              0x368000 // I2C data/control
#define MO_I2C_DIV          (0xf<<4)
#define MO_I2C_SYNC         (1<<3)
#define MO_I2C_W3B          (1<<2)
#define MO_I2C_SCL          (1<<1)
#define MO_I2C_SDA          (1<<0)


/* ---------------------------------------------------------------------- */
/* general purpose host registers                                         */
/* FIXME: tyops?  s/0x35/0x38/ ??                                         */

#define MO_GPHSTD_DMA       0x350000 // {64}RWp Host downstream
#define MO_GPHSTU_DMA       0x350008 // {64}RWp Host upstream
#define MO_GPHSTU_CNTRL     0x380048 // Host upstream control #1
#define MO_GPHSTD_CNTRL     0x38004C // Host downstream control #2
#define MO_GPHSTD_LNGTH     0x380050 // Host downstream line length
#define MO_GPHST_WSC        0x380054 // Host wait state control
#define MO_GPHST_XFR        0x380058 // Host transfer control
#define MO_GPHST_WDTH       0x38005C // Host interface width
#define MO_GPHST_HDSHK      0x380060 // Host peripheral handshake