mpc10x_common.c

linux-2.6.15.6

/*
 * arch/ppc/syslib/mpc10x_common.c
 *
 * Common routines for the Motorola SPS MPC106, MPC107 and MPC8240 Host bridge,
 * Mem ctlr, EPIC, etc.
 *
 * Author: Mark A. Greer
 *         [e-mail]
 *
 * 2001 (c) MontaVista, Software, Inc.  This file is licensed under
 * the terms of the GNU General Public License version 2.  This program
 * is licensed "as is" without any warranty of any kind, whether express
 * or implied.
 */

/*
 * *** WARNING - A BAT MUST be set to access the PCI config addr/data regs ***
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/serial_8250.h>
#include <linux/fsl_devices.h>
#include <linux/device.h>

#include <asm/byteorder.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/uaccess.h>
#include <asm/machdep.h>
#include <asm/pci-bridge.h>
#include <asm/open_pic.h>
#include <asm/mpc10x.h>
#include <asm/ppc_sys.h>

#ifdef CONFIG_MPC10X_OPENPIC
#ifdef CONFIG_EPIC_SERIAL_MODE
#define EPIC_IRQ_BASE (epic_serial_mode ? 16 : 5)
#else
#define EPIC_IRQ_BASE 5
#endif
#define MPC10X_I2C_IRQ (EPIC_IRQ_BASE + NUM_8259_INTERRUPTS)
#define MPC10X_DMA0_IRQ (EPIC_IRQ_BASE + 1 + NUM_8259_INTERRUPTS)
#define MPC10X_DMA1_IRQ (EPIC_IRQ_BASE + 2 + NUM_8259_INTERRUPTS)
#define MPC10X_UART0_IRQ (EPIC_IRQ_BASE + 4 + NUM_8259_INTERRUPTS)
#define MPC10X_UART1_IRQ (EPIC_IRQ_BASE + 5 + NUM_8259_INTERRUPTS)
#else
#define MPC10X_I2C_IRQ -1
#define MPC10X_DMA0_IRQ -1
#define MPC10X_DMA1_IRQ -1
#define MPC10X_UART0_IRQ -1
#define MPC10X_UART1_IRQ -1
#endif

static struct fsl_i2c_platform_data mpc10x_i2c_pdata = {
	.device_flags		= 0,
};

static struct plat_serial8250_port serial_plat_uart0[] = {
	[0] = {
		.mapbase	= 0x4500,
		.iotype		= UPIO_MEM,
		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
	},
	{ },
};
static struct plat_serial8250_port serial_plat_uart1[] = {
	[0] = {
		.mapbase	= 0x4600,
		.iotype		= UPIO_MEM,
		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
	},
	{ },
};

struct platform_device ppc_sys_platform_devices[] = {
	[MPC10X_IIC1] = {
		.name 	= "fsl-i2c",
		.id	= 1,
		.dev.platform_data = &mpc10x_i2c_pdata,
		.num_resources = 2,
		.resource = (struct resource[]) {
			{
				.start 	= MPC10X_EUMB_I2C_OFFSET,
				.end	= MPC10X_EUMB_I2C_OFFSET +
		                            MPC10X_EUMB_I2C_SIZE - 1,
				.flags	= IORESOURCE_MEM,
			},
			{
				.flags 	= IORESOURCE_IRQ
			},
		},
	},
	[MPC10X_DMA0] = {
		.name	= "fsl-dma",
		.id	= 0,
		.num_resources = 2,
		.resource = (struct resource[]) {
			{
				.start 	= MPC10X_EUMB_DMA_OFFSET + 0x10,
				.end	= MPC10X_EUMB_DMA_OFFSET + 0x1f,
				.flags	= IORESOURCE_MEM,
			},
			{
				.flags	= IORESOURCE_IRQ,
			},
		},
	},
	[MPC10X_DMA1] = {
		.name	= "fsl-dma",
		.id	= 1,
		.num_resources = 2,
		.resource = (struct resource[]) {
			{
				.start	= MPC10X_EUMB_DMA_OFFSET + 0x20,
				.end	= MPC10X_EUMB_DMA_OFFSET + 0x2f,
				.flags	= IORESOURCE_MEM,
			},
			{
				.flags	= IORESOURCE_IRQ,
			},
		},
	},
	[MPC10X_DMA1] = {
		.name	= "fsl-dma",
		.id	= 1,
		.num_resources = 2,
		.resource = (struct resource[]) {
			{
				.start	= MPC10X_EUMB_DMA_OFFSET + 0x20,
				.end	= MPC10X_EUMB_DMA_OFFSET + 0x2f,
				.flags	= IORESOURCE_MEM,
			},
			{
				.flags	= IORESOURCE_IRQ,
			},
		},
	},
	[MPC10X_UART0] = {
		.name = "serial8250",
		.id	= PLAT8250_DEV_PLATFORM,
		.dev.platform_data = serial_plat_uart0,
	},
	[MPC10X_UART1] = {
		.name = "serial8250",
		.id	= PLAT8250_DEV_PLATFORM1,
		.dev.platform_data = serial_plat_uart1,
	},

};

/* We use the PCI ID to match on */
struct ppc_sys_spec *cur_ppc_sys_spec;
struct ppc_sys_spec ppc_sys_specs[] = {
	{
		.ppc_sys_name 	= "8245",
		.mask		= 0xFFFFFFFF,
		.value		= MPC10X_BRIDGE_8245,
		.num_devices	= 5,
		.device_list	= (enum ppc_sys_devices[])
		{
			MPC10X_IIC1, MPC10X_DMA0, MPC10X_DMA1, MPC10X_UART0, MPC10X_UART1,
		},
	},
	{
		.ppc_sys_name 	= "8240",
		.mask		= 0xFFFFFFFF,
		.value		= MPC10X_BRIDGE_8240,
		.num_devices	= 3,
		.device_list	= (enum ppc_sys_devices[])
		{
			MPC10X_IIC1, MPC10X_DMA0, MPC10X_DMA1,
		},
	},
	{
		.ppc_sys_name	= "107",
		.mask		= 0xFFFFFFFF,
		.value		= MPC10X_BRIDGE_107,
		.num_devices	= 3,
		.device_list	= (enum ppc_sys_devices[])
		{
			MPC10X_IIC1, MPC10X_DMA0, MPC10X_DMA1,
		},
	},
	{       /* default match */
		.ppc_sys_name   = "",
		.mask           = 0x00000000,
		.value          = 0x00000000,
	},
};

/*
 * mach_mpc10x_fixup: This function enables DUART mode if it detects
 * if it detects two UARTS in the platform device entries.
 */
static int __init mach_mpc10x_fixup(struct platform_device *pdev)
{
	if (strncmp (pdev->name, "serial8250", 10) == 0 && pdev->id == 1)
		writeb(readb(serial_plat_uart1[0].membase + 0x11) | 0x1,
				serial_plat_uart1[0].membase + 0x11);
	return 0;
}

static int __init mach_mpc10x_init(void)
{
	ppc_sys_device_fixup = mach_mpc10x_fixup;
	return 0;
}
postcore_initcall(mach_mpc10x_init);

/* Set resources to match bridge memory map */
void __init
mpc10x_bridge_set_resources(int map, struct pci_controller *hose)
{

	switch (map) {
		case MPC10X_MEM_MAP_A:
			pci_init_resource(&hose->io_resource,
					0x00000000,
					0x3f7fffff,
					IORESOURCE_IO,
					"PCI host bridge");

			pci_init_resource (&hose->mem_resources[0],
					0xc0000000,
					0xfeffffff,
					IORESOURCE_MEM,
					"PCI host bridge");
			break;
		case MPC10X_MEM_MAP_B:
			pci_init_resource(&hose->io_resource,
					0x00000000,
					0x00bfffff,
					IORESOURCE_IO,
					"PCI host bridge");

			pci_init_resource (&hose->mem_resources[0],
					0x80000000,
					0xfcffffff,
					IORESOURCE_MEM,
					"PCI host bridge");
			break;
		default:
			printk("mpc10x_bridge_set_resources: "
					"Invalid map specified\n");
			if (ppc_md.progress)
				ppc_md.progress("mpc10x:exit1", 0x100);
	}
}

/*
 * Do some initialization and put the EUMB registers at the specified address
 * (also map the EPIC registers into virtual space--OpenPIC_Addr will be set).
 *
 * The EPIC is not on the 106, only the 8240 and 107.
 */
int __init
mpc10x_bridge_init(struct pci_controller *hose,
		   uint current_map,
		   uint new_map,
		   uint phys_eumb_base)
{
	int	host_bridge, picr1, picr1_bit, i;
	ulong	pci_config_addr, pci_config_data;
	u_char	pir, byte;

	if (ppc_md.progress) ppc_md.progress("mpc10x:enter", 0x100);

	/* Set up for current map so we can get at config regs */
	switch (current_map) {
		case MPC10X_MEM_MAP_A:
			setup_indirect_pci(hose,
					   MPC10X_MAPA_CNFG_ADDR,
					   MPC10X_MAPA_CNFG_DATA);
			break;
		case MPC10X_MEM_MAP_B:
			setup_indirect_pci(hose,
					   MPC10X_MAPB_CNFG_ADDR,
					   MPC10X_MAPB_CNFG_DATA);
			break;
		default:
			printk("mpc10x_bridge_init: %s\n",
				"Invalid current map specified");
			if (ppc_md.progress)
				ppc_md.progress("mpc10x:exit1", 0x100);
			return -1;
	}

	/* Make sure it's a supported bridge */
	early_read_config_dword(hose,
			        0,
			        PCI_DEVFN(0,0),
			        PCI_VENDOR_ID,
			        &host_bridge);

	switch (host_bridge) {
		case MPC10X_BRIDGE_106:
		case MPC10X_BRIDGE_8240:
		case MPC10X_BRIDGE_107:
		case MPC10X_BRIDGE_8245:
			break;
		default:
			if (ppc_md.progress)
				ppc_md.progress("mpc10x:exit2", 0x100);
			return -1;
	}

	switch (new_map) {
		case MPC10X_MEM_MAP_A:
			MPC10X_SETUP_HOSE(hose, A);
			pci_config_addr = MPC10X_MAPA_CNFG_ADDR;
			pci_config_data = MPC10X_MAPA_CNFG_DATA;
			picr1_bit = MPC10X_CFG_PICR1_ADDR_MAP_A;
			break;
		case MPC10X_MEM_MAP_B:
			MPC10X_SETUP_HOSE(hose, B);
			pci_config_addr = MPC10X_MAPB_CNFG_ADDR;
			pci_config_data = MPC10X_MAPB_CNFG_DATA;
			picr1_bit = MPC10X_CFG_PICR1_ADDR_MAP_B;
			break;
		default:
			printk("mpc10x_bridge_init: %s\n",
				"Invalid new map specified");
			if (ppc_md.progress)
				ppc_md.progress("mpc10x:exit3", 0x100);
			return -1;
	}