mv64x60.c

linux-2.6.15.6

/*
 * arch/ppc/syslib/mv64x60.c
 *
 * Common routines for the Marvell/Galileo Discovery line of host bridges
 * (gt64260, mv64360, mv64460, ...).
 *
 * Author: Mark A. Greer <[e-mail]>
 *
 * 2004 (c) MontaVista, Software, Inc.  This file is licensed under
 * the terms of the GNU General Public License version 2.  This program
 * is licensed "as is" without any warranty of any kind, whether express
 * or implied.
 */
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/spinlock.h>
#include <linux/mv643xx.h>
#include <linux/platform_device.h>

#include <asm/byteorder.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/uaccess.h>
#include <asm/machdep.h>
#include <asm/pci-bridge.h>
#include <asm/delay.h>
#include <asm/mv64x60.h>


u8 mv64x60_pci_exclude_bridge = 1;
DEFINE_SPINLOCK(mv64x60_lock);

static phys_addr_t 	mv64x60_bridge_pbase;
static void 		__iomem *mv64x60_bridge_vbase;
static u32		mv64x60_bridge_type = MV64x60_TYPE_INVALID;
static u32		mv64x60_bridge_rev;
#if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260)
static struct pci_controller	sysfs_hose_a;
#endif

static u32 gt64260_translate_size(u32 base, u32 size, u32 num_bits);
static u32 gt64260_untranslate_size(u32 base, u32 size, u32 num_bits);
static void gt64260_set_pci2mem_window(struct pci_controller *hose, u32 bus,
	u32 window, u32 base);
static void gt64260_set_pci2regs_window(struct mv64x60_handle *bh,
	struct pci_controller *hose, u32 bus, u32 base);
static u32 gt64260_is_enabled_32bit(struct mv64x60_handle *bh, u32 window);
static void gt64260_enable_window_32bit(struct mv64x60_handle *bh, u32 window);
static void gt64260_disable_window_32bit(struct mv64x60_handle *bh, u32 window);
static void gt64260_enable_window_64bit(struct mv64x60_handle *bh, u32 window);
static void gt64260_disable_window_64bit(struct mv64x60_handle *bh, u32 window);
static void gt64260_disable_all_windows(struct mv64x60_handle *bh,
	struct mv64x60_setup_info *si);
static void gt64260a_chip_specific_init(struct mv64x60_handle *bh,
	struct mv64x60_setup_info *si);
static void gt64260b_chip_specific_init(struct mv64x60_handle *bh,
	struct mv64x60_setup_info *si);

static u32 mv64360_translate_size(u32 base, u32 size, u32 num_bits);
static u32 mv64360_untranslate_size(u32 base, u32 size, u32 num_bits);
static void mv64360_set_pci2mem_window(struct pci_controller *hose, u32 bus,
	u32 window, u32 base);
static void mv64360_set_pci2regs_window(struct mv64x60_handle *bh,
	struct pci_controller *hose, u32 bus, u32 base);
static u32 mv64360_is_enabled_32bit(struct mv64x60_handle *bh, u32 window);
static void mv64360_enable_window_32bit(struct mv64x60_handle *bh, u32 window);
static void mv64360_disable_window_32bit(struct mv64x60_handle *bh, u32 window);
static void mv64360_enable_window_64bit(struct mv64x60_handle *bh, u32 window);
static void mv64360_disable_window_64bit(struct mv64x60_handle *bh, u32 window);
static void mv64360_disable_all_windows(struct mv64x60_handle *bh,
	struct mv64x60_setup_info *si);
static void mv64360_config_io2mem_windows(struct mv64x60_handle *bh,
	struct mv64x60_setup_info *si,
	u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]);
static void mv64360_set_mpsc2regs_window(struct mv64x60_handle *bh, u32 base);
static void mv64360_chip_specific_init(struct mv64x60_handle *bh,
	struct mv64x60_setup_info *si);
static void mv64460_chip_specific_init(struct mv64x60_handle *bh,
	struct mv64x60_setup_info *si);


/*
 * Define tables that have the chip-specific info for each type of
 * Marvell bridge chip.
 */
static struct mv64x60_chip_info gt64260a_ci __initdata = { /* GT64260A */
	.translate_size		= gt64260_translate_size,
	.untranslate_size	= gt64260_untranslate_size,
	.set_pci2mem_window	= gt64260_set_pci2mem_window,
	.set_pci2regs_window	= gt64260_set_pci2regs_window,
	.is_enabled_32bit	= gt64260_is_enabled_32bit,
	.enable_window_32bit	= gt64260_enable_window_32bit,
	.disable_window_32bit	= gt64260_disable_window_32bit,
	.enable_window_64bit	= gt64260_enable_window_64bit,
	.disable_window_64bit	= gt64260_disable_window_64bit,
	.disable_all_windows	= gt64260_disable_all_windows,
	.chip_specific_init	= gt64260a_chip_specific_init,
	.window_tab_32bit	= gt64260_32bit_windows,
	.window_tab_64bit	= gt64260_64bit_windows,
};

static struct mv64x60_chip_info gt64260b_ci __initdata = { /* GT64260B */
	.translate_size		= gt64260_translate_size,
	.untranslate_size	= gt64260_untranslate_size,
	.set_pci2mem_window	= gt64260_set_pci2mem_window,
	.set_pci2regs_window	= gt64260_set_pci2regs_window,
	.is_enabled_32bit	= gt64260_is_enabled_32bit,
	.enable_window_32bit	= gt64260_enable_window_32bit,
	.disable_window_32bit	= gt64260_disable_window_32bit,
	.enable_window_64bit	= gt64260_enable_window_64bit,
	.disable_window_64bit	= gt64260_disable_window_64bit,
	.disable_all_windows	= gt64260_disable_all_windows,
	.chip_specific_init	= gt64260b_chip_specific_init,
	.window_tab_32bit	= gt64260_32bit_windows,
	.window_tab_64bit	= gt64260_64bit_windows,
};

static struct mv64x60_chip_info mv64360_ci __initdata = { /* MV64360 */
	.translate_size		= mv64360_translate_size,
	.untranslate_size	= mv64360_untranslate_size,
	.set_pci2mem_window	= mv64360_set_pci2mem_window,
	.set_pci2regs_window	= mv64360_set_pci2regs_window,
	.is_enabled_32bit	= mv64360_is_enabled_32bit,
	.enable_window_32bit	= mv64360_enable_window_32bit,
	.disable_window_32bit	= mv64360_disable_window_32bit,
	.enable_window_64bit	= mv64360_enable_window_64bit,
	.disable_window_64bit	= mv64360_disable_window_64bit,
	.disable_all_windows	= mv64360_disable_all_windows,
	.config_io2mem_windows	= mv64360_config_io2mem_windows,
	.set_mpsc2regs_window	= mv64360_set_mpsc2regs_window,
	.chip_specific_init	= mv64360_chip_specific_init,
	.window_tab_32bit	= mv64360_32bit_windows,
	.window_tab_64bit	= mv64360_64bit_windows,
};

static struct mv64x60_chip_info mv64460_ci __initdata = { /* MV64460 */
	.translate_size		= mv64360_translate_size,
	.untranslate_size	= mv64360_untranslate_size,
	.set_pci2mem_window	= mv64360_set_pci2mem_window,
	.set_pci2regs_window	= mv64360_set_pci2regs_window,
	.is_enabled_32bit	= mv64360_is_enabled_32bit,
	.enable_window_32bit	= mv64360_enable_window_32bit,
	.disable_window_32bit	= mv64360_disable_window_32bit,
	.enable_window_64bit	= mv64360_enable_window_64bit,
	.disable_window_64bit	= mv64360_disable_window_64bit,
	.disable_all_windows	= mv64360_disable_all_windows,
	.config_io2mem_windows	= mv64360_config_io2mem_windows,
	.set_mpsc2regs_window	= mv64360_set_mpsc2regs_window,
	.chip_specific_init	= mv64460_chip_specific_init,
	.window_tab_32bit	= mv64360_32bit_windows,
	.window_tab_64bit	= mv64360_64bit_windows,
};

/*
 *****************************************************************************
 *
 *	Platform Device Definitions
 *
 *****************************************************************************
 */
#ifdef CONFIG_SERIAL_MPSC
static struct mpsc_shared_pdata mv64x60_mpsc_shared_pdata = {
	.mrr_val		= 0x3ffffe38,
	.rcrr_val		= 0,
	.tcrr_val		= 0,
	.intr_cause_val		= 0,
	.intr_mask_val		= 0,
};

static struct resource mv64x60_mpsc_shared_resources[] = {
	/* Do not change the order of the IORESOURCE_MEM resources */
	[0] = {
		.name	= "mpsc routing base",
		.start	= MV64x60_MPSC_ROUTING_OFFSET,
		.end	= MV64x60_MPSC_ROUTING_OFFSET +
			MPSC_ROUTING_REG_BLOCK_SIZE - 1,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.name	= "sdma intr base",
		.start	= MV64x60_SDMA_INTR_OFFSET,
		.end	= MV64x60_SDMA_INTR_OFFSET +
			MPSC_SDMA_INTR_REG_BLOCK_SIZE - 1,
		.flags	= IORESOURCE_MEM,
	},
};

static struct platform_device mpsc_shared_device = { /* Shared device */
	.name		= MPSC_SHARED_NAME,
	.id		= 0,
	.num_resources	= ARRAY_SIZE(mv64x60_mpsc_shared_resources),
	.resource	= mv64x60_mpsc_shared_resources,
	.dev = {
		.platform_data = &mv64x60_mpsc_shared_pdata,
	},
};

static struct mpsc_pdata mv64x60_mpsc0_pdata = {
	.mirror_regs		= 0,
	.cache_mgmt		= 0,
	.max_idle		= 0,
	.default_baud		= 9600,
	.default_bits		= 8,
	.default_parity		= 'n',
	.default_flow		= 'n',
	.chr_1_val		= 0x00000000,
	.chr_2_val		= 0x00000000,
	.chr_10_val		= 0x00000003,
	.mpcr_val		= 0,
	.bcr_val		= 0,
	.brg_can_tune		= 0,
	.brg_clk_src		= 8,		/* Default to TCLK */
	.brg_clk_freq		= 100000000,	/* Default to 100 MHz */
};

static struct resource mv64x60_mpsc0_resources[] = {
	/* Do not change the order of the IORESOURCE_MEM resources */
	[0] = {
		.name	= "mpsc 0 base",
		.start	= MV64x60_MPSC_0_OFFSET,
		.end	= MV64x60_MPSC_0_OFFSET + MPSC_REG_BLOCK_SIZE - 1,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.name	= "sdma 0 base",
		.start	= MV64x60_SDMA_0_OFFSET,
		.end	= MV64x60_SDMA_0_OFFSET + MPSC_SDMA_REG_BLOCK_SIZE - 1,
		.flags	= IORESOURCE_MEM,
	},
	[2] = {
		.name	= "brg 0 base",
		.start	= MV64x60_BRG_0_OFFSET,
		.end	= MV64x60_BRG_0_OFFSET + MPSC_BRG_REG_BLOCK_SIZE - 1,
		.flags	= IORESOURCE_MEM,
	},
	[3] = {
		.name	= "sdma 0 irq",
		.start	= MV64x60_IRQ_SDMA_0,
		.end	= MV64x60_IRQ_SDMA_0,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device mpsc0_device = {
	.name		= MPSC_CTLR_NAME,
	.id		= 0,
	.num_resources	= ARRAY_SIZE(mv64x60_mpsc0_resources),
	.resource	= mv64x60_mpsc0_resources,
	.dev = {
		.platform_data = &mv64x60_mpsc0_pdata,
	},
};

static struct mpsc_pdata mv64x60_mpsc1_pdata = {
	.mirror_regs		= 0,
	.cache_mgmt		= 0,
	.max_idle		= 0,
	.default_baud		= 9600,
	.default_bits		= 8,
	.default_parity		= 'n',
	.default_flow		= 'n',
	.chr_1_val		= 0x00000000,
	.chr_1_val		= 0x00000000,
	.chr_2_val		= 0x00000000,
	.chr_10_val		= 0x00000003,
	.mpcr_val		= 0,
	.bcr_val		= 0,
	.brg_can_tune		= 0,
	.brg_clk_src		= 8,		/* Default to TCLK */
	.brg_clk_freq		= 100000000,	/* Default to 100 MHz */
};

static struct resource mv64x60_mpsc1_resources[] = {
	/* Do not change the order of the IORESOURCE_MEM resources */
	[0] = {
		.name	= "mpsc 1 base",
		.start	= MV64x60_MPSC_1_OFFSET,
		.end	= MV64x60_MPSC_1_OFFSET + MPSC_REG_BLOCK_SIZE - 1,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.name	= "sdma 1 base",
		.start	= MV64x60_SDMA_1_OFFSET,
		.end	= MV64x60_SDMA_1_OFFSET + MPSC_SDMA_REG_BLOCK_SIZE - 1,
		.flags	= IORESOURCE_MEM,
	},
	[2] = {
		.name	= "brg 1 base",
		.start	= MV64x60_BRG_1_OFFSET,
		.end	= MV64x60_BRG_1_OFFSET + MPSC_BRG_REG_BLOCK_SIZE - 1,
		.flags	= IORESOURCE_MEM,
	},
	[3] = {
		.name	= "sdma 1 irq",
		.start	= MV64360_IRQ_SDMA_1,
		.end	= MV64360_IRQ_SDMA_1,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device mpsc1_device = {
	.name		= MPSC_CTLR_NAME,
	.id		= 1,
	.num_resources	= ARRAY_SIZE(mv64x60_mpsc1_resources),
	.resource	= mv64x60_mpsc1_resources,
	.dev = {
		.platform_data = &mv64x60_mpsc1_pdata,
	},
};
#endif

#ifdef CONFIG_MV643XX_ETH
static struct resource mv64x60_eth_shared_resources[] = {
	[0] = {
		.name	= "ethernet shared base",
		.start	= MV643XX_ETH_SHARED_REGS,
		.end	= MV643XX_ETH_SHARED_REGS +
					MV643XX_ETH_SHARED_REGS_SIZE - 1,
		.flags	= IORESOURCE_MEM,
	},
};

static struct platform_device mv64x60_eth_shared_device = {
	.name		= MV643XX_ETH_SHARED_NAME,
	.id		= 0,
	.num_resources	= ARRAY_SIZE(mv64x60_eth_shared_resources),
	.resource	= mv64x60_eth_shared_resources,
};

#ifdef CONFIG_MV643XX_ETH_0
static struct resource mv64x60_eth0_resources[] = {
	[0] = {
		.name	= "eth0 irq",
		.start	= MV64x60_IRQ_ETH_0,
		.end	= MV64x60_IRQ_ETH_0,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct mv643xx_eth_platform_data eth0_pd;

static struct platform_device eth0_device = {
	.name		= MV643XX_ETH_NAME,
	.id		= 0,
	.num_resources	= ARRAY_SIZE(mv64x60_eth0_resources),
	.resource	= mv64x60_eth0_resources,
	.dev = {
		.platform_data = &eth0_pd,
	},
};
#endif

#ifdef CONFIG_MV643XX_ETH_1
static struct resource mv64x60_eth1_resources[] = {
	[0] = {
		.name	= "eth1 irq",
		.start	= MV64x60_IRQ_ETH_1,
		.end	= MV64x60_IRQ_ETH_1,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct mv643xx_eth_platform_data eth1_pd;

static struct platform_device eth1_device = {
	.name		= MV643XX_ETH_NAME,
	.id		= 1,
	.num_resources	= ARRAY_SIZE(mv64x60_eth1_resources),
	.resource	= mv64x60_eth1_resources,
	.dev = {
		.platform_data = &eth1_pd,
	},
};
#endif

#ifdef CONFIG_MV643XX_ETH_2
static struct resource mv64x60_eth2_resources[] = {
	[0] = {
		.name	= "eth2 irq",
		.start	= MV64x60_IRQ_ETH_2,
		.end	= MV64x60_IRQ_ETH_2,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct mv643xx_eth_platform_data eth2_pd;

static struct platform_device eth2_device = {
	.name		= MV643XX_ETH_NAME,
	.id		= 2,
	.num_resources	= ARRAY_SIZE(mv64x60_eth2_resources),
	.resource	= mv64x60_eth2_resources,
	.dev = {
		.platform_data = &eth2_pd,
	},
};
#endif
#endif

#ifdef	CONFIG_I2C_MV64XXX
static struct mv64xxx_i2c_pdata mv64xxx_i2c_pdata = {
	.freq_m			= 8,
	.freq_n			= 3,
	.timeout		= 1000, /* Default timeout of 1 second */
	.retries		= 1,
};

static struct resource mv64xxx_i2c_resources[] = {
	/* Do not change the order of the IORESOURCE_MEM resources */
	[0] = {
		.name	= "mv64xxx i2c base",
		.start	= MV64XXX_I2C_OFFSET,
		.end	= MV64XXX_I2C_OFFSET + MV64XXX_I2C_REG_BLOCK_SIZE - 1,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.name	= "mv64xxx i2c irq",
		.start	= MV64x60_IRQ_I2C,
		.end	= MV64x60_IRQ_I2C,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device i2c_device = {
	.name		= MV64XXX_I2C_CTLR_NAME,
	.id		= 0,
	.num_resources	= ARRAY_SIZE(mv64xxx_i2c_resources),
	.resource	= mv64xxx_i2c_resources,
	.dev = {
		.platform_data = &mv64xxx_i2c_pdata,
	},
};
#endif

#if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260)
static struct mv64xxx_pdata mv64xxx_pdata = {
	.hs_reg_valid	= 0,
};

static struct platform_device mv64xxx_device = { /* general mv64x60 stuff */
	.name	= MV64XXX_DEV_NAME,
	.id	= 0,
	.dev = {
		.platform_data = &mv64xxx_pdata,
	},
};
#endif

static struct platform_device *mv64x60_pd_devs[] __initdata = {
#ifdef CONFIG_SERIAL_MPSC
	&mpsc_shared_device,
	&mpsc0_device,
	&mpsc1_device,
#endif