📄 radstone_ppc7d.h
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#define PPC7D_CPLD_MEM_CONFIG_EXTEND 0x0806#define PPC7D_CPLD_SCSI_ACTIVITY_LED 0x0808#define PPC7D_CPLD_EQUIPMENT_PRESENT_1 0x080C#define PPC7D_CPLD_EQUIPMENT_PRESENT_2 0x080E#define PPC7D_CPLD_EQUIPMENT_PRESENT_3 0x0810#define PPC7D_CPLD_EQUIPMENT_PRESENT_4 0x0812#define PPC7D_CPLD_KEY_LOCK 0x0818#define PPC7D_CPLD_LEDS 0x0820#define PPC7D_CPLD_COMS 0x0824#define PPC7D_CPLD_RTS 0x0826#define PPC7D_CPLD_RESET 0x0828#define PPC7D_CPLD_WATCHDOG_TRIG 0x082C#define PPC7D_CPLD_INTR 0x082E#define PPC7D_CPLD_INTR_STATUS 0x0830#define PPC7D_CPLD_PCI_CONFIG 0x0832#define PPC7D_CPLD_BOARD_REVISION 0x0854#define PPC7D_CPLD_EXTENDED_ID 0x0858#define PPC7D_CPLD_ID_LINK 0x0864#define PPC7D_CPLD_MOTHERBOARD_TYPE 0x0866#define PPC7D_CPLD_FLASH_WRITE_CNTL 0x0868#define PPC7D_CPLD_SW_FLASH_WRITE_PROTECT 0x086A#define PPC7D_CPLD_FLASH_CNTL 0x086E/* MEMORY_CONFIG_EXTEND */#define PPC7D_CPLD_SDRAM_BANK_NUM_MASK 0x02#define PPC7D_CPLD_SDRAM_BANK_SIZE_MASK 0xc0#define PPC7D_CPLD_SDRAM_BANK_SIZE_128M 0#define PPC7D_CPLD_SDRAM_BANK_SIZE_256M 0x40#define PPC7D_CPLD_SDRAM_BANK_SIZE_512M 0x80#define PPC7D_CPLD_SDRAM_BANK_SIZE_1G 0xc0#define PPC7D_CPLD_FLASH_DEV_SIZE_MASK 0x03#define PPC7D_CPLD_FLASH_BANK_NUM_MASK 0x0c#define PPC7D_CPLD_FLASH_DEV_SIZE_64M 0#define PPC7D_CPLD_FLASH_DEV_SIZE_32M 1#define PPC7D_CPLD_FLASH_DEV_SIZE_16M 3#define PPC7D_CPLD_FLASH_BANK_NUM_4 0x00#define PPC7D_CPLD_FLASH_BANK_NUM_3 0x04#define PPC7D_CPLD_FLASH_BANK_NUM_2 0x08#define PPC7D_CPLD_FLASH_BANK_NUM_1 0x0c/* SCSI_LED */#define PPC7D_CPLD_SCSI_ACTIVITY_LED_OFF 0#define PPC7D_CPLD_SCSI_ACTIVITY_LED_ON 1/* EQUIPMENT_PRESENT_1 */#define PPC7D_CPLD_EQPT_PRES_1_FITTED 0#define PPC7D_CPLD_EQPT_PRES_1_PMC2_MASK (0x80 >> 2)#define PPC7D_CPLD_EQPT_PRES_1_PMC1_MASK (0x80 >> 3)#define PPC7D_CPLD_EQPT_PRES_1_AFIX_MASK (0x80 >> 4)/* EQUIPMENT_PRESENT_2 */#define PPC7D_CPLD_EQPT_PRES_2_FITTED !0#define PPC7D_CPLD_EQPT_PRES_2_UNIVERSE_MASK (0x80 >> 0)#define PPC7D_CPLD_EQPT_PRES_2_COM36_MASK (0x80 >> 2)#define PPC7D_CPLD_EQPT_PRES_2_GIGE_MASK (0x80 >> 3)#define PPC7D_CPLD_EQPT_PRES_2_DUALGIGE_MASK (0x80 >> 4)/* EQUIPMENT_PRESENT_3 */#define PPC7D_CPLD_EQPT_PRES_3_PMC2_V_MASK (0x80 >> 3)#define PPC7D_CPLD_EQPT_PRES_3_PMC2_5V (0 >> 3)#define PPC7D_CPLD_EQPT_PRES_3_PMC2_3V (0x80 >> 3)#define PPC7D_CPLD_EQPT_PRES_3_PMC1_V_MASK (0x80 >> 4)#define PPC7D_CPLD_EQPT_PRES_3_PMC1_5V (0 >> 4)#define PPC7D_CPLD_EQPT_PRES_3_PMC1_3V (0x80 >> 4)#define PPC7D_CPLD_EQPT_PRES_3_PMC_POWER_MASK (0x80 >> 5)#define PPC7D_CPLD_EQPT_PRES_3_PMC_POWER_INTER (0 >> 5)#define PPC7D_CPLD_EQPT_PRES_3_PMC_POWER_VME (0x80 >> 5)/* EQUIPMENT_PRESENT_4 */#define PPC7D_CPLD_EQPT_PRES_4_LPT_MASK (0x80 >> 2)#define PPC7D_CPLD_EQPT_PRES_4_LPT_FITTED (0x80 >> 2)#define PPC7D_CPLD_EQPT_PRES_4_PS2_USB2_MASK (0xc0 >> 6)#define PPC7D_CPLD_EQPT_PRES_4_PS2_FITTED (0x40 >> 6)#define PPC7D_CPLD_EQPT_PRES_4_USB2_FITTED (0x80 >> 6)/* CPLD_LEDS */#define PPC7D_CPLD_LEDS_ON (!0)#define PPC7D_CPLD_LEDS_OFF (0)#define PPC7D_CPLD_LEDS_NVRAM_PAGE_MASK (0xc0 >> 2)#define PPC7D_CPLD_LEDS_DS201_MASK (0x80 >> 4)#define PPC7D_CPLD_LEDS_DS219_MASK (0x80 >> 5)#define PPC7D_CPLD_LEDS_DS220_MASK (0x80 >> 6)#define PPC7D_CPLD_LEDS_DS221_MASK (0x80 >> 7)/* CPLD_COMS */#define PPC7D_CPLD_COMS_COM3_TCLKEN (0x80 >> 0)#define PPC7D_CPLD_COMS_COM3_RTCLKEN (0x80 >> 1)#define PPC7D_CPLD_COMS_COM3_MODE_MASK (0x80 >> 2)#define PPC7D_CPLD_COMS_COM3_MODE_RS232 (0)#define PPC7D_CPLD_COMS_COM3_MODE_RS422 (0x80 >> 2)#define PPC7D_CPLD_COMS_COM3_TXEN (0x80 >> 3)#define PPC7D_CPLD_COMS_COM4_TCLKEN (0x80 >> 4)#define PPC7D_CPLD_COMS_COM4_RTCLKEN (0x80 >> 5)#define PPC7D_CPLD_COMS_COM4_MODE_MASK (0x80 >> 6)#define PPC7D_CPLD_COMS_COM4_MODE_RS232 (0)#define PPC7D_CPLD_COMS_COM4_MODE_RS422 (0x80 >> 6)#define PPC7D_CPLD_COMS_COM4_TXEN (0x80 >> 7)/* CPLD_RTS */#define PPC7D_CPLD_RTS_COM36_LOOPBACK (0x80 >> 0)#define PPC7D_CPLD_RTS_COM4_SCLK (0x80 >> 1)#define PPC7D_CPLD_RTS_COM3_TXFUNC_MASK (0xc0 >> 2)#define PPC7D_CPLD_RTS_COM3_TXFUNC_DISABLED (0 >> 2)#define PPC7D_CPLD_RTS_COM3_TXFUNC_ENABLED (0x80 >> 2)#define PPC7D_CPLD_RTS_COM3_TXFUNC_ENABLED_RTG3 (0xc0 >> 2)#define PPC7D_CPLD_RTS_COM3_TXFUNC_ENABLED_RTG3S (0xc0 >> 2)#define PPC7D_CPLD_RTS_COM56_MODE_MASK (0x80 >> 4)#define PPC7D_CPLD_RTS_COM56_MODE_RS232 (0)#define PPC7D_CPLD_RTS_COM56_MODE_RS422 (0x80 >> 4)#define PPC7D_CPLD_RTS_COM56_ENABLE_MASK (0x80 >> 5)#define PPC7D_CPLD_RTS_COM56_DISABLED (0)#define PPC7D_CPLD_RTS_COM56_ENABLED (0x80 >> 5)#define PPC7D_CPLD_RTS_COM4_TXFUNC_MASK (0xc0 >> 6)#define PPC7D_CPLD_RTS_COM4_TXFUNC_DISABLED (0 >> 6)#define PPC7D_CPLD_RTS_COM4_TXFUNC_ENABLED (0x80 >> 6)#define PPC7D_CPLD_RTS_COM4_TXFUNC_ENABLED_RTG3 (0x40 >> 6)#define PPC7D_CPLD_RTS_COM4_TXFUNC_ENABLED_RTG3S (0x40 >> 6)/* WATCHDOG_TRIG */#define PPC7D_CPLD_WDOG_CAUSE_MASK (0x80 >> 0)#define PPC7D_CPLD_WDOG_CAUSE_NORMAL_RESET (0 >> 0)#define PPC7D_CPLD_WDOG_CAUSE_WATCHDOG (0x80 >> 0)#define PPC7D_CPLD_WDOG_ENABLE_MASK (0x80 >> 6)#define PPC7D_CPLD_WDOG_ENABLE_OFF (0 >> 6)#define PPC7D_CPLD_WDOG_ENABLE_ON (0x80 >> 6)#define PPC7D_CPLD_WDOG_RESETSW_MASK (0x80 >> 7)#define PPC7D_CPLD_WDOG_RESETSW_OFF (0 >> 7)#define PPC7D_CPLD_WDOG_RESETSW_ON (0x80 >> 7)/* Interrupt mask and status bits */#define PPC7D_CPLD_INTR_TEMP_MASK (0x80 >> 0)#define PPC7D_CPLD_INTR_HB8_MASK (0x80 >> 1)#define PPC7D_CPLD_INTR_PHY1_MASK (0x80 >> 2)#define PPC7D_CPLD_INTR_PHY0_MASK (0x80 >> 3)#define PPC7D_CPLD_INTR_ISANMI_MASK (0x80 >> 5)#define PPC7D_CPLD_INTR_CRITTEMP_MASK (0x80 >> 6)/* CPLD_INTR */#define PPC7D_CPLD_INTR_ENABLE_OFF (0)#define PPC7D_CPLD_INTR_ENABLE_ON (!0)/* CPLD_INTR_STATUS */#define PPC7D_CPLD_INTR_STATUS_OFF (0)#define PPC7D_CPLD_INTR_STATUS_ON (!0)/* CPLD_PCI_CONFIG */#define PPC7D_CPLD_PCI_CONFIG_PCI0_MASK 0x70#define PPC7D_CPLD_PCI_CONFIG_PCI0_PCI33 0x00#define PPC7D_CPLD_PCI_CONFIG_PCI0_PCI66 0x10#define PPC7D_CPLD_PCI_CONFIG_PCI0_PCIX33 0x40#define PPC7D_CPLD_PCI_CONFIG_PCI0_PCIX66 0x50#define PPC7D_CPLD_PCI_CONFIG_PCI0_PCIX100 0x60#define PPC7D_CPLD_PCI_CONFIG_PCI0_PCIX133 0x70#define PPC7D_CPLD_PCI_CONFIG_PCI1_MASK 0x07#define PPC7D_CPLD_PCI_CONFIG_PCI1_PCI33 0x00#define PPC7D_CPLD_PCI_CONFIG_PCI1_PCI66 0x01#define PPC7D_CPLD_PCI_CONFIG_PCI1_PCIX33 0x04#define PPC7D_CPLD_PCI_CONFIG_PCI1_PCIX66 0x05#define PPC7D_CPLD_PCI_CONFIG_PCI1_PCIX100 0x06#define PPC7D_CPLD_PCI_CONFIG_PCI1_PCIX133 0x07/* CPLD_BOARD_REVISION */#define PPC7D_CPLD_BOARD_REVISION_NUMBER_MASK 0xe0#define PPC7D_CPLD_BOARD_REVISION_LETTER_MASK 0x1f/* CPLD_EXTENDED_ID */#define PPC7D_CPLD_EXTENDED_ID_PPC7D 0x18/* CPLD_ID_LINK */#define PPC7D_CPLD_ID_LINK_VME64_GAP_MASK (0x80 >> 2)#define PPC7D_CPLD_ID_LINK_VME64_GA4_MASK (0x80 >> 3)#define PPC7D_CPLD_ID_LINK_E13_MASK (0x80 >> 4)#define PPC7D_CPLD_ID_LINK_E12_MASK (0x80 >> 5)#define PPC7D_CPLD_ID_LINK_E7_MASK (0x80 >> 6)#define PPC7D_CPLD_ID_LINK_E6_MASK (0x80 >> 7)/* CPLD_MOTHERBOARD_TYPE */#define PPC7D_CPLD_MB_TYPE_ECC_ENABLE_MASK (0x80 >> 0)#define PPC7D_CPLD_MB_TYPE_ECC_ENABLED (0x80 >> 0)#define PPC7D_CPLD_MB_TYPE_ECC_DISABLED (0 >> 0)#define PPC7D_CPLD_MB_TYPE_ECC_FITTED_MASK (0x80 >> 3)#define PPC7D_CPLD_MB_TYPE_PLL_MASK 0x0c#define PPC7D_CPLD_MB_TYPE_PLL_133 0x00#define PPC7D_CPLD_MB_TYPE_PLL_100 0x08#define PPC7D_CPLD_MB_TYPE_PLL_64 0x04#define PPC7D_CPLD_MB_TYPE_HW_ID_MASK 0x03/* CPLD_FLASH_WRITE_CNTL */#define PPD7D_CPLD_FLASH_CNTL_WR_LINK_MASK (0x80 >> 0)#define PPD7D_CPLD_FLASH_CNTL_WR_LINK_FITTED (0x80 >> 0)#define PPD7D_CPLD_FLASH_CNTL_BOOT_LINK_MASK (0x80 >> 2)#define PPD7D_CPLD_FLASH_CNTL_BOOT_LINK_FITTED (0x80 >> 2)#define PPD7D_CPLD_FLASH_CNTL_USER_LINK_MASK (0x80 >> 3)#define PPD7D_CPLD_FLASH_CNTL_USER_LINK_FITTED (0x80 >> 3)#define PPD7D_CPLD_FLASH_CNTL_RECO_WR_MASK (0x80 >> 5)#define PPD7D_CPLD_FLASH_CNTL_RECO_WR_ENABLED (0x80 >> 5)#define PPD7D_CPLD_FLASH_CNTL_BOOT_WR_MASK (0x80 >> 6)#define PPD7D_CPLD_FLASH_CNTL_BOOT_WR_ENABLED (0x80 >> 6)#define PPD7D_CPLD_FLASH_CNTL_USER_WR_MASK (0x80 >> 7)#define PPD7D_CPLD_FLASH_CNTL_USER_WR_ENABLED (0x80 >> 7)/* CPLD_SW_FLASH_WRITE_PROTECT */#define PPC7D_CPLD_SW_FLASH_WRPROT_ENABLED (!0)#define PPC7D_CPLD_SW_FLASH_WRPROT_DISABLED (0)#define PPC7D_CPLD_SW_FLASH_WRPROT_SYSBOOT_MASK (0x80 >> 6)#define PPC7D_CPLD_SW_FLASH_WRPROT_USER_MASK (0x80 >> 7)/* CPLD_FLASH_WRITE_CNTL */#define PPC7D_CPLD_FLASH_CNTL_NVRAM_PROT_MASK (0x80 >> 0)#define PPC7D_CPLD_FLASH_CNTL_NVRAM_DISABLED (0 >> 0)#define PPC7D_CPLD_FLASH_CNTL_NVRAM_ENABLED (0x80 >> 0)#define PPC7D_CPLD_FLASH_CNTL_ALTBOOT_LINK_MASK (0x80 >> 1)#define PPC7D_CPLD_FLASH_CNTL_VMEBOOT_LINK_MASK (0x80 >> 2)#define PPC7D_CPLD_FLASH_CNTL_RECBOOT_LINK_MASK (0x80 >> 3)#endif /* __PPC_PLATFORMS_PPC7D_H */⌨️ 快捷键说明
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