chestnut.c

linux-2.6.15.6

/*
 * arch/ppc/platforms/chestnut.c
 *
 * Board setup routines for IBM Chestnut
 *
 * Author: <[e-mail]>
 *
 * <2004> (c) MontaVista Software, Inc. This file is licensed under
 * the terms of the GNU General Public License version 2. This program
 * is licensed "as is" without any warranty of any kind, whether express
 * or implied.
 */

#include <linux/config.h>
#include <linux/stddef.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/reboot.h>
#include <linux/kdev_t.h>
#include <linux/major.h>
#include <linux/blkdev.h>
#include <linux/console.h>
#include <linux/root_dev.h>
#include <linux/initrd.h>
#include <linux/delay.h>
#include <linux/seq_file.h>
#include <linux/ide.h>
#include <linux/serial.h>
#include <linux/serial_core.h>
#include <linux/mtd/physmap.h>
#include <asm/system.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/time.h>
#include <asm/dma.h>
#include <asm/io.h>
#include <asm/hw_irq.h>
#include <asm/machdep.h>
#include <asm/kgdb.h>
#include <asm/bootinfo.h>
#include <asm/mv64x60.h>
#include <platforms/chestnut.h>

static void __iomem *sram_base; /* Virtual addr of Internal SRAM */
static void __iomem *cpld_base; /* Virtual addr of CPLD Regs */

static mv64x60_handle_t	bh;

extern void gen550_progress(char *, unsigned short);
extern void gen550_init(int, struct uart_port *);
extern void mv64360_pcibios_fixup(mv64x60_handle_t *bh);

#define BIT(x) (1<<x)
#define CHESTNUT_PRESERVE_MASK (BIT(MV64x60_CPU2DEV_0_WIN) | \
				BIT(MV64x60_CPU2DEV_1_WIN) | \
				BIT(MV64x60_CPU2DEV_2_WIN) | \
				BIT(MV64x60_CPU2DEV_3_WIN) | \
				BIT(MV64x60_CPU2BOOT_WIN))
/**************************************************************************
 * FUNCTION: chestnut_calibrate_decr
 *
 * DESCRIPTION: initialize decrementer interrupt frequency (used as system
 *              timer)
 *
 ****/
static void __init
chestnut_calibrate_decr(void)
{
	ulong freq;

	freq = CHESTNUT_BUS_SPEED / 4;

	printk("time_init: decrementer frequency = %lu.%.6lu MHz\n",
		freq/1000000, freq%1000000);

	tb_ticks_per_jiffy = freq / HZ;
	tb_to_us = mulhwu_scale_factor(freq, 1000000);
}

static int
chestnut_show_cpuinfo(struct seq_file *m)
{
	seq_printf(m, "vendor\t\t: IBM\n");
	seq_printf(m, "machine\t\t: 750FX/GX Eval Board (Chestnut/Buckeye)\n");

	return 0;
}

/**************************************************************************
 * FUNCTION: chestnut_find_end_of_memory
 *
 * DESCRIPTION: ppc_md memory size callback
 *
 ****/
unsigned long __init
chestnut_find_end_of_memory(void)
{
   	static int  mem_size = 0;

   	if (mem_size == 0) {
      		mem_size = mv64x60_get_mem_size(CONFIG_MV64X60_NEW_BASE,
				MV64x60_TYPE_MV64460);
   	}
   	return mem_size;
}

#if defined(CONFIG_SERIAL_8250)
static void __init
chestnut_early_serial_map(void)
{
	struct uart_port port;

	/* Setup serial port access */
	memset(&port, 0, sizeof(port));
	port.uartclk = BASE_BAUD * 16;
	port.irq = UART0_INT;
	port.flags = STD_COM_FLAGS | UPF_IOREMAP;
	port.iotype = SERIAL_IO_MEM;
	port.mapbase = CHESTNUT_UART0_IO_BASE;
	port.regshift = 0;

	if (early_serial_setup(&port) != 0)
		printk("Early serial init of port 0 failed\n");

	/* Assume early_serial_setup() doesn't modify serial_req */
	port.line = 1;
	port.irq = UART1_INT;
	port.mapbase = CHESTNUT_UART1_IO_BASE;

	if (early_serial_setup(&port) != 0)
		printk("Early serial init of port 1 failed\n");
}
#endif

/**************************************************************************
 * FUNCTION: chestnut_map_irq
 *
 * DESCRIPTION: 0 return since PCI IRQs not needed
 *
 ****/
static int __init
chestnut_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
{
	static char pci_irq_table[][4] = {
		{CHESTNUT_PCI_SLOT0_IRQ, CHESTNUT_PCI_SLOT0_IRQ,
		 CHESTNUT_PCI_SLOT0_IRQ, CHESTNUT_PCI_SLOT0_IRQ},
		{CHESTNUT_PCI_SLOT1_IRQ, CHESTNUT_PCI_SLOT1_IRQ,
		 CHESTNUT_PCI_SLOT1_IRQ, CHESTNUT_PCI_SLOT1_IRQ},
		{CHESTNUT_PCI_SLOT2_IRQ, CHESTNUT_PCI_SLOT2_IRQ,
		 CHESTNUT_PCI_SLOT2_IRQ, CHESTNUT_PCI_SLOT2_IRQ},
		{CHESTNUT_PCI_SLOT3_IRQ, CHESTNUT_PCI_SLOT3_IRQ,
		 CHESTNUT_PCI_SLOT3_IRQ, CHESTNUT_PCI_SLOT3_IRQ},
	};
	const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;

	return PCI_IRQ_TABLE_LOOKUP;
}


/**************************************************************************
 * FUNCTION: chestnut_setup_bridge
 *
 * DESCRIPTION: initalize board-specific settings on the MV64360
 *
 ****/
static void __init
chestnut_setup_bridge(void)
{
	struct mv64x60_setup_info	si;
	int i;

   	if ( ppc_md.progress )
		ppc_md.progress("chestnut_setup_bridge: enter", 0);

	memset(&si, 0, sizeof(si));

	si.phys_reg_base = CONFIG_MV64X60_NEW_BASE;

	/* setup only PCI bus 0 (bus 1 not used) */
	si.pci_0.enable_bus = 1;
	si.pci_0.pci_io.cpu_base = CHESTNUT_PCI0_IO_PROC_ADDR;
	si.pci_0.pci_io.pci_base_hi = 0;
	si.pci_0.pci_io.pci_base_lo = CHESTNUT_PCI0_IO_PCI_ADDR;
	si.pci_0.pci_io.size = CHESTNUT_PCI0_IO_SIZE;
	si.pci_0.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE; /* no swapping */
	si.pci_0.pci_mem[0].cpu_base = CHESTNUT_PCI0_MEM_PROC_ADDR;
	si.pci_0.pci_mem[0].pci_base_hi = CHESTNUT_PCI0_MEM_PCI_HI_ADDR;
	si.pci_0.pci_mem[0].pci_base_lo = CHESTNUT_PCI0_MEM_PCI_LO_ADDR;
	si.pci_0.pci_mem[0].size = CHESTNUT_PCI0_MEM_SIZE;
	si.pci_0.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE; /* no swapping */
	si.pci_0.pci_cmd_bits = 0;
	si.pci_0.latency_timer = 0x80;

	for (i=0; i<MV64x60_CPU2MEM_WINDOWS; i++) {
#if defined(CONFIG_NOT_COHERENT_CACHE)
		si.cpu_prot_options[i] = 0;
		si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE;
		si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE;
		si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE;

		si.pci_1.acc_cntl_options[i] =
		    MV64360_PCI_ACC_CNTL_SNOOP_NONE |
		    MV64360_PCI_ACC_CNTL_SWAP_NONE |
		    MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
		    MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
#else
		si.cpu_prot_options[i] = 0;
		si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE; /* errata */
		si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE; /* errata */
		si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE; /* errata */

		si.pci_1.acc_cntl_options[i] =
		    MV64360_PCI_ACC_CNTL_SNOOP_WB |
		    MV64360_PCI_ACC_CNTL_SWAP_NONE |
		    MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
		    MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES;
#endif
	}

   	/* Lookup host bridge - on CPU 0 - no SMP support */
   	if (mv64x60_init(&bh, &si)) {
        	printk("\n\nPCI Bridge initialization failed!\n");
   	}

	pci_dram_offset = 0;
	ppc_md.pci_swizzle = common_swizzle;
	ppc_md.pci_map_irq = chestnut_map_irq;
	ppc_md.pci_exclude_device = mv64x60_pci_exclude_device;

	mv64x60_set_bus(&bh, 0, 0);
	bh.hose_a->first_busno = 0;
	bh.hose_a->last_busno = 0xff;
	bh.hose_a->last_busno = pciauto_bus_scan(bh.hose_a, 0);
}

void __init
chestnut_setup_peripherals(void)
{
   	mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
			CHESTNUT_BOOT_8BIT_BASE, CHESTNUT_BOOT_8BIT_SIZE, 0);
	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);

	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN,
			CHESTNUT_32BIT_BASE, CHESTNUT_32BIT_SIZE, 0);
	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN);

	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN,
			CHESTNUT_CPLD_BASE, CHESTNUT_CPLD_SIZE, 0);
	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);
	cpld_base = ioremap(CHESTNUT_CPLD_BASE, CHESTNUT_CPLD_SIZE);

	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN,
			CHESTNUT_UART_BASE, CHESTNUT_UART_SIZE, 0);
	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN);

	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_3_WIN,
			CHESTNUT_FRAM_BASE, CHESTNUT_FRAM_SIZE, 0);
	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_3_WIN);

   	mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
			CHESTNUT_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0);
	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);

#ifdef CONFIG_NOT_COHERENT_CACHE
   	mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b0);
#else
   	mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b2);
#endif
	sram_base = ioremap(CHESTNUT_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE);
   	memset(sram_base, 0, MV64360_SRAM_SIZE);

	/*
	 * Configure MPP pins for PCI DMA
	 *
	 * PCI Slot	GNT pin		REQ pin
	 *	0	MPP16		MPP17
	 *	1	MPP18		MPP19
	 *	2	MPP20		MPP21
	 *	3	MPP22		MPP23
	 */
	mv64x60_write(&bh, MV64x60_MPP_CNTL_2,
			(0x1 << 0)  |	/* MPPSel16 PCI0_GNT[0] */
			(0x1 << 4)  |	/* MPPSel17 PCI0_REQ[0] */
			(0x1 << 8)  |	/* MPPSel18 PCI0_GNT[1] */
			(0x1 << 12) |	/* MPPSel19 PCI0_REQ[1] */
			(0x1 << 16) |	/* MPPSel20 PCI0_GNT[2] */
			(0x1 << 20) |	/* MPPSel21 PCI0_REQ[2] */
			(0x1 << 24) |	/* MPPSel22 PCI0_GNT[3] */
			(0x1 << 28));	/* MPPSel23 PCI0_REQ[3] */