radstone_ppc7d.c

linux-2.6.15.6

#endif
	/* If system operates with internal bus arbiter (CPU master
	 * control bit8) clear AACK Delay bit [25] in CPU
	 * configuration register.
	 */
	temp = mv64x60_read(&bh, MV64x60_CPU_MASTER_CNTL);
	if (temp & (1 << 8)) {
		temp = mv64x60_read(&bh, MV64x60_CPU_CONFIG);
		mv64x60_write(&bh, MV64x60_CPU_CONFIG, (temp & ~(1 << 25)));
	}

	/* Data and address parity is enabled */
	temp = mv64x60_read(&bh, MV64x60_CPU_CONFIG);
	mv64x60_write(&bh, MV64x60_CPU_CONFIG,
		      (temp | (1 << 26) | (1 << 19)));

	pci_dram_offset = 0;	/* sys mem at same addr on PCI & cpu bus */
	ppc_md.pci_swizzle = common_swizzle;
	ppc_md.pci_map_irq = ppc7d_map_irq;
	ppc_md.pci_exclude_device = ppc7d_pci_exclude_device;

	mv64x60_set_bus(&bh, 0, 0);
	bh.hose_a->first_busno = 0;
	bh.hose_a->last_busno = 0xff;
	bh.hose_a->mem_space.start = PPC7D_PCI0_MEM0_START_PCI_LO_ADDR;
	bh.hose_a->mem_space.end =
	    PPC7D_PCI0_MEM0_START_PCI_LO_ADDR + PPC7D_PCI0_MEM0_SIZE;

	/* These will be set later, as a result of PCI0 scan */
	bh.hose_b->first_busno = 0;
	bh.hose_b->last_busno = 0xff;
	bh.hose_b->mem_space.start = PPC7D_PCI1_MEM0_START_PCI_LO_ADDR;
	bh.hose_b->mem_space.end =
	    PPC7D_PCI1_MEM0_START_PCI_LO_ADDR + PPC7D_PCI1_MEM0_SIZE;

	pr_debug("MV64360: PCI#0 IO decode %08x/%08x IO remap %08x\n",
		 mv64x60_read(&bh, 0x48), mv64x60_read(&bh, 0x50),
		 mv64x60_read(&bh, 0xf0));
}

static void __init ppc7d_setup_arch(void)
{
	int port;

	loops_per_jiffy = 100000000 / HZ;

#ifdef CONFIG_BLK_DEV_INITRD
	if (initrd_start)
		ROOT_DEV = Root_RAM0;
	else
#endif
#ifdef	CONFIG_ROOT_NFS
		ROOT_DEV = Root_NFS;
#else
		ROOT_DEV = Root_HDA1;
#endif

	if ((cur_cpu_spec->cpu_features & CPU_FTR_SPEC7450) ||
	    (cur_cpu_spec->cpu_features & CPU_FTR_L3CR))
		/* 745x is different.  We only want to pass along enable. */
		_set_L2CR(L2CR_L2E);
	else if (cur_cpu_spec->cpu_features & CPU_FTR_L2CR)
		/* All modules have 1MB of L2.  We also assume that an
		 * L2 divisor of 3 will work.
		 */
		_set_L2CR(L2CR_L2E | L2CR_L2SIZ_1MB | L2CR_L2CLK_DIV3
			  | L2CR_L2RAM_PIPE | L2CR_L2OH_1_0 | L2CR_L2DF);

	if (cur_cpu_spec->cpu_features & CPU_FTR_L3CR)
		/* No L3 cache */
		_set_L3CR(0);

#ifdef CONFIG_DUMMY_CONSOLE
	conswitchp = &dummy_con;
#endif

	/* Lookup PCI host bridges */
	if (ppc_md.progress)
		ppc_md.progress("ppc7d_setup_arch: calling setup_bridge", 0);

	ppc7d_setup_bridge();
	ppc7d_setup_peripherals();

	/* Disable ethernet. It might have been setup by the bootrom */
	for (port = 0; port < 3; port++)
		mv64x60_write(&bh, MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port),
			      0x0000ff00);

	/* Clear queue pointers to ensure they are all initialized,
	 * otherwise since queues 1-7 are unused, they have random
	 * pointers which look strange in register dumps. Don't bother
	 * with queue 0 since it will be initialized later.
	 */
	for (port = 0; port < 3; port++) {
		mv64x60_write(&bh,
			      MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port),
			      0x00000000);
		mv64x60_write(&bh,
			      MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port),
			      0x00000000);
		mv64x60_write(&bh,
			      MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port),
			      0x00000000);
		mv64x60_write(&bh,
			      MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port),
			      0x00000000);
		mv64x60_write(&bh,
			      MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port),
			      0x00000000);
		mv64x60_write(&bh,
			      MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port),
			      0x00000000);
		mv64x60_write(&bh,
			      MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port),
			      0x00000000);
	}

	printk(KERN_INFO "Radstone Technology PPC7D\n");
	if (ppc_md.progress)
		ppc_md.progress("ppc7d_setup_arch: exit", 0);

}

/* Real Time Clock support.
 * PPC7D has a DS1337 accessed by I2C.
 */
static ulong ppc7d_get_rtc_time(void)
{
        struct rtc_time tm;
        int result;

        spin_lock(&rtc_lock);
        result = ds1337_do_command(0, DS1337_GET_DATE, &tm);
        spin_unlock(&rtc_lock);

        if (result == 0)
                result = mktime(tm.tm_year, tm.tm_mon, tm.tm_mday, tm.tm_hour, tm.tm_min, tm.tm_sec);

        return result;
}

static int ppc7d_set_rtc_time(unsigned long nowtime)
{
        struct rtc_time tm;
        int result;

        spin_lock(&rtc_lock);
        to_tm(nowtime, &tm);
        result = ds1337_do_command(0, DS1337_SET_DATE, &tm);
        spin_unlock(&rtc_lock);

        return result;
}

/* This kernel command line parameter can be used to have the target
 * wait for a JTAG debugger to attach. Of course, a JTAG debugger
 * with hardware breakpoint support can have the target stop at any
 * location during init, but this is a convenience feature that makes
 * it easier in the common case of loading the code using the ppcboot
 * bootloader..
 */
static unsigned long ppc7d_wait_debugger;

static int __init ppc7d_waitdbg(char *str)
{
	ppc7d_wait_debugger = 1;
	return 1;
}

__setup("waitdbg", ppc7d_waitdbg);

/* Second phase board init, called after other (architecture common)
 * low-level services have been initialized.
 */
static void ppc7d_init2(void)
{
	unsigned long flags;
	u32 data;
	u8 data8;

	pr_debug("%s: enter\n", __FUNCTION__);

	/* Wait for debugger? */
	if (ppc7d_wait_debugger) {
		printk("Waiting for debugger...\n");

		while (readl(&ppc7d_wait_debugger)) ;
	}

	/* Hook up i8259 interrupt which is connected to GPP28 */
	request_irq(mv64360_irq_base + MV64x60_IRQ_GPP28, ppc7d_i8259_intr,
		    SA_INTERRUPT, "I8259 (GPP28) interrupt", (void *)0);

	/* Configure MPP16 as watchdog NMI, MPP17 as watchdog WDE */
	spin_lock_irqsave(&mv64x60_lock, flags);
	data = mv64x60_read(&bh, MV64x60_MPP_CNTL_2);
	data &= ~(0x0000000f << 0);
	data |= (0x00000004 << 0);
	data &= ~(0x0000000f << 4);
	data |= (0x00000004 << 4);
	mv64x60_write(&bh, MV64x60_MPP_CNTL_2, data);
	spin_unlock_irqrestore(&mv64x60_lock, flags);

	/* All LEDs off */
	data8 = inb(PPC7D_CPLD_LEDS);
	data8 &= ~0x08;
	data8 |= 0x07;
	outb(data8, PPC7D_CPLD_LEDS);

        /* Hook up RTC. We couldn't do this earlier because we need the I2C subsystem */
        ppc_md.set_rtc_time = ppc7d_set_rtc_time;
        ppc_md.get_rtc_time = ppc7d_get_rtc_time;

	pr_debug("%s: exit\n", __FUNCTION__);
}

/* Called from machine_init(), early, before any of the __init functions
 * have run. We must init software-configurable pins before other functions
 * such as interrupt controllers are initialised.
 */
void __init platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
			  unsigned long r6, unsigned long r7)
{
	u8 val8;
	u8 rev_num;

	/* Map 0xe0000000-0xffffffff early because we need access to SRAM
	 * and the ISA memory space (for serial port) here. This mapping
	 * is redone properly in ppc7d_map_io() later.
	 */
	mtspr(SPRN_DBAT3U, 0xe0003fff);
	mtspr(SPRN_DBAT3L, 0xe000002a);

	/*
	 * Zero SRAM. Note that this generates parity errors on
	 * internal data path in SRAM if it's first time accessing it
	 * after reset.
	 *
	 * We do this ASAP to avoid parity errors when reading
	 * uninitialized SRAM.
	 */
	memset((void *)PPC7D_INTERNAL_SRAM_BASE, 0, MV64360_SRAM_SIZE);

	pr_debug("platform_init: r3-r7: %lx %lx %lx %lx %lx\n",
		 r3, r4, r5, r6, r7);

	parse_bootinfo(find_bootinfo());

	/* ASSUMPTION:  If both r3 (bd_t pointer) and r6 (cmdline pointer)
	 * are non-zero, then we should use the board info from the bd_t
	 * structure and the cmdline pointed to by r6 instead of the
	 * information from birecs, if any.  Otherwise, use the information
	 * from birecs as discovered by the preceeding call to
	 * parse_bootinfo().  This rule should work with both PPCBoot, which
	 * uses a bd_t board info structure, and the kernel boot wrapper,
	 * which uses birecs.
	 */
	if (r3 && r6) {
		bd_t *bp = (bd_t *) __res;

		/* copy board info structure */
		memcpy((void *)__res, (void *)(r3 + KERNELBASE), sizeof(bd_t));
		/* copy command line */
		*(char *)(r7 + KERNELBASE) = 0;
		strcpy(cmd_line, (char *)(r6 + KERNELBASE));

		printk(KERN_INFO "Board info data:-\n");
		printk(KERN_INFO "  Internal freq: %lu MHz, bus freq: %lu MHz\n",
		       bp->bi_intfreq, bp->bi_busfreq);
		printk(KERN_INFO "  Memory: %lx, size %lx\n", bp->bi_memstart,
		       bp->bi_memsize);
		printk(KERN_INFO "  Console baudrate: %lu\n", bp->bi_baudrate);
		printk(KERN_INFO "  Ethernet address: "
		       "%02x:%02x:%02x:%02x:%02x:%02x\n",
		       bp->bi_enetaddr[0], bp->bi_enetaddr[1],
		       bp->bi_enetaddr[2], bp->bi_enetaddr[3],
		       bp->bi_enetaddr[4], bp->bi_enetaddr[5]);
	}
#ifdef CONFIG_BLK_DEV_INITRD
	/* take care of initrd if we have one */
	if (r4) {
		initrd_start = r4 + KERNELBASE;
		initrd_end = r5 + KERNELBASE;
		printk(KERN_INFO "INITRD @ %lx/%lx\n", initrd_start, initrd_end);
	}
#endif /* CONFIG_BLK_DEV_INITRD */

	/* Map in board regs, etc. */
	isa_io_base = 0xe8000000;
	isa_mem_base = 0xe8000000;
	pci_dram_offset = 0x00000000;
	ISA_DMA_THRESHOLD = 0x00ffffff;
	DMA_MODE_READ = 0x44;
	DMA_MODE_WRITE = 0x48;

	ppc_md.setup_arch = ppc7d_setup_arch;
	ppc_md.init = ppc7d_init2;
	ppc_md.show_cpuinfo = ppc7d_show_cpuinfo;
	/* XXX this is broken... */
	ppc_md.irq_canonicalize = ppc7d_irq_canonicalize;
	ppc_md.init_IRQ = ppc7d_init_irq;
	ppc_md.get_irq = ppc7d_get_irq;

	ppc_md.restart = ppc7d_restart;
	ppc_md.power_off = ppc7d_power_off;
	ppc_md.halt = ppc7d_halt;

	ppc_md.find_end_of_memory = ppc7d_find_end_of_memory;
	ppc_md.setup_io_mappings = ppc7d_map_io;

	ppc_md.time_init = NULL;
	ppc_md.set_rtc_time = NULL;
	ppc_md.get_rtc_time = NULL;
	ppc_md.calibrate_decr = ppc7d_calibrate_decr;
	ppc_md.nvram_read_val = NULL;
	ppc_md.nvram_write_val = NULL;

	ppc_md.heartbeat = ppc7d_heartbeat;
	ppc_md.heartbeat_reset = HZ;
	ppc_md.heartbeat_count = ppc_md.heartbeat_reset;

	ppc_md.pcibios_fixup_bus = ppc7d_pci_fixup_bus;

#if defined(CONFIG_SERIAL_MPSC) || defined(CONFIG_MV643XX_ETH) || \
    defined(CONFIG_I2C_MV64XXX)
	platform_notify = ppc7d_platform_notify;
#endif

#ifdef CONFIG_SERIAL_MPSC
	/* On PPC7D, we must configure MPSC support via CPLD control
	 * registers.
	 */
	outb(PPC7D_CPLD_RTS_COM4_SCLK |
	     PPC7D_CPLD_RTS_COM56_ENABLED, PPC7D_CPLD_RTS);
	outb(PPC7D_CPLD_COMS_COM3_TCLKEN |
	     PPC7D_CPLD_COMS_COM3_TXEN |
	     PPC7D_CPLD_COMS_COM4_TCLKEN |
	     PPC7D_CPLD_COMS_COM4_TXEN, PPC7D_CPLD_COMS);
#endif /* CONFIG_SERIAL_MPSC */

#if defined(CONFIG_KGDB) || defined(CONFIG_SERIAL_TEXT_DEBUG)
	ppc7d_early_serial_map();
#ifdef  CONFIG_SERIAL_TEXT_DEBUG
#if defined(CONFIG_SERIAL_MPSC_CONSOLE)
	ppc_md.progress = mv64x60_mpsc_progress;
#elif defined(CONFIG_SERIAL_8250)
	ppc_md.progress = gen550_progress;
#else
#error CONFIG_KGDB || CONFIG_SERIAL_TEXT_DEBUG has no supported CONFIG_SERIAL_XXX
#endif /* CONFIG_SERIAL_8250 */
#endif /* CONFIG_SERIAL_TEXT_DEBUG */
#endif /* CONFIG_KGDB || CONFIG_SERIAL_TEXT_DEBUG */

	/* Enable write access to user flash.  This is necessary for
	 * flash probe.
	 */
	val8 = readb((void *)isa_io_base + PPC7D_CPLD_SW_FLASH_WRITE_PROTECT);
	writeb(val8 | (PPC7D_CPLD_SW_FLASH_WRPROT_ENABLED &
		       PPC7D_CPLD_SW_FLASH_WRPROT_USER_MASK),
	       (void *)isa_io_base + PPC7D_CPLD_SW_FLASH_WRITE_PROTECT);

	/* Determine if this board has IBM ALMA VME devices */
	val8 = readb((void *)isa_io_base + PPC7D_CPLD_BOARD_REVISION);
	rev_num = (val8 & PPC7D_CPLD_BOARD_REVISION_NUMBER_MASK) >> 5;
	if (rev_num <= 1)
		ppc7d_has_alma = 1;

#ifdef DEBUG
	console_printk[0] = 8;
#endif
}