radstone_ppc7d.c

linux-2.6.15.6

/*****************************************************************************
 * PCI device fixups.
 * These aren't really fixups per se. They are used to init devices as they
 * are found during PCI scan.
 *
 * The PPC7D has an HB8 PCI-X bridge which must be set up during a PCI
 * scan in order to find other devices on its secondary side.
 *****************************************************************************/

static void __init ppc7d_fixup_hb8(struct pci_dev *dev)
{
	u16 val16;

	if (dev->bus->number == 0) {
		pr_debug("PCI: HB8 init\n");

		pci_write_config_byte(dev, 0x1c,
				      ((PPC7D_PCI0_IO_START_PCI_ADDR & 0xf000)
				       >> 8) | 0x01);
		pci_write_config_byte(dev, 0x1d,
				      (((PPC7D_PCI0_IO_START_PCI_ADDR +
					 PPC7D_PCI0_IO_SIZE -
					 1) & 0xf000) >> 8) | 0x01);
		pci_write_config_word(dev, 0x30,
				      PPC7D_PCI0_IO_START_PCI_ADDR >> 16);
		pci_write_config_word(dev, 0x32,
				      ((PPC7D_PCI0_IO_START_PCI_ADDR +
					PPC7D_PCI0_IO_SIZE -
					1) >> 16) & 0xffff);

		pci_write_config_word(dev, 0x20,
				      PPC7D_PCI0_MEM0_START_PCI_LO_ADDR >> 16);
		pci_write_config_word(dev, 0x22,
				      ((PPC7D_PCI0_MEM0_START_PCI_LO_ADDR +
					PPC7D_PCI0_MEM0_SIZE -
					1) >> 16) & 0xffff);
		pci_write_config_word(dev, 0x24, 0);
		pci_write_config_word(dev, 0x26, 0);
		pci_write_config_dword(dev, 0x28, 0);
		pci_write_config_dword(dev, 0x2c, 0);

		pci_read_config_word(dev, 0x3e, &val16);
		val16 |= ((1 << 5) | (1 << 1));	/* signal master aborts and
						 * SERR to primary
						 */
		val16 &= ~(1 << 2);		/* ISA disable, so all ISA
						 * ports forwarded to secondary
						 */
		pci_write_config_word(dev, 0x3e, val16);
	}
}

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0028, ppc7d_fixup_hb8);

/* This should perhaps be a separate driver as we're actually initializing
 * the chip for this board here. It's hardly a fixup...
 */
static void __init ppc7d_fixup_ali1535(struct pci_dev *dev)
{
	pr_debug("PCI: ALI1535 init\n");

	if (dev->bus->number == 1) {
		/* Configure the ISA Port Settings */
		pci_write_config_byte(dev, 0x43, 0x00);

		/* Disable PCI Interrupt polling mode */
		pci_write_config_byte(dev, 0x45, 0x00);

		/* Multifunction pin select INTFJ -> INTF */
		pci_write_config_byte(dev, 0x78, 0x00);

		/* Set PCI INT -> IRQ Routing control in for external
		 * pins south bridge.
		 */
		pci_write_config_byte(dev, 0x48, 0x31);	/* [7-4] INT B -> IRQ10
							 * [3-0] INT A -> IRQ9
							 */
		pci_write_config_byte(dev, 0x49, 0x5D);	/* [7-4] INT D -> IRQ5
							 * [3-0] INT C -> IRQ14
							 */

		/* PPC7D setup */
		/* NEC USB device on IRQ 11 (INTE) - INTF disabled */
		pci_write_config_byte(dev, 0x4A, 0x09);

		/* GPIO on IRQ 6 */
		pci_write_config_byte(dev, 0x76, 0x07);

		/* SIRQ I (COMS 5/6) use IRQ line 15.
		 * Positive (not subtractive) address decode.
		 */
		pci_write_config_byte(dev, 0x44, 0x0f);

		/* SIRQ II disabled */
		pci_write_config_byte(dev, 0x75, 0x0);

		/* On board USB and RTC disabled */
		pci_write_config_word(dev, 0x52, (1 << 14));
		pci_write_config_byte(dev, 0x74, 0x00);

		/* On board IDE disabled */
		pci_write_config_byte(dev, 0x58, 0x00);

		/* Decode 32-bit addresses */
		pci_write_config_byte(dev, 0x5b, 0);

		/* Disable docking IO */
		pci_write_config_word(dev, 0x5c, 0x0000);

		/* Disable modem, enable sound */
		pci_write_config_byte(dev, 0x77, (1 << 6));

		/* Disable hot-docking mode */
		pci_write_config_byte(dev, 0x7d, 0x00);
	}
}

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1533, ppc7d_fixup_ali1535);

static int ppc7d_pci_exclude_device(u8 bus, u8 devfn)
{
	/* Early versions of this board were fitted with IBM ALMA
	 * PCI-VME bridge chips. The PCI config space of these devices
	 * was not set up correctly and causes PCI scan problems.
	 */
	if ((bus == 1) && (PCI_SLOT(devfn) == 4) && ppc7d_has_alma)
		return PCIBIOS_DEVICE_NOT_FOUND;

	return mv64x60_pci_exclude_device(bus, devfn);
}

/* This hook is called when each PCI bus is probed.
 */
static void ppc7d_pci_fixup_bus(struct pci_bus *bus)
{
	pr_debug("PCI BUS %hu: %lx/%lx %lx/%lx %lx/%lx %lx/%lx\n",
		 bus->number,
		 bus->resource[0] ? bus->resource[0]->start : 0,
		 bus->resource[0] ? bus->resource[0]->end : 0,
		 bus->resource[1] ? bus->resource[1]->start : 0,
		 bus->resource[1] ? bus->resource[1]->end : 0,
		 bus->resource[2] ? bus->resource[2]->start : 0,
		 bus->resource[2] ? bus->resource[2]->end : 0,
		 bus->resource[3] ? bus->resource[3]->start : 0,
		 bus->resource[3] ? bus->resource[3]->end : 0);

	if ((bus->number == 1) && (bus->resource[2] != NULL)) {
		/* Hide PCI window 2 of Bus 1 which is used only to
		 * map legacy ISA memory space.
		 */
		bus->resource[2]->start = 0;
		bus->resource[2]->end = 0;
		bus->resource[2]->flags = 0;
	}
}

/*****************************************************************************
 * Board device setup code
 *****************************************************************************/

void __init ppc7d_setup_peripherals(void)
{
	u32 val32;

	/* Set up windows for boot CS */
	mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
				 PPC7D_BOOT_WINDOW_BASE, PPC7D_BOOT_WINDOW_SIZE,
				 0);
	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);

	/* Boot firmware configures the following DevCS addresses.
	 * DevCS0 - board control/status
	 * DevCS1 - test registers
	 * DevCS2 - AFIX port/address registers (for identifying)
	 * DevCS3 - FLASH
	 *
	 * We don't use DevCS0, DevCS1.
	 */
	val32 = mv64x60_read(&bh, MV64360_CPU_BAR_ENABLE);
	val32 |= ((1 << 4) | (1 << 5));
	mv64x60_write(&bh, MV64360_CPU_BAR_ENABLE, val32);
	mv64x60_write(&bh, MV64x60_CPU2DEV_0_BASE, 0);
	mv64x60_write(&bh, MV64x60_CPU2DEV_0_SIZE, 0);
	mv64x60_write(&bh, MV64x60_CPU2DEV_1_BASE, 0);
	mv64x60_write(&bh, MV64x60_CPU2DEV_1_SIZE, 0);

	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN,
				 PPC7D_AFIX_REG_BASE, PPC7D_AFIX_REG_SIZE, 0);
	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN);

	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_3_WIN,
				 PPC7D_FLASH_BASE, PPC7D_FLASH_SIZE_ACTUAL, 0);
	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_3_WIN);

	mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
				 PPC7D_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE,
				 0);
	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);

	/* Set up Enet->SRAM window */
	mv64x60_set_32bit_window(&bh, MV64x60_ENET2MEM_4_WIN,
				 PPC7D_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE,
				 0x2);
	bh.ci->enable_window_32bit(&bh, MV64x60_ENET2MEM_4_WIN);

	/* Give enet r/w access to memory region */
	val32 = mv64x60_read(&bh, MV64360_ENET2MEM_ACC_PROT_0);
	val32 |= (0x3 << (4 << 1));
	mv64x60_write(&bh, MV64360_ENET2MEM_ACC_PROT_0, val32);
	val32 = mv64x60_read(&bh, MV64360_ENET2MEM_ACC_PROT_1);
	val32 |= (0x3 << (4 << 1));
	mv64x60_write(&bh, MV64360_ENET2MEM_ACC_PROT_1, val32);
	val32 = mv64x60_read(&bh, MV64360_ENET2MEM_ACC_PROT_2);
	val32 |= (0x3 << (4 << 1));
	mv64x60_write(&bh, MV64360_ENET2MEM_ACC_PROT_2, val32);

	val32 = mv64x60_read(&bh, MV64x60_TIMR_CNTR_0_3_CNTL);
	val32 &= ~((1 << 0) | (1 << 8) | (1 << 16) | (1 << 24));
	mv64x60_write(&bh, MV64x60_TIMR_CNTR_0_3_CNTL, val32);

	/* Enumerate pci bus.
	 *
	 * We scan PCI#0 first (the bus with the HB8 and other
	 * on-board peripherals). We must configure the 64360 before
	 * each scan, according to the bus number assignments.  Busses
	 * are assigned incrementally, starting at 0.  PCI#0 is
	 * usually assigned bus#0, the secondary side of the HB8 gets
	 * bus#1 and PCI#1 (second PMC site) gets bus#2.  However, if
	 * any PMC card has a PCI bridge, these bus assignments will
	 * change.
	 */

	/* Turn off PCI retries */
	val32 = mv64x60_read(&bh, MV64x60_CPU_CONFIG);
	val32 |= (1 << 17);
	mv64x60_write(&bh, MV64x60_CPU_CONFIG, val32);

	/* Scan PCI#0 */
	mv64x60_set_bus(&bh, 0, 0);
	bh.hose_a->first_busno = 0;
	bh.hose_a->last_busno = 0xff;
	bh.hose_a->last_busno = pciauto_bus_scan(bh.hose_a, 0);
	printk(KERN_INFO "PCI#0: first=%d last=%d\n",
	       bh.hose_a->first_busno, bh.hose_a->last_busno);

	/* Scan PCI#1 */
	bh.hose_b->first_busno = bh.hose_a->last_busno + 1;
	mv64x60_set_bus(&bh, 1, bh.hose_b->first_busno);
	bh.hose_b->last_busno = 0xff;
	bh.hose_b->last_busno = pciauto_bus_scan(bh.hose_b,
		bh.hose_b->first_busno);
	printk(KERN_INFO "PCI#1: first=%d last=%d\n",
	       bh.hose_b->first_busno, bh.hose_b->last_busno);

	/* Turn on PCI retries */
	val32 = mv64x60_read(&bh, MV64x60_CPU_CONFIG);
	val32 &= ~(1 << 17);
	mv64x60_write(&bh, MV64x60_CPU_CONFIG, val32);

	/* Setup interrupts */
	ppc7d_intr_setup();
}

static void __init ppc7d_setup_bridge(void)
{
	struct mv64x60_setup_info si;
	int i;
	u32 temp;

	mv64360_irq_base = 16;	/* first 16 intrs are 2 x 8259's */

	memset(&si, 0, sizeof(si));

	si.phys_reg_base = CONFIG_MV64X60_NEW_BASE;

	si.pci_0.enable_bus = 1;
	si.pci_0.pci_io.cpu_base = PPC7D_PCI0_IO_START_PROC_ADDR;
	si.pci_0.pci_io.pci_base_hi = 0;
	si.pci_0.pci_io.pci_base_lo = PPC7D_PCI0_IO_START_PCI_ADDR;
	si.pci_0.pci_io.size = PPC7D_PCI0_IO_SIZE;
	si.pci_0.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
	si.pci_0.pci_mem[0].cpu_base = PPC7D_PCI0_MEM0_START_PROC_ADDR;
	si.pci_0.pci_mem[0].pci_base_hi = PPC7D_PCI0_MEM0_START_PCI_HI_ADDR;
	si.pci_0.pci_mem[0].pci_base_lo = PPC7D_PCI0_MEM0_START_PCI_LO_ADDR;
	si.pci_0.pci_mem[0].size = PPC7D_PCI0_MEM0_SIZE;
	si.pci_0.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
	si.pci_0.pci_mem[1].cpu_base = PPC7D_PCI0_MEM1_START_PROC_ADDR;
	si.pci_0.pci_mem[1].pci_base_hi = PPC7D_PCI0_MEM1_START_PCI_HI_ADDR;
	si.pci_0.pci_mem[1].pci_base_lo = PPC7D_PCI0_MEM1_START_PCI_LO_ADDR;
	si.pci_0.pci_mem[1].size = PPC7D_PCI0_MEM1_SIZE;
	si.pci_0.pci_mem[1].swap = MV64x60_CPU2PCI_SWAP_NONE;
	si.pci_0.pci_cmd_bits = 0;
	si.pci_0.latency_timer = 0x80;

	si.pci_1.enable_bus = 1;
	si.pci_1.pci_io.cpu_base = PPC7D_PCI1_IO_START_PROC_ADDR;
	si.pci_1.pci_io.pci_base_hi = 0;
	si.pci_1.pci_io.pci_base_lo = PPC7D_PCI1_IO_START_PCI_ADDR;
	si.pci_1.pci_io.size = PPC7D_PCI1_IO_SIZE;
	si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
	si.pci_1.pci_mem[0].cpu_base = PPC7D_PCI1_MEM0_START_PROC_ADDR;
	si.pci_1.pci_mem[0].pci_base_hi = PPC7D_PCI1_MEM0_START_PCI_HI_ADDR;
	si.pci_1.pci_mem[0].pci_base_lo = PPC7D_PCI1_MEM0_START_PCI_LO_ADDR;
	si.pci_1.pci_mem[0].size = PPC7D_PCI1_MEM0_SIZE;
	si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
	si.pci_1.pci_mem[1].cpu_base = PPC7D_PCI1_MEM1_START_PROC_ADDR;
	si.pci_1.pci_mem[1].pci_base_hi = PPC7D_PCI1_MEM1_START_PCI_HI_ADDR;
	si.pci_1.pci_mem[1].pci_base_lo = PPC7D_PCI1_MEM1_START_PCI_LO_ADDR;
	si.pci_1.pci_mem[1].size = PPC7D_PCI1_MEM1_SIZE;
	si.pci_1.pci_mem[1].swap = MV64x60_CPU2PCI_SWAP_NONE;
	si.pci_1.pci_cmd_bits = 0;
	si.pci_1.latency_timer = 0x80;

	/* Don't clear the SRAM window since we use it for debug */
	si.window_preserve_mask_32_lo = (1 << MV64x60_CPU2SRAM_WIN);

	printk(KERN_INFO "PCI: MV64360 PCI#0 IO at %x, size %x\n",
	       si.pci_0.pci_io.cpu_base, si.pci_0.pci_io.size);
	printk(KERN_INFO "PCI: MV64360 PCI#1 IO at %x, size %x\n",
	       si.pci_1.pci_io.cpu_base, si.pci_1.pci_io.size);

	for (i = 0; i < MV64x60_CPU2MEM_WINDOWS; i++) {
#if defined(CONFIG_NOT_COHERENT_CACHE)
		si.cpu_prot_options[i] = 0;
		si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE;
		si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE;
		si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE;

		si.pci_0.acc_cntl_options[i] =
		    MV64360_PCI_ACC_CNTL_SNOOP_NONE |
		    MV64360_PCI_ACC_CNTL_SWAP_NONE |
		    MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
		    MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;

		si.pci_1.acc_cntl_options[i] =
		    MV64360_PCI_ACC_CNTL_SNOOP_NONE |
		    MV64360_PCI_ACC_CNTL_SWAP_NONE |
		    MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
		    MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
#else
		si.cpu_prot_options[i] = 0;
		/* All PPC7D hardware uses B0 or newer MV64360 silicon which
		 * does not have snoop bugs.
		 */
		si.enet_options[i] = MV64360_ENET2MEM_SNOOP_WB;
		si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_WB;
		si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_WB;

		si.pci_0.acc_cntl_options[i] =
		    MV64360_PCI_ACC_CNTL_SNOOP_WB |
		    MV64360_PCI_ACC_CNTL_SWAP_NONE |
		    MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
		    MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES;

		si.pci_1.acc_cntl_options[i] =
		    MV64360_PCI_ACC_CNTL_SNOOP_WB |
		    MV64360_PCI_ACC_CNTL_SWAP_NONE |
		    MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
		    MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES;
#endif
	}

	/* Lookup PCI host bridges */
	if (mv64x60_init(&bh, &si))
		printk(KERN_ERR "MV64360 initialization failed.\n");

	pr_debug("MV64360 regs @ %lx/%p\n", bh.p_base, bh.v_base);

	/* Enable WB Cache coherency on SRAM */
	temp = mv64x60_read(&bh, MV64360_SRAM_CONFIG);
	pr_debug("SRAM_CONFIG: %x\n", temp);
#if defined(CONFIG_NOT_COHERENT_CACHE)
	mv64x60_write(&bh, MV64360_SRAM_CONFIG, temp & ~0x2);
#else
	mv64x60_write(&bh, MV64360_SRAM_CONFIG, temp | 0x2);