radstone_ppc7d.c

linux-2.6.15.6

			"16-bit SCSI + VGA",
			"1553 (Single Channel with sideband)",
			"1553 (Dual Channel with sideband)",
			NULL
		};
		u8 id = __raw_readb((void *)PPC7D_AFIX_REG_BASE + 0x03);
		seq_printf(m, "AFIX module\t: 0x%hx [%s]\n", id,
			   id < 7 ? ids[id] : "unknown");
	}

	val = inb(PPC7D_CPLD_PCI_CONFIG);
	val1 = (val & PPC7D_CPLD_PCI_CONFIG_PCI0_MASK) >> 4;
	val2 = (val & PPC7D_CPLD_PCI_CONFIG_PCI1_MASK);
	seq_printf(m, "PCI#0\t\t: %s\nPCI#1\t\t: %s\n",
		   pci_modes[val1], pci_modes[val2]);

	val = inb(PPC7D_CPLD_EQUIPMENT_PRESENT_2);
	seq_printf(m, "PMC1\t\t: %s\nPMC2\t\t: %s\n",
		   (val & PPC7D_CPLD_EQPT_PRES_3_PMC1_V_MASK) ? "3.3v" : "5v",
		   (val & PPC7D_CPLD_EQPT_PRES_3_PMC2_V_MASK) ? "3.3v" : "5v");
	seq_printf(m, "PMC power source: %s\n",
		   (val & PPC7D_CPLD_EQPT_PRES_3_PMC_POWER_MASK) ? "VME" :
		   "internal");

	val = inb(PPC7D_CPLD_EQUIPMENT_PRESENT_4);
	val2 = inb(PPC7D_CPLD_EQUIPMENT_PRESENT_2);
	seq_printf(m, "Fit options\t: %s%s%s%s%s%s%s\n",
		   (val & PPC7D_CPLD_EQPT_PRES_4_LPT_MASK) ? "LPT " : "",
		   (val & PPC7D_CPLD_EQPT_PRES_4_PS2_FITTED) ? "PS2 " : "",
		   (val & PPC7D_CPLD_EQPT_PRES_4_USB2_FITTED) ? "USB2 " : "",
		   (val2 & PPC7D_CPLD_EQPT_PRES_2_UNIVERSE_MASK) ? "VME " : "",
		   (val2 & PPC7D_CPLD_EQPT_PRES_2_COM36_MASK) ? "COM3-6 " : "",
		   (val2 & PPC7D_CPLD_EQPT_PRES_2_GIGE_MASK) ? "eth0 " : "",
		   (val2 & PPC7D_CPLD_EQPT_PRES_2_DUALGIGE_MASK) ? "eth1 " :
		   "");

	val = inb(PPC7D_CPLD_ID_LINK);
	val1 = val & (PPC7D_CPLD_ID_LINK_E6_MASK |
		      PPC7D_CPLD_ID_LINK_E7_MASK |
		      PPC7D_CPLD_ID_LINK_E12_MASK |
		      PPC7D_CPLD_ID_LINK_E13_MASK);

	val = inb(PPC7D_CPLD_FLASH_WRITE_CNTL) &
	    (PPD7D_CPLD_FLASH_CNTL_WR_LINK_MASK |
	     PPD7D_CPLD_FLASH_CNTL_BOOT_LINK_MASK |
	     PPD7D_CPLD_FLASH_CNTL_USER_LINK_MASK);

	seq_printf(m, "Board links present: %s%s%s%s%s%s%s%s\n",
		   (val1 & PPC7D_CPLD_ID_LINK_E6_MASK) ? "E6 " : "",
		   (val1 & PPC7D_CPLD_ID_LINK_E7_MASK) ? "E7 " : "",
		   (val & PPD7D_CPLD_FLASH_CNTL_WR_LINK_MASK) ? "E9 " : "",
		   (val & PPD7D_CPLD_FLASH_CNTL_BOOT_LINK_MASK) ? "E10 " : "",
		   (val & PPD7D_CPLD_FLASH_CNTL_USER_LINK_MASK) ? "E11 " : "",
		   (val1 & PPC7D_CPLD_ID_LINK_E12_MASK) ? "E12 " : "",
		   (val1 & PPC7D_CPLD_ID_LINK_E13_MASK) ? "E13 " : "",
		   ((val == 0) && (val1 == 0)) ? "NONE" : "");

	val = inb(PPC7D_CPLD_WDOG_RESETSW_MASK);
	seq_printf(m, "Front panel reset switch: %sabled\n",
		   (val & PPC7D_CPLD_WDOG_RESETSW_MASK) ? "dis" : "en");

	return 0;
}

static void __init ppc7d_calibrate_decr(void)
{
	ulong freq;

	freq = 100000000 / 4;

	pr_debug("time_init: decrementer frequency = %lu.%.6lu MHz\n",
		 freq / 1000000, freq % 1000000);

	tb_ticks_per_jiffy = freq / HZ;
	tb_to_us = mulhwu_scale_factor(freq, 1000000);
}

/*****************************************************************************
 * Interrupt stuff
 *****************************************************************************/

static irqreturn_t ppc7d_i8259_intr(int irq, void *dev_id, struct pt_regs *regs)
{
	u32 temp = mv64x60_read(&bh, MV64x60_GPP_INTR_CAUSE);
	if (temp & (1 << 28)) {
		i8259_irq(regs);
		mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, temp & (~(1 << 28)));
		return IRQ_HANDLED;
	}

	return IRQ_NONE;
}

/*
 * Each interrupt cause is assigned an IRQ number.
 * Southbridge has 16*2 (two 8259's) interrupts.
 * Discovery-II has 96 interrupts (cause-hi, cause-lo, gpp x 32).
 * If multiple interrupts are pending, get_irq() returns the
 * lowest pending irq number first.
 *
 *
 * IRQ #   Source                              Trig   Active
 * =============================================================
 *
 * Southbridge
 * -----------
 * IRQ #   Source                              Trig
 * =============================================================
 * 0       ISA High Resolution Counter         Edge
 * 1       Keyboard                            Edge
 * 2       Cascade From (IRQ 8-15)             Edge
 * 3       Com 2 (Uart 2)                      Edge
 * 4       Com 1 (Uart 1)                      Edge
 * 5       PCI Int D/AFIX IRQZ ID4 (2,7)       Level
 * 6       GPIO                                Level
 * 7       LPT                                 Edge
 * 8       RTC Alarm                           Edge
 * 9       PCI Int A/PMC 2/AFIX IRQW ID1 (2,0) Level
 * 10      PCI Int B/PMC 1/AFIX IRQX ID2 (2,1) Level
 * 11      USB2                                Level
 * 12      Mouse                               Edge
 * 13      Reserved internally by Ali M1535+
 * 14      PCI Int C/VME/AFIX IRQY ID3 (2,6)   Level
 * 15      COM 5/6                             Level
 *
 * 16..112 Discovery-II...
 *
 * MPP28   Southbridge                         Edge   High
 *
 *
 * Interrupts are cascaded through to the Discovery-II.
 *
 *  PCI ---
 *         \
 * CPLD --> ALI1535 -------> DISCOVERY-II
 *        INTF           MPP28
 */
static void __init ppc7d_init_irq(void)
{
	int irq;

	pr_debug("%s\n", __FUNCTION__);
	i8259_init(0, 0);
	mv64360_init_irq();

	/* IRQs 5,6,9,10,11,14,15 are level sensitive */
	irq_desc[5].status |= IRQ_LEVEL;
	irq_desc[6].status |= IRQ_LEVEL;
	irq_desc[9].status |= IRQ_LEVEL;
	irq_desc[10].status |= IRQ_LEVEL;
	irq_desc[11].status |= IRQ_LEVEL;
	irq_desc[14].status |= IRQ_LEVEL;
	irq_desc[15].status |= IRQ_LEVEL;

	/* GPP28 is edge triggered */
	irq_desc[mv64360_irq_base + MV64x60_IRQ_GPP28].status &= ~IRQ_LEVEL;
}

static u32 ppc7d_irq_canonicalize(u32 irq)
{
	if ((irq >= 16) && (irq < (16 + 96)))
		irq -= 16;

	return irq;
}

static int ppc7d_get_irq(struct pt_regs *regs)
{
	int irq;

	irq = mv64360_get_irq(regs);
	if (irq == (mv64360_irq_base + MV64x60_IRQ_GPP28))
		irq = i8259_irq(regs);
	return irq;
}

/*
 * 9       PCI Int A/PMC 2/AFIX IRQW ID1 (2,0) Level
 * 10      PCI Int B/PMC 1/AFIX IRQX ID2 (2,1) Level
 * 14      PCI Int C/VME/AFIX IRQY ID3 (2,6)   Level
 * 5       PCI Int D/AFIX IRQZ ID4 (2,7)       Level
 */
static int __init ppc7d_map_irq(struct pci_dev *dev, unsigned char idsel,
				unsigned char pin)
{
	static const char pci_irq_table[][4] =
	    /*
	     *      PCI IDSEL/INTPIN->INTLINE
	     *         A   B   C   D
	     */
	{
		{10, 14, 5, 9},	/* IDSEL 10 - PMC2 / AFIX IRQW */
		{9, 10, 14, 5},	/* IDSEL 11 - PMC1 / AFIX IRQX */
		{5, 9, 10, 14},	/* IDSEL 12 - AFIX IRQY */
		{14, 5, 9, 10},	/* IDSEL 13 - AFIX IRQZ */
	};
	const long min_idsel = 10, max_idsel = 14, irqs_per_slot = 4;

	pr_debug("%s: %04x/%04x/%x: idsel=%hx pin=%hu\n", __FUNCTION__,
		 dev->vendor, dev->device, PCI_FUNC(dev->devfn), idsel, pin);

	return PCI_IRQ_TABLE_LOOKUP;
}

void __init ppc7d_intr_setup(void)
{
	u32 data;

	/*
	 * Define GPP 28 interrupt polarity as active high
	 * input signal and level triggered
	 */
	data = mv64x60_read(&bh, MV64x60_GPP_LEVEL_CNTL);
	data &= ~(1 << 28);
	mv64x60_write(&bh, MV64x60_GPP_LEVEL_CNTL, data);
	data = mv64x60_read(&bh, MV64x60_GPP_IO_CNTL);
	data &= ~(1 << 28);
	mv64x60_write(&bh, MV64x60_GPP_IO_CNTL, data);

	/* Config GPP intr ctlr to respond to level trigger */
	data = mv64x60_read(&bh, MV64x60_COMM_ARBITER_CNTL);
	data |= (1 << 10);
	mv64x60_write(&bh, MV64x60_COMM_ARBITER_CNTL, data);

	/* XXXX Erranum FEr PCI-#8 */
	data = mv64x60_read(&bh, MV64x60_PCI0_CMD);
	data &= ~((1 << 5) | (1 << 9));
	mv64x60_write(&bh, MV64x60_PCI0_CMD, data);
	data = mv64x60_read(&bh, MV64x60_PCI1_CMD);
	data &= ~((1 << 5) | (1 << 9));
	mv64x60_write(&bh, MV64x60_PCI1_CMD, data);

	/*
	 * Dismiss and then enable interrupt on GPP interrupt cause
	 * for CPU #0
	 */
	mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~(1 << 28));
	data = mv64x60_read(&bh, MV64x60_GPP_INTR_MASK);
	data |= (1 << 28);
	mv64x60_write(&bh, MV64x60_GPP_INTR_MASK, data);

	/*
	 * Dismiss and then enable interrupt on CPU #0 high cause reg
	 * BIT27 summarizes GPP interrupts 23-31
	 */
	mv64x60_write(&bh, MV64360_IC_MAIN_CAUSE_HI, ~(1 << 27));
	data = mv64x60_read(&bh, MV64360_IC_CPU0_INTR_MASK_HI);
	data |= (1 << 27);
	mv64x60_write(&bh, MV64360_IC_CPU0_INTR_MASK_HI, data);
}

/*****************************************************************************
 * Platform device data fixup routines.
 *****************************************************************************/

#if defined(CONFIG_SERIAL_MPSC)
static void __init ppc7d_fixup_mpsc_pdata(struct platform_device *pdev)
{
	struct mpsc_pdata *pdata;

	pdata = (struct mpsc_pdata *)pdev->dev.platform_data;

	pdata->max_idle = 40;
	pdata->default_baud = PPC7D_DEFAULT_BAUD;
	pdata->brg_clk_src = PPC7D_MPSC_CLK_SRC;
	pdata->brg_clk_freq = PPC7D_MPSC_CLK_FREQ;

	return;
}
#endif

#if defined(CONFIG_MV643XX_ETH)
static void __init ppc7d_fixup_eth_pdata(struct platform_device *pdev)
{
	struct mv643xx_eth_platform_data *eth_pd;
	static u16 phy_addr[] = {
		PPC7D_ETH0_PHY_ADDR,
		PPC7D_ETH1_PHY_ADDR,
		PPC7D_ETH2_PHY_ADDR,
	};
	int i;

	eth_pd = pdev->dev.platform_data;
	eth_pd->force_phy_addr = 1;
	eth_pd->phy_addr = phy_addr[pdev->id];
	eth_pd->tx_queue_size = PPC7D_ETH_TX_QUEUE_SIZE;
	eth_pd->rx_queue_size = PPC7D_ETH_RX_QUEUE_SIZE;

	/* Adjust IRQ by mv64360_irq_base */
	for (i = 0; i < pdev->num_resources; i++) {
		struct resource *r = &pdev->resource[i];

		if (r->flags & IORESOURCE_IRQ) {
			r->start += mv64360_irq_base;
			r->end += mv64360_irq_base;
			pr_debug("%s, uses IRQ %d\n", pdev->name,
				 (int)r->start);
		}
	}

}
#endif

#if defined(CONFIG_I2C_MV64XXX)
static void __init
ppc7d_fixup_i2c_pdata(struct platform_device *pdev)
{
	struct mv64xxx_i2c_pdata *pdata;
	int i;

	pdata = pdev->dev.platform_data;
	if (pdata == NULL) {
		pdata = kmalloc(sizeof(*pdata), GFP_KERNEL);
		if (pdata == NULL)
			return;

		memset(pdata, 0, sizeof(*pdata));
		pdev->dev.platform_data = pdata;
	}

	/* divisors M=8, N=3 for 100kHz I2C from 133MHz system clock */
	pdata->freq_m = 8;
	pdata->freq_n = 3;
	pdata->timeout = 500;
	pdata->retries = 3;

	/* Adjust IRQ by mv64360_irq_base */
	for (i = 0; i < pdev->num_resources; i++) {
		struct resource *r = &pdev->resource[i];

		if (r->flags & IORESOURCE_IRQ) {
			r->start += mv64360_irq_base;
			r->end += mv64360_irq_base;
			pr_debug("%s, uses IRQ %d\n", pdev->name, (int) r->start);
		}
	}
}
#endif

static int __init ppc7d_platform_notify(struct device *dev)
{
	static struct {
		char *bus_id;
		void ((*rtn) (struct platform_device * pdev));
	} dev_map[] = {
#if defined(CONFIG_SERIAL_MPSC)
		{ MPSC_CTLR_NAME ".0", ppc7d_fixup_mpsc_pdata },
		{ MPSC_CTLR_NAME ".1", ppc7d_fixup_mpsc_pdata },
#endif
#if defined(CONFIG_MV643XX_ETH)
		{ MV643XX_ETH_NAME ".0", ppc7d_fixup_eth_pdata },
		{ MV643XX_ETH_NAME ".1", ppc7d_fixup_eth_pdata },
		{ MV643XX_ETH_NAME ".2", ppc7d_fixup_eth_pdata },
#endif
#if defined(CONFIG_I2C_MV64XXX)
		{ MV64XXX_I2C_CTLR_NAME ".0", ppc7d_fixup_i2c_pdata },
#endif
	};
	struct platform_device *pdev;
	int i;

	if (dev && dev->bus_id)
		for (i = 0; i < ARRAY_SIZE(dev_map); i++)
			if (!strncmp(dev->bus_id, dev_map[i].bus_id,
				     BUS_ID_SIZE)) {

				pdev = container_of(dev,
						    struct platform_device,
						    dev);
				dev_map[i].rtn(pdev);
			}

	return 0;
}