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📄 srmmu.c

📁 linux-2.6.15.6
💻 C
📖 第 1 页 / 共 5 页
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/* * srmmu.c:  SRMMU specific routines for memory management. * * Copyright (C) 1995 David S. Miller  (davem@caip.rutgers.edu) * Copyright (C) 1995,2002 Pete Zaitcev (zaitcev@yahoo.com) * Copyright (C) 1996 Eddie C. Dost    (ecd@skynet.be) * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz) * Copyright (C) 1999,2000 Anton Blanchard (anton@samba.org) */#include <linux/config.h>#include <linux/kernel.h>#include <linux/mm.h>#include <linux/slab.h>#include <linux/vmalloc.h>#include <linux/pagemap.h>#include <linux/init.h>#include <linux/spinlock.h>#include <linux/bootmem.h>#include <linux/fs.h>#include <linux/seq_file.h>#include <asm/bitext.h>#include <asm/page.h>#include <asm/pgalloc.h>#include <asm/pgtable.h>#include <asm/io.h>#include <asm/kdebug.h>#include <asm/vaddrs.h>#include <asm/traps.h>#include <asm/smp.h>#include <asm/mbus.h>#include <asm/cache.h>#include <asm/oplib.h>#include <asm/sbus.h>#include <asm/asi.h>#include <asm/msi.h>#include <asm/a.out.h>#include <asm/mmu_context.h>#include <asm/io-unit.h>#include <asm/cacheflush.h>#include <asm/tlbflush.h>/* Now the cpu specific definitions. */#include <asm/viking.h>#include <asm/mxcc.h>#include <asm/ross.h>#include <asm/tsunami.h>#include <asm/swift.h>#include <asm/turbosparc.h>#include <asm/btfixup.h>enum mbus_module srmmu_modtype;unsigned int hwbug_bitmask;int vac_cache_size;int vac_line_size;extern struct resource sparc_iomap;extern unsigned long last_valid_pfn;extern unsigned long page_kernel;pgd_t *srmmu_swapper_pg_dir;#ifdef CONFIG_SMP#define FLUSH_BEGIN(mm)#define FLUSH_END#else#define FLUSH_BEGIN(mm) if((mm)->context != NO_CONTEXT) {#define FLUSH_END	}#endifBTFIXUPDEF_CALL(void, flush_page_for_dma, unsigned long)#define flush_page_for_dma(page) BTFIXUP_CALL(flush_page_for_dma)(page)int flush_page_for_dma_global = 1;#ifdef CONFIG_SMPBTFIXUPDEF_CALL(void, local_flush_page_for_dma, unsigned long)#define local_flush_page_for_dma(page) BTFIXUP_CALL(local_flush_page_for_dma)(page)#endifchar *srmmu_name;ctxd_t *srmmu_ctx_table_phys;ctxd_t *srmmu_context_table;int viking_mxcc_present;static DEFINE_SPINLOCK(srmmu_context_spinlock);int is_hypersparc;/* * In general all page table modifications should use the V8 atomic * swap instruction.  This insures the mmu and the cpu are in sync * with respect to ref/mod bits in the page tables. */static inline unsigned long srmmu_swap(unsigned long *addr, unsigned long value){	__asm__ __volatile__("swap [%2], %0" : "=&r" (value) : "0" (value), "r" (addr));	return value;}static inline void srmmu_set_pte(pte_t *ptep, pte_t pteval){	srmmu_swap((unsigned long *)ptep, pte_val(pteval));}/* The very generic SRMMU page table operations. */static inline int srmmu_device_memory(unsigned long x){	return ((x & 0xF0000000) != 0);}int srmmu_cache_pagetables;/* these will be initialized in srmmu_nocache_calcsize() */unsigned long srmmu_nocache_size;unsigned long srmmu_nocache_end;/* 1 bit <=> 256 bytes of nocache <=> 64 PTEs */#define SRMMU_NOCACHE_BITMAP_SHIFT (PAGE_SHIFT - 4)/* The context table is a nocache user with the biggest alignment needs. */#define SRMMU_NOCACHE_ALIGN_MAX (sizeof(ctxd_t)*SRMMU_MAX_CONTEXTS)void *srmmu_nocache_pool;void *srmmu_nocache_bitmap;static struct bit_map srmmu_nocache_map;static unsigned long srmmu_pte_pfn(pte_t pte){	if (srmmu_device_memory(pte_val(pte))) {		/* Just return something that will cause		 * pfn_valid() to return false.  This makes		 * copy_one_pte() to just directly copy to		 * PTE over.		 */		return ~0UL;	}	return (pte_val(pte) & SRMMU_PTE_PMASK) >> (PAGE_SHIFT-4);}static struct page *srmmu_pmd_page(pmd_t pmd){	if (srmmu_device_memory(pmd_val(pmd)))		BUG();	return pfn_to_page((pmd_val(pmd) & SRMMU_PTD_PMASK) >> (PAGE_SHIFT-4));}static inline unsigned long srmmu_pgd_page(pgd_t pgd){ return srmmu_device_memory(pgd_val(pgd))?~0:(unsigned long)__nocache_va((pgd_val(pgd) & SRMMU_PTD_PMASK) << 4); }static inline int srmmu_pte_none(pte_t pte){ return !(pte_val(pte) & 0xFFFFFFF); }static inline int srmmu_pte_present(pte_t pte){ return ((pte_val(pte) & SRMMU_ET_MASK) == SRMMU_ET_PTE); }static inline int srmmu_pte_read(pte_t pte){ return !(pte_val(pte) & SRMMU_NOREAD); }static inline void srmmu_pte_clear(pte_t *ptep){ srmmu_set_pte(ptep, __pte(0)); }static inline int srmmu_pmd_none(pmd_t pmd){ return !(pmd_val(pmd) & 0xFFFFFFF); }static inline int srmmu_pmd_bad(pmd_t pmd){ return (pmd_val(pmd) & SRMMU_ET_MASK) != SRMMU_ET_PTD; }static inline int srmmu_pmd_present(pmd_t pmd){ return ((pmd_val(pmd) & SRMMU_ET_MASK) == SRMMU_ET_PTD); }static inline void srmmu_pmd_clear(pmd_t *pmdp) {	int i;	for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++)		srmmu_set_pte((pte_t *)&pmdp->pmdv[i], __pte(0));}static inline int srmmu_pgd_none(pgd_t pgd)          { return !(pgd_val(pgd) & 0xFFFFFFF); }static inline int srmmu_pgd_bad(pgd_t pgd){ return (pgd_val(pgd) & SRMMU_ET_MASK) != SRMMU_ET_PTD; }static inline int srmmu_pgd_present(pgd_t pgd){ return ((pgd_val(pgd) & SRMMU_ET_MASK) == SRMMU_ET_PTD); }static inline void srmmu_pgd_clear(pgd_t * pgdp){ srmmu_set_pte((pte_t *)pgdp, __pte(0)); }static inline pte_t srmmu_pte_wrprotect(pte_t pte){ return __pte(pte_val(pte) & ~SRMMU_WRITE);}static inline pte_t srmmu_pte_mkclean(pte_t pte){ return __pte(pte_val(pte) & ~SRMMU_DIRTY);}static inline pte_t srmmu_pte_mkold(pte_t pte){ return __pte(pte_val(pte) & ~SRMMU_REF);}static inline pte_t srmmu_pte_mkwrite(pte_t pte){ return __pte(pte_val(pte) | SRMMU_WRITE);}static inline pte_t srmmu_pte_mkdirty(pte_t pte){ return __pte(pte_val(pte) | SRMMU_DIRTY);}static inline pte_t srmmu_pte_mkyoung(pte_t pte){ return __pte(pte_val(pte) | SRMMU_REF);}/* * Conversion functions: convert a page and protection to a page entry, * and a page entry and page directory to the page they refer to. */static pte_t srmmu_mk_pte(struct page *page, pgprot_t pgprot){ return __pte((page_to_pfn(page) << (PAGE_SHIFT-4)) | pgprot_val(pgprot)); }static pte_t srmmu_mk_pte_phys(unsigned long page, pgprot_t pgprot){ return __pte(((page) >> 4) | pgprot_val(pgprot)); }static pte_t srmmu_mk_pte_io(unsigned long page, pgprot_t pgprot, int space){ return __pte(((page) >> 4) | (space << 28) | pgprot_val(pgprot)); }/* XXX should we hyper_flush_whole_icache here - Anton */static inline void srmmu_ctxd_set(ctxd_t *ctxp, pgd_t *pgdp){ srmmu_set_pte((pte_t *)ctxp, (SRMMU_ET_PTD | (__nocache_pa((unsigned long) pgdp) >> 4))); }static inline void srmmu_pgd_set(pgd_t * pgdp, pmd_t * pmdp){ srmmu_set_pte((pte_t *)pgdp, (SRMMU_ET_PTD | (__nocache_pa((unsigned long) pmdp) >> 4))); }static void srmmu_pmd_set(pmd_t *pmdp, pte_t *ptep){	unsigned long ptp;	/* Physical address, shifted right by 4 */	int i;	ptp = __nocache_pa((unsigned long) ptep) >> 4;	for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++) {		srmmu_set_pte((pte_t *)&pmdp->pmdv[i], SRMMU_ET_PTD | ptp);		ptp += (SRMMU_REAL_PTRS_PER_PTE*sizeof(pte_t) >> 4);	}}static void srmmu_pmd_populate(pmd_t *pmdp, struct page *ptep){	unsigned long ptp;	/* Physical address, shifted right by 4 */	int i;	ptp = page_to_pfn(ptep) << (PAGE_SHIFT-4);	/* watch for overflow */	for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++) {		srmmu_set_pte((pte_t *)&pmdp->pmdv[i], SRMMU_ET_PTD | ptp);		ptp += (SRMMU_REAL_PTRS_PER_PTE*sizeof(pte_t) >> 4);	}}static inline pte_t srmmu_pte_modify(pte_t pte, pgprot_t newprot){ return __pte((pte_val(pte) & SRMMU_CHG_MASK) | pgprot_val(newprot)); }/* to find an entry in a top-level page table... */static inline pgd_t *srmmu_pgd_offset(struct mm_struct * mm, unsigned long address){ return mm->pgd + (address >> SRMMU_PGDIR_SHIFT); }/* Find an entry in the second-level page table.. */static inline pmd_t *srmmu_pmd_offset(pgd_t * dir, unsigned long address){	return (pmd_t *) srmmu_pgd_page(*dir) +	    ((address >> PMD_SHIFT) & (PTRS_PER_PMD - 1));}/* Find an entry in the third-level page table.. */ static inline pte_t *srmmu_pte_offset(pmd_t * dir, unsigned long address){	void *pte;	pte = __nocache_va((dir->pmdv[0] & SRMMU_PTD_PMASK) << 4);	return (pte_t *) pte +	    ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1));}static unsigned long srmmu_swp_type(swp_entry_t entry){	return (entry.val >> SRMMU_SWP_TYPE_SHIFT) & SRMMU_SWP_TYPE_MASK;}static unsigned long srmmu_swp_offset(swp_entry_t entry){	return (entry.val >> SRMMU_SWP_OFF_SHIFT) & SRMMU_SWP_OFF_MASK;}static swp_entry_t srmmu_swp_entry(unsigned long type, unsigned long offset){	return (swp_entry_t) {		  (type & SRMMU_SWP_TYPE_MASK) << SRMMU_SWP_TYPE_SHIFT		| (offset & SRMMU_SWP_OFF_MASK) << SRMMU_SWP_OFF_SHIFT };}/* * size: bytes to allocate in the nocache area. * align: bytes, number to align at. * Returns the virtual address of the allocated area. */static unsigned long __srmmu_get_nocache(int size, int align){	int offset;	if (size < SRMMU_NOCACHE_BITMAP_SHIFT) {		printk("Size 0x%x too small for nocache request\n", size);		size = SRMMU_NOCACHE_BITMAP_SHIFT;	}	if (size & (SRMMU_NOCACHE_BITMAP_SHIFT-1)) {		printk("Size 0x%x unaligned int nocache request\n", size);		size += SRMMU_NOCACHE_BITMAP_SHIFT-1;	}	BUG_ON(align > SRMMU_NOCACHE_ALIGN_MAX);	offset = bit_map_string_get(&srmmu_nocache_map,		       			size >> SRMMU_NOCACHE_BITMAP_SHIFT,					align >> SRMMU_NOCACHE_BITMAP_SHIFT);	if (offset == -1) {		printk("srmmu: out of nocache %d: %d/%d\n",		    size, (int) srmmu_nocache_size,		    srmmu_nocache_map.used << SRMMU_NOCACHE_BITMAP_SHIFT);		return 0;	}	return (SRMMU_NOCACHE_VADDR + (offset << SRMMU_NOCACHE_BITMAP_SHIFT));}unsigned inline long srmmu_get_nocache(int size, int align){	unsigned long tmp;	tmp = __srmmu_get_nocache(size, align);	if (tmp)		memset((void *)tmp, 0, size);	return tmp;}void srmmu_free_nocache(unsigned long vaddr, int size){	int offset;	if (vaddr < SRMMU_NOCACHE_VADDR) {		printk("Vaddr %lx is smaller than nocache base 0x%lx\n",		    vaddr, (unsigned long)SRMMU_NOCACHE_VADDR);		BUG();	}	if (vaddr+size > srmmu_nocache_end) {		printk("Vaddr %lx is bigger than nocache end 0x%lx\n",		    vaddr, srmmu_nocache_end);		BUG();	}	if (size & (size-1)) {		printk("Size 0x%x is not a power of 2\n", size);		BUG();	}	if (size < SRMMU_NOCACHE_BITMAP_SHIFT) {		printk("Size 0x%x is too small\n", size);		BUG();	}	if (vaddr & (size-1)) {		printk("Vaddr %lx is not aligned to size 0x%x\n", vaddr, size);		BUG();	}	offset = (vaddr - SRMMU_NOCACHE_VADDR) >> SRMMU_NOCACHE_BITMAP_SHIFT;	size = size >> SRMMU_NOCACHE_BITMAP_SHIFT;	bit_map_clear(&srmmu_nocache_map, offset, size);}void srmmu_early_allocate_ptable_skeleton(unsigned long start, unsigned long end);extern unsigned long probe_memory(void);	/* in fault.c *//* * Reserve nocache dynamically proportionally to the amount of * system RAM. -- Tomas Szepe <szepe@pinerecords.com>, June 2002 */void srmmu_nocache_calcsize(void){	unsigned long sysmemavail = probe_memory() / 1024;	int srmmu_nocache_npages;	srmmu_nocache_npages =		sysmemavail / SRMMU_NOCACHE_ALCRATIO / 1024 * 256; /* P3 XXX The 4x overuse: corroborated by /proc/meminfo. */	// if (srmmu_nocache_npages < 256) srmmu_nocache_npages = 256;	if (srmmu_nocache_npages < SRMMU_MIN_NOCACHE_PAGES)		srmmu_nocache_npages = SRMMU_MIN_NOCACHE_PAGES;	/* anything above 1280 blows up */	if (srmmu_nocache_npages > SRMMU_MAX_NOCACHE_PAGES)		srmmu_nocache_npages = SRMMU_MAX_NOCACHE_PAGES;	srmmu_nocache_size = srmmu_nocache_npages * PAGE_SIZE;	srmmu_nocache_end = SRMMU_NOCACHE_VADDR + srmmu_nocache_size;}void srmmu_nocache_init(void){	unsigned int bitmap_bits;	pgd_t *pgd;	pmd_t *pmd;	pte_t *pte;	unsigned long paddr, vaddr;	unsigned long pteval;	bitmap_bits = srmmu_nocache_size >> SRMMU_NOCACHE_BITMAP_SHIFT;	srmmu_nocache_pool = __alloc_bootmem(srmmu_nocache_size,		SRMMU_NOCACHE_ALIGN_MAX, 0UL);	memset(srmmu_nocache_pool, 0, srmmu_nocache_size);	srmmu_nocache_bitmap = __alloc_bootmem(bitmap_bits >> 3, SMP_CACHE_BYTES, 0UL);	bit_map_init(&srmmu_nocache_map, srmmu_nocache_bitmap, bitmap_bits);	srmmu_swapper_pg_dir = (pgd_t *)__srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE, SRMMU_PGD_TABLE_SIZE);	memset(__nocache_fix(srmmu_swapper_pg_dir), 0, SRMMU_PGD_TABLE_SIZE);	init_mm.pgd = srmmu_swapper_pg_dir;	srmmu_early_allocate_ptable_skeleton(SRMMU_NOCACHE_VADDR, srmmu_nocache_end);	paddr = __pa((unsigned long)srmmu_nocache_pool);	vaddr = SRMMU_NOCACHE_VADDR;	while (vaddr < srmmu_nocache_end) {		pgd = pgd_offset_k(vaddr);		pmd = srmmu_pmd_offset(__nocache_fix(pgd), vaddr);		pte = srmmu_pte_offset(__nocache_fix(pmd), vaddr);		pteval = ((paddr >> 4) | SRMMU_ET_PTE | SRMMU_PRIV);		if (srmmu_cache_pagetables)			pteval |= SRMMU_CACHE;

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