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	ldil		L%(TMPALIAS_MAP_START), %r28#ifdef CONFIG_64BIT#if (TMPALIAS_MAP_START >= 0x80000000)	depdi		0, 31,32, %r28		/* clear any sign extension */#endif	extrd,u		%r26, 56,32, %r26	/* convert phys addr to tlb insert format */	depd		%r25, 63,22, %r28	/* Form aliased virtual address 'to' */	depdi		0, 63,12, %r28		/* Clear any offset bits */#else	extrw,u		%r26, 24,25, %r26	/* convert phys addr to tlb insert format */	depw		%r25, 31,22, %r28	/* Form aliased virtual address 'to' */	depwi		0, 31,12, %r28		/* Clear any offset bits */#endif	/* Purge any old translation */	pdtlb		0(%r28)#ifdef CONFIG_64BIT	ldi		32, %r1			/* PAGE_SIZE/128 == 32 */	/* PREFETCH (Write) has not (yet) been proven to help here *//* #define	PREFETCHW_OP	ldd		256(%0), %r0 */1:	std		%r0, 0(%r28)	std		%r0, 8(%r28)	std		%r0, 16(%r28)	std		%r0, 24(%r28)	std		%r0, 32(%r28)	std		%r0, 40(%r28)	std		%r0, 48(%r28)	std		%r0, 56(%r28)	std		%r0, 64(%r28)	std		%r0, 72(%r28)	std		%r0, 80(%r28)	std		%r0, 88(%r28)	std		%r0, 96(%r28)	std		%r0, 104(%r28)	std		%r0, 112(%r28)	std		%r0, 120(%r28)	ADDIB>		-1, %r1, 1b	ldo		128(%r28), %r28#else	/* ! CONFIG_64BIT */	ldi		64, %r1			/* PAGE_SIZE/64 == 64 */1:	stw		%r0, 0(%r28)	stw		%r0, 4(%r28)	stw		%r0, 8(%r28)	stw		%r0, 12(%r28)	stw		%r0, 16(%r28)	stw		%r0, 20(%r28)	stw		%r0, 24(%r28)	stw		%r0, 28(%r28)	stw		%r0, 32(%r28)	stw		%r0, 36(%r28)	stw		%r0, 40(%r28)	stw		%r0, 44(%r28)	stw		%r0, 48(%r28)	stw		%r0, 52(%r28)	stw		%r0, 56(%r28)	stw		%r0, 60(%r28)	ADDIB>		-1, %r1, 1b	ldo		64(%r28), %r28#endif	/* CONFIG_64BIT */	bv		%r0(%r2)	nop	.exit	.procend	.export flush_kernel_dcache_pageflush_kernel_dcache_page:	.proc	.callinfo NO_CALLS	.entry	ldil		L%dcache_stride, %r1	ldw		R%dcache_stride(%r1), %r23#ifdef CONFIG_64BIT	depdi,z		1, 63-PAGE_SHIFT,1, %r25#else	depwi,z		1, 31-PAGE_SHIFT,1, %r25#endif	add		%r26, %r25, %r25	sub		%r25, %r23, %r251:      fdc,m		%r23(%r26)	fdc,m		%r23(%r26)	fdc,m		%r23(%r26)	fdc,m		%r23(%r26)	fdc,m		%r23(%r26)	fdc,m		%r23(%r26)	fdc,m		%r23(%r26)	fdc,m		%r23(%r26)	fdc,m		%r23(%r26)	fdc,m		%r23(%r26)	fdc,m		%r23(%r26)	fdc,m		%r23(%r26)	fdc,m		%r23(%r26)	fdc,m		%r23(%r26)	fdc,m		%r23(%r26)	CMPB<<		%r26, %r25,1b	fdc,m		%r23(%r26)	sync	bv		%r0(%r2)	nop	.exit	.procend		.export flush_user_dcache_pageflush_user_dcache_page:	.proc	.callinfo NO_CALLS	.entry	ldil		L%dcache_stride, %r1	ldw		R%dcache_stride(%r1), %r23#ifdef CONFIG_64BIT	depdi,z		1,63-PAGE_SHIFT,1, %r25#else	depwi,z		1,31-PAGE_SHIFT,1, %r25#endif	add		%r26, %r25, %r25	sub		%r25, %r23, %r251:      fdc,m		%r23(%sr3, %r26)	fdc,m		%r23(%sr3, %r26)	fdc,m		%r23(%sr3, %r26)	fdc,m		%r23(%sr3, %r26)	fdc,m		%r23(%sr3, %r26)	fdc,m		%r23(%sr3, %r26)	fdc,m		%r23(%sr3, %r26)	fdc,m		%r23(%sr3, %r26)	fdc,m		%r23(%sr3, %r26)	fdc,m		%r23(%sr3, %r26)	fdc,m		%r23(%sr3, %r26)	fdc,m		%r23(%sr3, %r26)	fdc,m		%r23(%sr3, %r26)	fdc,m		%r23(%sr3, %r26)	fdc,m		%r23(%sr3, %r26)	CMPB<<		%r26, %r25,1b	fdc,m		%r23(%sr3, %r26)	sync	bv		%r0(%r2)	nop	.exit	.procend	.export flush_user_icache_pageflush_user_icache_page:	.proc	.callinfo NO_CALLS	.entry	ldil		L%dcache_stride, %r1	ldw		R%dcache_stride(%r1), %r23#ifdef CONFIG_64BIT	depdi,z		1, 63-PAGE_SHIFT,1, %r25#else	depwi,z		1, 31-PAGE_SHIFT,1, %r25#endif	add		%r26, %r25, %r25	sub		%r25, %r23, %r251:      fic,m		%r23(%sr3, %r26)	fic,m		%r23(%sr3, %r26)	fic,m		%r23(%sr3, %r26)	fic,m		%r23(%sr3, %r26)	fic,m		%r23(%sr3, %r26)	fic,m		%r23(%sr3, %r26)	fic,m		%r23(%sr3, %r26)	fic,m		%r23(%sr3, %r26)	fic,m		%r23(%sr3, %r26)	fic,m		%r23(%sr3, %r26)	fic,m		%r23(%sr3, %r26)	fic,m		%r23(%sr3, %r26)	fic,m		%r23(%sr3, %r26)	fic,m		%r23(%sr3, %r26)	fic,m		%r23(%sr3, %r26)	CMPB<<		%r26, %r25,1b	fic,m		%r23(%sr3, %r26)	sync	bv		%r0(%r2)	nop	.exit	.procend	.export purge_kernel_dcache_pagepurge_kernel_dcache_page:	.proc	.callinfo NO_CALLS	.entry	ldil		L%dcache_stride, %r1	ldw		R%dcache_stride(%r1), %r23#ifdef CONFIG_64BIT	depdi,z		1, 63-PAGE_SHIFT,1, %r25#else	depwi,z		1, 31-PAGE_SHIFT,1, %r25#endif	add		%r26, %r25, %r25	sub		%r25, %r23, %r251:      pdc,m		%r23(%r26)	pdc,m		%r23(%r26)	pdc,m		%r23(%r26)	pdc,m		%r23(%r26)	pdc,m		%r23(%r26)	pdc,m		%r23(%r26)	pdc,m		%r23(%r26)	pdc,m		%r23(%r26)	pdc,m		%r23(%r26)	pdc,m		%r23(%r26)	pdc,m		%r23(%r26)	pdc,m		%r23(%r26)	pdc,m		%r23(%r26)	pdc,m		%r23(%r26)	pdc,m		%r23(%r26)	CMPB<<		%r26, %r25, 1b	pdc,m		%r23(%r26)	sync	bv		%r0(%r2)	nop	.exit	.procend#if 0	/* Currently not used, but it still is a possible alternate	 * solution.	 */	.export flush_alias_pageflush_alias_page:	.proc	.callinfo NO_CALLS	.entry	tophys_r1		%r26	ldil		L%(TMPALIAS_MAP_START), %r28#ifdef CONFIG_64BIT	extrd,u		%r26, 56,32, %r26	/* convert phys addr to tlb insert format */	depd		%r25, 63,22, %r28	/* Form aliased virtual address 'to' */	depdi		0, 63,12, %r28		/* Clear any offset bits */#else	extrw,u		%r26, 24,25, %r26	/* convert phys addr to tlb insert format */	depw		%r25, 31,22, %r28	/* Form aliased virtual address 'to' */	depwi		0, 31,12, %r28		/* Clear any offset bits */#endif	/* Purge any old translation */	pdtlb		0(%r28)	ldil		L%dcache_stride, %r1	ldw		R%dcache_stride(%r1), %r23#ifdef CONFIG_64BIT	depdi,z		1, 63-PAGE_SHIFT,1, %r29#else	depwi,z		1, 31-PAGE_SHIFT,1, %r29#endif	add		%r28, %r29, %r29	sub		%r29, %r23, %r291:      fdc,m		%r23(%r28)	fdc,m		%r23(%r28)	fdc,m		%r23(%r28)	fdc,m		%r23(%r28)	fdc,m		%r23(%r28)	fdc,m		%r23(%r28)	fdc,m		%r23(%r28)	fdc,m		%r23(%r28)	fdc,m		%r23(%r28)	fdc,m		%r23(%r28)	fdc,m		%r23(%r28)	fdc,m		%r23(%r28)	fdc,m		%r23(%r28)	fdc,m		%r23(%r28)	fdc,m		%r23(%r28)	CMPB<<		%r28, %r29, 1b	fdc,m		%r23(%r28)	sync	bv		%r0(%r2)	nop	.exit	.procend#endif	.export flush_user_dcache_range_asmflush_user_dcache_range_asm:	.proc	.callinfo NO_CALLS	.entry	ldil		L%dcache_stride, %r1	ldw		R%dcache_stride(%r1), %r23	ldo		-1(%r23), %r21	ANDCM		%r26, %r21, %r261:      CMPB<<,n	%r26, %r25, 1b	fdc,m		%r23(%sr3, %r26)	sync	bv		%r0(%r2)	nop	.exit	.procend	.export flush_kernel_dcache_range_asmflush_kernel_dcache_range_asm:	.proc	.callinfo NO_CALLS	.entry	ldil		L%dcache_stride, %r1	ldw		R%dcache_stride(%r1), %r23	ldo		-1(%r23), %r21	ANDCM		%r26, %r21, %r261:      CMPB<<,n	%r26, %r25,1b	fdc,m		%r23(%r26)	sync	syncdma	bv		%r0(%r2)	nop	.exit	.procend	.export flush_user_icache_range_asmflush_user_icache_range_asm:	.proc	.callinfo NO_CALLS	.entry	ldil		L%icache_stride, %r1	ldw		R%icache_stride(%r1), %r23	ldo		-1(%r23), %r21	ANDCM		%r26, %r21, %r261:      CMPB<<,n	%r26, %r25,1b	fic,m		%r23(%sr3, %r26)	sync	bv		%r0(%r2)	nop	.exit	.procend	.export flush_kernel_icache_pageflush_kernel_icache_page:	.proc	.callinfo NO_CALLS	.entry	ldil		L%icache_stride, %r1	ldw		R%icache_stride(%r1), %r23#ifdef CONFIG_64BIT	depdi,z		1, 63-PAGE_SHIFT,1, %r25#else	depwi,z		1, 31-PAGE_SHIFT,1, %r25#endif	add		%r26, %r25, %r25	sub		%r25, %r23, %r251:      fic,m		%r23(%sr4, %r26)	fic,m		%r23(%sr4, %r26)	fic,m		%r23(%sr4, %r26)	fic,m		%r23(%sr4, %r26)	fic,m		%r23(%sr4, %r26)	fic,m		%r23(%sr4, %r26)	fic,m		%r23(%sr4, %r26)	fic,m		%r23(%sr4, %r26)	fic,m		%r23(%sr4, %r26)	fic,m		%r23(%sr4, %r26)	fic,m		%r23(%sr4, %r26)	fic,m		%r23(%sr4, %r26)	fic,m		%r23(%sr4, %r26)	fic,m		%r23(%sr4, %r26)	fic,m		%r23(%sr4, %r26)	CMPB<<		%r26, %r25, 1b	fic,m		%r23(%sr4, %r26)	sync	bv		%r0(%r2)	nop	.exit	.procend	.export flush_kernel_icache_range_asmflush_kernel_icache_range_asm:	.proc	.callinfo NO_CALLS	.entry	ldil		L%icache_stride, %r1	ldw		R%icache_stride(%r1), %r23	ldo		-1(%r23), %r21	ANDCM		%r26, %r21, %r261:      CMPB<<,n	%r26, %r25, 1b	fic,m		%r23(%sr4, %r26)	sync	bv		%r0(%r2)	nop	.exit	.procend	/* align should cover use of rfi in disable_sr_hashing_asm and	 * srdis_done.	 */	.align	256	.export disable_sr_hashing_asm,codedisable_sr_hashing_asm:	.proc	.callinfo NO_CALLS	.entry	/*	 * Switch to real mode	 */	/* pcxt_ssm_bug */	rsm		PSW_SM_I, %r0	load32		PA(1f), %r1	nop	nop	nop	nop	nop	rsm		PSW_SM_Q, %r0		/* prep to load iia queue */	mtctl		%r0, %cr17		/* Clear IIASQ tail */	mtctl		%r0, %cr17		/* Clear IIASQ head */	mtctl		%r1, %cr18		/* IIAOQ head */	ldo		4(%r1), %r1	mtctl		%r1, %cr18		/* IIAOQ tail */	load32		REAL_MODE_PSW, %r1	mtctl		%r1, %ipsw	rfi	nop1:      cmpib,=,n	SRHASH_PCXST, %r26,srdis_pcxs	cmpib,=,n	SRHASH_PCXL, %r26,srdis_pcxl	cmpib,=,n	SRHASH_PA20, %r26,srdis_pa20	b,n		srdis_donesrdis_pcxs:	/* Disable Space Register Hashing for PCXS,PCXT,PCXT' */	.word		0x141c1a00		/* mfdiag %dr0, %r28 */	.word		0x141c1a00		/* must issue twice */	depwi		0,18,1, %r28		/* Clear DHE (dcache hash enable) */	depwi		0,20,1, %r28		/* Clear IHE (icache hash enable) */	.word		0x141c1600		/* mtdiag %r28, %dr0 */	.word		0x141c1600		/* must issue twice */	b,n		srdis_donesrdis_pcxl:	/* Disable Space Register Hashing for PCXL */	.word		0x141c0600		/* mfdiag %dr0, %r28 */	depwi           0,28,2, %r28		/* Clear DHASH_EN & IHASH_EN */	.word		0x141c0240		/* mtdiag %r28, %dr0 */	b,n		srdis_donesrdis_pa20:	/* Disable Space Register Hashing for PCXU,PCXU+,PCXW,PCXW+,PCXW2 */	.word		0x144008bc		/* mfdiag %dr2, %r28 */	depdi		0, 54,1, %r28		/* clear DIAG_SPHASH_ENAB (bit 54) */	.word		0x145c1840		/* mtdiag %r28, %dr2 */srdis_done:	/* Switch back to virtual mode */	rsm		PSW_SM_I, %r0		/* prep to load iia queue */	load32 	   	2f, %r1	nop	nop	nop	nop	nop	rsm		PSW_SM_Q, %r0		/* prep to load iia queue */	mtctl		%r0, %cr17		/* Clear IIASQ tail */	mtctl		%r0, %cr17		/* Clear IIASQ head */	mtctl		%r1, %cr18		/* IIAOQ head */	ldo		4(%r1), %r1	mtctl		%r1, %cr18		/* IIAOQ tail */	load32		KERNEL_PSW, %r1	mtctl		%r1, %ipsw	rfi	nop2:      bv		%r0(%r2)	nop	.exit	.procend	.end
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