pm.c

linux-2.6.15.6

	local_irq_enable();
	local_fiq_enable();

	omap_serial_wake_trigger(0);

	printk("PM: OMAP%x is re-starting from deep sleep...\n", system_rev);

	if (machine_is_omap_osk()) {
		/* Let LED1 (D9) blink again */
		tps65010_set_led(LED1, BLINK);
	}
}

#if defined(DEBUG) && defined(CONFIG_PROC_FS)
static int g_read_completed;

/*
 * Read system PM registers for debugging
 */
static int omap_pm_read_proc(
	char *page_buffer,
	char **my_first_byte,
	off_t virtual_start,
	int length,
	int *eof,
	void *data)
{
	int my_buffer_offset = 0;
	char * const my_base = page_buffer;

	ARM_SAVE(ARM_CKCTL);
	ARM_SAVE(ARM_IDLECT1);
	ARM_SAVE(ARM_IDLECT2);
	if (!(cpu_is_omap1510()))
		ARM_SAVE(ARM_IDLECT3);
	ARM_SAVE(ARM_EWUPCT);
	ARM_SAVE(ARM_RSTCT1);
	ARM_SAVE(ARM_RSTCT2);
	ARM_SAVE(ARM_SYSST);

	ULPD_SAVE(ULPD_IT_STATUS);
	ULPD_SAVE(ULPD_CLOCK_CTRL);
	ULPD_SAVE(ULPD_SOFT_REQ);
	ULPD_SAVE(ULPD_STATUS_REQ);
	ULPD_SAVE(ULPD_DPLL_CTRL);
	ULPD_SAVE(ULPD_POWER_CTRL);

	if (cpu_is_omap730()) {
		MPUI730_SAVE(MPUI_CTRL);
		MPUI730_SAVE(MPUI_DSP_STATUS);
		MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG);
		MPUI730_SAVE(MPUI_DSP_API_CONFIG);
		MPUI730_SAVE(EMIFF_SDRAM_CONFIG);
		MPUI730_SAVE(EMIFS_CONFIG);
	} else if (cpu_is_omap1510()) {
		MPUI1510_SAVE(MPUI_CTRL);
		MPUI1510_SAVE(MPUI_DSP_STATUS);
		MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
		MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
		MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
		MPUI1510_SAVE(EMIFS_CONFIG);
	} else if (cpu_is_omap16xx()) {
		MPUI1610_SAVE(MPUI_CTRL);
		MPUI1610_SAVE(MPUI_DSP_STATUS);
		MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
		MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
		MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
		MPUI1610_SAVE(EMIFS_CONFIG);
	}

	if (virtual_start == 0) {
		g_read_completed = 0;

		my_buffer_offset += sprintf(my_base + my_buffer_offset,
		   "ARM_CKCTL_REG:            0x%-8x     \n"
		   "ARM_IDLECT1_REG:          0x%-8x     \n"
		   "ARM_IDLECT2_REG:          0x%-8x     \n"
		   "ARM_IDLECT3_REG:	      0x%-8x     \n"
		   "ARM_EWUPCT_REG:           0x%-8x     \n"
		   "ARM_RSTCT1_REG:           0x%-8x     \n"
		   "ARM_RSTCT2_REG:           0x%-8x     \n"
		   "ARM_SYSST_REG:            0x%-8x     \n"
		   "ULPD_IT_STATUS_REG:       0x%-4x     \n"
		   "ULPD_CLOCK_CTRL_REG:      0x%-4x     \n"
		   "ULPD_SOFT_REQ_REG:        0x%-4x     \n"
		   "ULPD_DPLL_CTRL_REG:       0x%-4x     \n"
		   "ULPD_STATUS_REQ_REG:      0x%-4x     \n"
		   "ULPD_POWER_CTRL_REG:      0x%-4x     \n",
		   ARM_SHOW(ARM_CKCTL),
		   ARM_SHOW(ARM_IDLECT1),
		   ARM_SHOW(ARM_IDLECT2),
		   ARM_SHOW(ARM_IDLECT3),
		   ARM_SHOW(ARM_EWUPCT),
		   ARM_SHOW(ARM_RSTCT1),
		   ARM_SHOW(ARM_RSTCT2),
		   ARM_SHOW(ARM_SYSST),
		   ULPD_SHOW(ULPD_IT_STATUS),
		   ULPD_SHOW(ULPD_CLOCK_CTRL),
		   ULPD_SHOW(ULPD_SOFT_REQ),
		   ULPD_SHOW(ULPD_DPLL_CTRL),
		   ULPD_SHOW(ULPD_STATUS_REQ),
		   ULPD_SHOW(ULPD_POWER_CTRL));

		if (cpu_is_omap730()) {
			my_buffer_offset += sprintf(my_base + my_buffer_offset,
			   "MPUI730_CTRL_REG	     0x%-8x \n"
			   "MPUI730_DSP_STATUS_REG:      0x%-8x \n"
			   "MPUI730_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
	 "MPUI730_DSP_API_CONFIG_REG:  0x%-8x \n"
	 "MPUI730_SDRAM_CONFIG_REG:    0x%-8x \n"
	 "MPUI730_EMIFS_CONFIG_REG:    0x%-8x \n",
	 MPUI730_SHOW(MPUI_CTRL),
	 MPUI730_SHOW(MPUI_DSP_STATUS),
	 MPUI730_SHOW(MPUI_DSP_BOOT_CONFIG),
	 MPUI730_SHOW(MPUI_DSP_API_CONFIG),
	 MPUI730_SHOW(EMIFF_SDRAM_CONFIG),
	 MPUI730_SHOW(EMIFS_CONFIG));
		} else if (cpu_is_omap1510()) {
			my_buffer_offset += sprintf(my_base + my_buffer_offset,
			   "MPUI1510_CTRL_REG             0x%-8x \n"
			   "MPUI1510_DSP_STATUS_REG:      0x%-8x \n"
			   "MPUI1510_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
		   	   "MPUI1510_DSP_API_CONFIG_REG:  0x%-8x \n"
		   	   "MPUI1510_SDRAM_CONFIG_REG:    0x%-8x \n"
		   	   "MPUI1510_EMIFS_CONFIG_REG:    0x%-8x \n",
		   	   MPUI1510_SHOW(MPUI_CTRL),
		   	   MPUI1510_SHOW(MPUI_DSP_STATUS),
		   	   MPUI1510_SHOW(MPUI_DSP_BOOT_CONFIG),
		   	   MPUI1510_SHOW(MPUI_DSP_API_CONFIG),
		   	   MPUI1510_SHOW(EMIFF_SDRAM_CONFIG),
		   	   MPUI1510_SHOW(EMIFS_CONFIG));
		} else if (cpu_is_omap16xx()) {
			my_buffer_offset += sprintf(my_base + my_buffer_offset,
			   "MPUI1610_CTRL_REG             0x%-8x \n"
			   "MPUI1610_DSP_STATUS_REG:      0x%-8x \n"
			   "MPUI1610_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
		   	   "MPUI1610_DSP_API_CONFIG_REG:  0x%-8x \n"
		   	   "MPUI1610_SDRAM_CONFIG_REG:    0x%-8x \n"
		   	   "MPUI1610_EMIFS_CONFIG_REG:    0x%-8x \n",
		   	   MPUI1610_SHOW(MPUI_CTRL),
		   	   MPUI1610_SHOW(MPUI_DSP_STATUS),
		   	   MPUI1610_SHOW(MPUI_DSP_BOOT_CONFIG),
		   	   MPUI1610_SHOW(MPUI_DSP_API_CONFIG),
		   	   MPUI1610_SHOW(EMIFF_SDRAM_CONFIG),
		   	   MPUI1610_SHOW(EMIFS_CONFIG));
		}

		g_read_completed++;
	} else if (g_read_completed >= 1) {
		 *eof = 1;
		 return 0;
	}
	g_read_completed++;

	*my_first_byte = page_buffer;
	return  my_buffer_offset;
}

static void omap_pm_init_proc(void)
{
	struct proc_dir_entry *entry;

	entry = create_proc_read_entry("driver/omap_pm",
				       S_IWUSR | S_IRUGO, NULL,
	   omap_pm_read_proc, NULL);
}

#endif /* DEBUG && CONFIG_PROC_FS */

/*
 *	omap_pm_prepare - Do preliminary suspend work.
 *	@state:		suspend state we're entering.
 *
 */
//#include <asm/hardware.h>

static int omap_pm_prepare(suspend_state_t state)
{
	int error = 0;

	switch (state)
	{
	case PM_SUSPEND_STANDBY:
	case PM_SUSPEND_MEM:
		break;

	case PM_SUSPEND_DISK:
		return -ENOTSUPP;

	default:
		return -EINVAL;
	}

	return error;
}


/*
 *	omap_pm_enter - Actually enter a sleep state.
 *	@state:		State we're entering.
 *
 */

static int omap_pm_enter(suspend_state_t state)
{
	switch (state)
	{
	case PM_SUSPEND_STANDBY:
	case PM_SUSPEND_MEM:
		omap_pm_suspend();
		break;

	case PM_SUSPEND_DISK:
		return -ENOTSUPP;

	default:
		return -EINVAL;
	}

	return 0;
}


/**
 *	omap_pm_finish - Finish up suspend sequence.
 *	@state:		State we're coming out of.
 *
 *	This is called after we wake back up (or if entering the sleep state
 *	failed).
 */

static int omap_pm_finish(suspend_state_t state)
{
	return 0;
}


static irqreturn_t  omap_wakeup_interrupt(int  irq, void *  dev,
				     struct pt_regs *  regs)
{
	return IRQ_HANDLED;
}

static struct irqaction omap_wakeup_irq = {
	.name		= "peripheral wakeup",
	.flags		= SA_INTERRUPT,
	.handler	= omap_wakeup_interrupt
};



static struct pm_ops omap_pm_ops ={
	.pm_disk_mode = 0,
        .prepare        = omap_pm_prepare,
        .enter          = omap_pm_enter,
        .finish         = omap_pm_finish,
};

static int __init omap_pm_init(void)
{
	printk("Power Management for TI OMAP.\n");
	/*
	 * We copy the assembler sleep/wakeup routines to SRAM.
	 * These routines need to be in SRAM as that's the only
	 * memory the MPU can see when it wakes up.
	 */
	if (cpu_is_omap730()) {
		omap_sram_idle = omap_sram_push(omap730_idle_loop_suspend,
						omap730_idle_loop_suspend_sz);
		omap_sram_suspend = omap_sram_push(omap730_cpu_suspend,
	 omap730_cpu_suspend_sz);
	} else if (cpu_is_omap1510()) {
		omap_sram_idle = omap_sram_push(omap1510_idle_loop_suspend,
						omap1510_idle_loop_suspend_sz);
		omap_sram_suspend = omap_sram_push(omap1510_cpu_suspend,
						   omap1510_cpu_suspend_sz);
	} else if (cpu_is_omap16xx()) {
		omap_sram_idle = omap_sram_push(omap1610_idle_loop_suspend,
						omap1610_idle_loop_suspend_sz);
		omap_sram_suspend = omap_sram_push(omap1610_cpu_suspend,
						   omap1610_cpu_suspend_sz);
	}

	if (omap_sram_idle == NULL || omap_sram_suspend == NULL) {
		printk(KERN_ERR "PM not initialized: Missing SRAM support\n");
		return -ENODEV;
	}

	pm_idle = omap_pm_idle;

	if (cpu_is_omap730())
		setup_irq(INT_730_WAKE_UP_REQ, &omap_wakeup_irq);
	else if (cpu_is_omap16xx())
		setup_irq(INT_1610_WAKE_UP_REQ, &omap_wakeup_irq);

#if 0
	/* --- BEGIN BOARD-DEPENDENT CODE --- */
	/* Sleepx mask direction */
	omap_writew((omap_readw(0xfffb5008) & ~2), 0xfffb5008);
	/* Unmask sleepx signal */
	omap_writew((omap_readw(0xfffb5004) & ~2), 0xfffb5004);
	/* --- END BOARD-DEPENDENT CODE --- */
#endif

	/* Program new power ramp-up time
	 * (0 for most boards since we don't lower voltage when in deep sleep)
	 */
	omap_writew(ULPD_SETUP_ANALOG_CELL_3_VAL, ULPD_SETUP_ANALOG_CELL_3);

	/* Setup ULPD POWER_CTRL_REG - enter deep sleep whenever possible */
	omap_writew(ULPD_POWER_CTRL_REG_VAL, ULPD_POWER_CTRL);

	/* Configure IDLECT3 */
	if (cpu_is_omap730())
		omap_writel(OMAP730_IDLECT3_VAL, OMAP730_IDLECT3);
	else if (cpu_is_omap16xx())
		omap_writel(OMAP1610_IDLECT3_VAL, OMAP1610_IDLECT3);

	pm_set_ops(&omap_pm_ops);

#if defined(DEBUG) && defined(CONFIG_PROC_FS)
	omap_pm_init_proc();
#endif

	if (cpu_is_omap16xx()) {
		/* configure LOW_PWR pin */
		omap_cfg_reg(T20_1610_LOW_PWR);
	}

	return 0;
}
__initcall(omap_pm_init);