pci-sh7751.h

linux-2.6.15.6

  #define SH7751_PCIINT_TWDP         0x00000020  /* Tgt. Write Parity Error */
  #define SH7751_PCIINT_TRDP         0x00000010  /* Tgt. Read Parity Error Det. */
  #define SH7751_PCIINT_MTABT        0x00000008  /* Master-Tgt. Abort Error */
  #define SH7751_PCIINT_MMABT        0x00000004  /* Master-Master Abort Error */
  #define SH7751_PCIINT_MWPD         0x00000002  /* Master Write PERR Detect */
  #define SH7751_PCIINT_MRPD         0x00000002  /* Master Read PERR Detect */
#define SH7751_PCIINTM             0x118         /* PCI Interrupt Mask Register */
#define SH7751_PCIALR              0x11C         /* Error Address Register */
#define SH7751_PCICLR              0x120         /* Error Command/Data Register */
  #define SH7751_PCICLR_MPIO         0x80000000  /* Error Command/Data Register */
  #define SH7751_PCICLR_MDMA0        0x40000000  /* DMA0 Transfer Error */
  #define SH7751_PCICLR_MDMA1        0x20000000  /* DMA1 Transfer Error */
  #define SH7751_PCICLR_MDMA2        0x10000000  /* DMA2 Transfer Error */
  #define SH7751_PCICLR_MDMA3        0x08000000  /* DMA3 Transfer Error */
  #define SH7751_PCICLR_TGT          0x04000000  /* Target Transfer Error */
  #define SH7751_PCICLR_CMDL         0x0000000F  /* PCI Command at Error */
#define SH7751_PCIAINT             0x130         /* Arbiter Interrupt Register */
  #define SH7751_PCIAINT_MBKN        0x00002000  /* Master Broken Interrupt */
  #define SH7751_PCIAINT_TBTO        0x00001000  /* Target Bus Time Out */
  #define SH7751_PCIAINT_MBTO        0x00001000  /* Master Bus Time Out */
  #define SH7751_PCIAINT_TABT        0x00000008  /* Target Abort */
  #define SH7751_PCIAINT_MABT        0x00000004  /* Master Abort */
  #define SH7751_PCIAINT_RDPE        0x00000002  /* Read Data Parity Error */
  #define SH7751_PCIAINT_WDPE        0x00000002  /* Write Data Parity Error */
#define SH7751_PCIAINTM            0x134         /* Arbiter Int. Mask Register */
#define SH7751_PCIBMLR             0x138         /* Error Bus Master Register */
  #define SH7751_PCIBMLR_REQ4        0x00000010  /* REQ4 bus master at error */
  #define SH7751_PCIBMLR_REQ3        0x00000008  /* REQ3 bus master at error */
  #define SH7751_PCIBMLR_REQ2        0x00000004  /* REQ2 bus master at error */
  #define SH7751_PCIBMLR_REQ1        0x00000002  /* REQ1 bus master at error */
  #define SH7751_PCIBMLR_REQ0        0x00000001  /* REQ0 bus master at error */
#define SH7751_PCIDMABT            0x140         /* DMA Transfer Arb. Register */
  #define SH7751_PCIDMABT_RRBN       0x00000001  /* DMA Arbitor Round-Robin */
#define SH7751_PCIDPA0             0x180         /* DMA0 Transfer Addr. Register */
#define SH7751_PCIDLA0             0x184         /* DMA0 Local Addr. Register */
#define SH7751_PCIDTC0             0x188         /* DMA0 Transfer Cnt. Register */
#define SH7751_PCIDCR0             0x18C         /* DMA0 Control Register */
  #define SH7751_PCIDCR_ALGN         0x00000600  /* DMA Alignment Mode */
  #define SH7751_PCIDCR_MAST         0x00000100  /* DMA Termination Type */
  #define SH7751_PCIDCR_INTM         0x00000080  /* DMA Interrupt Done Mask*/
  #define SH7751_PCIDCR_INTS         0x00000040  /* DMA Interrupt Done Status */
  #define SH7751_PCIDCR_LHLD         0x00000020  /* Local Address Control */
  #define SH7751_PCIDCR_PHLD         0x00000010  /* PCI Address Control*/
  #define SH7751_PCIDCR_IOSEL        0x00000008  /* PCI Address Space Type */
  #define SH7751_PCIDCR_DIR          0x00000004  /* DMA Transfer Direction */
  #define SH7751_PCIDCR_STOP         0x00000002  /* Force DMA Stop */
  #define SH7751_PCIDCR_STRT         0x00000001  /* DMA Start */
#define SH7751_PCIDPA1             0x190         /* DMA1 Transfer Addr. Register */
#define SH7751_PCIDLA1             0x194         /* DMA1 Local Addr. Register */
#define SH7751_PCIDTC1             0x198         /* DMA1 Transfer Cnt. Register */
#define SH7751_PCIDCR1             0x19C         /* DMA1 Control Register */
#define SH7751_PCIDPA2             0x1A0         /* DMA2 Transfer Addr. Register */
#define SH7751_PCIDLA2             0x1A4         /* DMA2 Local Addr. Register */
#define SH7751_PCIDTC2             0x1A8         /* DMA2 Transfer Cnt. Register */
#define SH7751_PCIDCR2             0x1AC         /* DMA2 Control Register */
#define SH7751_PCIDPA3             0x1B0         /* DMA3 Transfer Addr. Register */
#define SH7751_PCIDLA3             0x1B4         /* DMA3 Local Addr. Register */
#define SH7751_PCIDTC3             0x1B8         /* DMA3 Transfer Cnt. Register */
#define SH7751_PCIDCR3             0x1BC         /* DMA3 Control Register */
#define SH7751_PCIPAR              0x1C0         /* PIO Address Register */
  #define SH7751_PCIPAR_CFGEN        0x80000000  /* Configuration Enable */
  #define SH7751_PCIPAR_BUSNO        0x00FF0000  /* Config. Bus Number */
  #define SH7751_PCIPAR_DEVNO        0x0000FF00  /* Config. Device Number */
  #define SH7751_PCIPAR_REGAD        0x000000FC  /* Register Address Number */
#define SH7751_PCIMBR              0x1C4         /* Memory Base Address Register */
  #define SH7751_PCIMBR_MASK         0xFF000000  /* Memory Space Mask */
  #define SH7751_PCIMBR_LOCK         0x00000001  /* Lock Memory Space */
#define SH7751_PCIIOBR             0x1C8         /* I/O Base Address Register */
  #define SH7751_PCIIOBR_MASK         0xFFFC0000 /* IO Space Mask */
  #define SH7751_PCIIOBR_LOCK         0x00000001 /* Lock IO Space */
#define SH7751_PCIPINT             0x1CC         /* Power Mgmnt Int. Register */
  #define SH7751_PCIPINT_D3           0x00000002 /* D3 Pwr Mgmt. Interrupt */
  #define SH7751_PCIPINT_D0           0x00000001 /* D0 Pwr Mgmt. Interrupt */  
#define SH7751_PCIPINTM            0x1D0         /* Power Mgmnt Mask Register */
#define SH7751_PCICLKR             0x1D4         /* Clock Ctrl. Register */
  #define SH7751_PCICLKR_PCSTP        0x00000002 /* PCI Clock Stop */
  #define SH7751_PCICLKR_BCSTP        0x00000002 /* BCLK Clock Stop */
/* For definitions of BCR, MCR see ... */
#define SH7751_PCIBCR1             0x1E0         /* Memory BCR1 Register */
#define SH7751_PCIBCR2             0x1E4         /* Memory BCR2 Register */
#define SH7751_PCIWCR1             0x1E8         /* Wait Control 1 Register */
#define SH7751_PCIWCR2             0x1EC         /* Wait Control 2 Register */
#define SH7751_PCIWCR3             0x1F0         /* Wait Control 3 Register */
#define SH7751_PCIMCR              0x1F4         /* Memory Control Register */
#define SH7751_PCIBCR3		   0x1f8	 /* Memory BCR3 Register */
#define SH7751_PCIPCTR             0x200         /* Port Control Register */
  #define SH7751_PCIPCTR_P2EN        0x000400000 /* Port 2 Enable */
  #define SH7751_PCIPCTR_P1EN        0x000200000 /* Port 1 Enable */
  #define SH7751_PCIPCTR_P0EN        0x000100000 /* Port 0 Enable */
  #define SH7751_PCIPCTR_P2UP        0x000000020 /* Port2 Pull Up Enable */
  #define SH7751_PCIPCTR_P2IO        0x000000010 /* Port2 Output Enable */
  #define SH7751_PCIPCTR_P1UP        0x000000008 /* Port1 Pull Up Enable */
  #define SH7751_PCIPCTR_P1IO        0x000000004 /* Port1 Output Enable */
  #define SH7751_PCIPCTR_P0UP        0x000000002 /* Port0 Pull Up Enable */
  #define SH7751_PCIPCTR_P0IO        0x000000001 /* Port0 Output Enable */
#define SH7751_PCIPDTR             0x204         /* Port Data Register */
  #define SH7751_PCIPDTR_PB5         0x000000020 /* Port 5 Enable */
  #define SH7751_PCIPDTR_PB4         0x000000010 /* Port 4 Enable */
  #define SH7751_PCIPDTR_PB3         0x000000008 /* Port 3 Enable */
  #define SH7751_PCIPDTR_PB2         0x000000004 /* Port 2 Enable */
  #define SH7751_PCIPDTR_PB1         0x000000002 /* Port 1 Enable */
  #define SH7751_PCIPDTR_PB0         0x000000001 /* Port 0 Enable */
#define SH7751_PCIPDR              0x220         /* Port IO Data Register */

/* Memory Control Registers */
#define SH7751_BCR1                0xFF800000    /* Memory BCR1 Register */
#define SH7751_BCR2                0xFF800004    /* Memory BCR2 Register */
#define SH7751_BCR3                0xFF800050    /* Memory BCR3 Register */
#define SH7751_BCR4                0xFE0A00F0    /* Memory BCR4 Register */
#define SH7751_WCR1                0xFF800008    /* Wait Control 1 Register */
#define SH7751_WCR2                0xFF80000C    /* Wait Control 2 Register */
#define SH7751_WCR3                0xFF800010    /* Wait Control 3 Register */
#define SH7751_MCR                 0xFF800014    /* Memory Control Register */

/* General Memory Config Addresses */
#define SH7751_CS0_BASE_ADDR       0x0
#define SH7751_MEM_REGION_SIZE     0x04000000
#define SH7751_CS1_BASE_ADDR       (SH7751_CS0_BASE_ADDR + SH7751_MEM_REGION_SIZE)
#define SH7751_CS2_BASE_ADDR       (SH7751_CS1_BASE_ADDR + SH7751_MEM_REGION_SIZE)
#define SH7751_CS3_BASE_ADDR       (SH7751_CS2_BASE_ADDR + SH7751_MEM_REGION_SIZE)
#define SH7751_CS4_BASE_ADDR       (SH7751_CS3_BASE_ADDR + SH7751_MEM_REGION_SIZE)
#define SH7751_CS5_BASE_ADDR       (SH7751_CS4_BASE_ADDR + SH7751_MEM_REGION_SIZE)
#define SH7751_CS6_BASE_ADDR       (SH7751_CS5_BASE_ADDR + SH7751_MEM_REGION_SIZE)

/* General PCI values */
#define SH7751_PCI_HOST_BRIDGE		0x6

/* Flags */
#define SH7751_PCIC_NO_RESET	0x0001

/* External functions defined per platform i.e. Big Sur, SE... (these could be routed 
 * through the machine vectors... */
extern int pcibios_init_platform(void);
extern int pcibios_map_platform_irq(u8 slot, u8 pin);

struct sh7751_pci_address_space {
	unsigned long base;
	unsigned long size;
};

struct sh7751_pci_address_map {
	struct sh7751_pci_address_space window0;
	struct sh7751_pci_address_space window1;
	unsigned long flags;
};

/* arch/sh/drivers/pci/pci-sh7751.c */
extern int sh7751_pcic_init(struct sh7751_pci_address_map *map);

#endif /* _PCI_SH7751_H_ */