sh7034.h

编译后直接运行的ＭＰ３播放器全部Ｃ语言源代码 一个包含FAT文件系统、系统引导 Boot、FLASH Driver等内容的

/***************************************************************************
 *             __________               __   ___.
 *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
 *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
 *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
 *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
 *                     \/            \/     \/    \/            \/
 * $Id: sh7034.h,v 1.2 2003/11/06 07:08:22 hohensoh Exp $
 *
 * Copyright (C) 2002 by Alan Korr
 *
 * All files in this archive are subject to the GNU General Public License.
 * See the file COPYING in the source tree root for full license agreement.
 *
 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
 * KIND, either express or implied.
 *
 ****************************************************************************/

#ifndef __SH7034_H__
#define __SH7034_H__

#define GBR           0x00000000

/* register address macros: */

#define SMR0_ADDR       0x05FFFEC0
#define BRR0_ADDR       0x05FFFEC1
#define SCR0_ADDR       0x05FFFEC2
#define TDR0_ADDR       0x05FFFEC3
#define SSR0_ADDR       0x05FFFEC4
#define RDR0_ADDR       0x05FFFEC5
#define SMR1_ADDR       0x05FFFEC8
#define BRR1_ADDR       0x05FFFEC9
#define SCR1_ADDR       0x05FFFECA
#define TDR1_ADDR       0x05FFFECB
#define SSR1_ADDR       0x05FFFECC
#define RDR1_ADDR       0x05FFFECD

#define ADDRAH_ADDR     0x05FFFEE0
#define ADDRAL_ADDR     0x05FFFEE1
#define ADDRBH_ADDR     0x05FFFEE2
#define ADDRBL_ADDR     0x05FFFEE3
#define ADDRCH_ADDR     0x05FFFEE4
#define ADDRCL_ADDR     0x05FFFEE5
#define ADDRDH_ADDR     0x05FFFEE6
#define ADDRDL_ADDR     0x05FFFEE7
#define ADCSR_ADDR      0x05FFFEE8
#define ADCR_ADDR       0x05FFFEE9

#define TSTR_ADDR       0x05FFFF00
#define TSNC_ADDR       0x05FFFF01
#define TMDR_ADDR       0x05FFFF02
#define TFCR_ADDR       0x05FFFF03
#define TCR0_ADDR       0x05FFFF04
#define TIOR0_ADDR      0x05FFFF05
#define TIER0_ADDR      0x05FFFF06
#define TSR0_ADDR       0x05FFFF07
#define TCNT0_ADDR      0x05FFFF08
#define GRA0_ADDR       0x05FFFF0A
#define GRB0_ADDR       0x05FFFF0C
#define TCR1_ADDR       0x05FFFF0E
#define TIOR1_ADDR      0x05FFFF0F
#define TIER1_ADDR      0x05FFFF10
#define TSR1_ADDR       0x05FFFF11
#define TCNT1_ADDR      0x05FFFF12
#define GRA1_ADDR       0x05FFFF14
#define GRB1_ADDR       0x05FFFF16
#define TCR2_ADDR       0x05FFFF18
#define TIOR2_ADDR      0x05FFFF19
#define TIER2_ADDR      0x05FFFF1A
#define TSR2_ADDR       0x05FFFF1B
#define TCNT2_ADDR      0x05FFFF1C
#define GRA2_ADDR       0x05FFFF1E
#define GRB2_ADDR       0x05FFFF20
#define TCR3_ADDR       0x05FFFF22
#define TIOR3_ADDR      0x05FFFF23
#define TIER3_ADDR      0x05FFFF24
#define TSR3_ADDR       0x05FFFF25
#define TCNT3_ADDR      0x05FFFF26
#define GRA3_ADDR       0x05FFFF28
#define GRB3_ADDR       0x05FFFF2A
#define BRA3_ADDR       0x05FFFF2C
#define BRB3_ADDR       0x05FFFF2E
#define TOCR_ADDR       0x05FFFF31
#define TCR4_ADDR       0x05FFFF32
#define TIOR4_ADDR      0x05FFFF33
#define TIER4_ADDR      0x05FFFF34
#define TSR4_ADDR       0x05FFFF35
#define TCNT4_ADDR      0x05FFFF36
#define GRA4_ADDR       0x05FFFF38
#define GRB4_ADDR       0x05FFFF3A
#define BRA4_ADDR       0x05FFFF3C
#define BRB4_ADDR       0x05FFFF3E

#define SAR0_ADDR       0x05FFFF40
#define DAR0_ADDR       0x05FFFF44
#define DMAOR_ADDR      0x05FFFF48
#define DTCR0_ADDR      0x05FFFF4A
#define CHCR0_ADDR      0x05FFFF4E
#define SAR1_ADDR       0x05FFFF50
#define DAR1_ADDR       0x05FFFF54
#define DTCR1_ADDR      0x05FFFF5A
#define CHCR1_ADDR      0x05FFFF5E
#define SAR2_ADDR       0x05FFFF60
#define DAR2_ADDR       0x05FFFF64
#define DTCR2_ADDR      0x05FFFF6A
#define CHCR2_ADDR      0x05FFFF6E
#define SAR3_ADDR       0x05FFFF70
#define DAR3_ADDR       0x05FFFF74
#define DTCR3_ADDR      0x05FFFF7A
#define CHCR3_ADDR      0x05FFFF7E

#define IPRA_ADDR       0x05FFFF84
#define IPRB_ADDR       0x05FFFF86
#define IPRC_ADDR       0x05FFFF88
#define IPRD_ADDR       0x05FFFF8A
#define IPRE_ADDR       0x05FFFF8C
#define ICR_ADDR        0x05FFFF8E

#define BARH_ADDR       0x05FFFF90
#define BARL_ADDR       0x05FFFF92
#define BAMRH_ADDR      0x05FFFF94
#define BAMRL_ADDR      0x05FFFF96
#define BBR_ADDR        0x05FFFF98

#define BCR_ADDR        0x05FFFFA0
#define WCR1_ADDR       0x05FFFFA2
#define WCR2_ADDR       0x05FFFFA4
#define WCR3_ADDR       0x05FFFFA6
#define DCR_ADDR        0x05FFFFA8
#define PCR_ADDR        0x05FFFFAA
#define RCR_ADDR        0x05FFFFAC
#define RTCSR_ADDR      0x05FFFFAE
#define RTCNT_ADDR      0x05FFFFB0
#define RTCOR_ADDR      0x05FFFFB2

#define TCSR_ADDR       0x05FFFFB8
#define TCNT_ADDR       0x05FFFFB9
#define RSTCSR_ADDR     0x05FFFFBB

#define SBYCR_ADDR      0x05FFFFBC
			
#define PADR_ADDR       0x05FFFFC0
#define PBDR_ADDR       0x05FFFFC2
#define PAIOR_ADDR      0x05FFFFC4
#define PBIOR_ADDR      0x05FFFFC6
#define PACR1_ADDR      0x05FFFFC8
#define PACR2_ADDR      0x05FFFFCA
#define PBCR1_ADDR      0x05FFFFCC
#define PBCR2_ADDR      0x05FFFFCE
#define PCDR_ADDR       0x05FFFFD0
			
#define CASCR_ADDR      0x05FFFFEE

/* byte halves of the ports */
#define PADRH_ADDR      0x05FFFFC0
#define PADRL_ADDR      0x05FFFFC1
#define PBDRH_ADDR      0x05FFFFC2
#define PBDRL_ADDR      0x05FFFFC3
#define PAIORH_ADDR     0x05FFFFC4
#define PAIORL_ADDR     0x05FFFFC5
#define PBIORH_ADDR     0x05FFFFC6
#define PBIORL_ADDR     0x05FFFFC7


/* Port B data register bits */
#define PBDR_LCD_SDA    0x0001 /* LCD serial data */
#define PBDR_LCD_SCK    0x0002 /* LCD serial clock */
#define PBDR_LCD_DC     0x0004 /* LCD data (1) / command (0) */
#define PBDR_LCD_CS1    0x0008 /* LCD chip select 1 (active low) */
#define PBDR_BTN_OFF    0x0010 /* Off button (active low) */
#define PBDR_LED_RED    0x0040 /* Red LED */
#define PBDR_BTN_ON     0x0100 /* On button (active low) */

/* A/D control/status register bits */
#define ADCSR_CH     0x07   /* Channel/group select */
#define ADCSR_CKS    0x08   /* Clock select */
#define ADCSR_SCAN   0x10   /* Scan mode */
#define ADCSR_ADST   0x20   /* A/D start */
#define ADCSR_ADIE   0x40   /* A/D interrupt enable */
#define ADCSR_ADF    0x80   /* A/D end flag */

/* A/D control register bits */
#define ADCR_TRGE    0x80   /* Trigger enable */

/* register macros for direct access: */

#define SMR0       (*((volatile unsigned char*)SMR0_ADDR))