📄 def21262.h
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#define SPIHI (BIT_12) // Bit 12 - SPI interrupt
#define GPTMR0I (BIT_13) // Bit 13 - General purpose IOP Timer = 0
#define SP1I (BIT_14) // Bit 14 - SPORT 1 Interrupt
#define SP3I (BIT_15) // Bit 15 - SPORT 3 Interrupt
#define SP5I (BIT_16) // Bit 16 - SPORT 5 Interrupt
#define CB7I (BIT_20) // Bit 20 - Circ. buffer 7 overflow
#define CB15I (BIT_21) // Bit 21 - Circ. buffer 15 overflow
#define TMZLI (BIT_22) // Bit 22 - Timer = 0 (low priority)
#define FIXI (BIT_23) // Bit 23 - Fixed-pt. overflow
#define FLTOI (BIT_24) // Bit 24 - fltg-pt. overflow
#define FLTUI (BIT_25) // Bit 25 - fltg-pt. underflow
#define FLTII (BIT_26) // Bit 26 - fltg-pt. invalid
#define EMULI (BIT_27) // Bit 27 - emulator interrupt
#define SFT0I (BIT_28) // Bit 28 - user software int 0
#define SFT1I (BIT_29) // Bit 29 - user software int 1
#define SFT2I (BIT_30) // Bit 30 - user software int 2
#define SFT3I (BIT_31) // Bit 31 - user software int 3
// LIRPTL register
#define SP0I (BIT_0) // Bit 0 - SPORT 0 interrupt
#define SP2I (BIT_1) // Bit 1 - SPORT 2 interrupt
#define SP4I (BIT_2) // Bit 2 - SPORT 4 interrupt
#define PPI (BIT_3) // Bit 3 - Parallel Port Interrupt
#define GPTMR1I (BIT_4) // Bit 4 - General Purpose IOP Timer 1 Interrupt
#define DAILI (BIT_6) // Bit 6 - DAI Low Priority Interrupt
#define GPTMR2I (BIT_8) // Bit 8 - General Purpose IOP Timer 2 Interrupt
#define SPILI (BIT_9) // Bit 9 - SPI Low Priority Interrupt
#define SP0IMSK (BIT_10) // Bit 10 - SPORT0 Interrupt Mask
#define SP2IMSK (BIT_11) // Bit 11 - SPORT2 Interrupt Mask
#define SP4IMSK (BIT_12) // Bit 12 - SPORT4 Interrupt Mask
#define PPIMSK (BIT_13) // Bit 13 - Parallel Port Interrupt Mask
#define GPTMR1IMSK (BIT_14) // Bit 14 - General Purpose IOP Timer 1 Interrupt Mask
#define DAILIMSK (BIT_16) // Bit 16 - DAI Low Priority Interrupt Mask
#define GPTMR2IMSK (BIT_18) // Bit 18 - General Purpose IOP Timer 2 Interrupt Mask
#define SPILIMSK (BIT_19) // Bit 19 - SPI Low Priority Interrupt Mask
#define SP0IMSKP (BIT_20) // Bit 20 - SPORT0 Interrupt Mask Pointer
#define SP2IMSKP (BIT_21) // Bit 21 - SPORT2 Interrupt Mask Pointer
#define SP4IMSKP (BIT_22) // Bit 22 - SPORT4 Interrupt Mask Pointer
#define PPIMSKP (BIT_23) // Bit 23 - Parallel Port Interrupt Mask Pointer
#define GPTMR1IMSKP (BIT_24) // Bit 24 - General Purpose IOP Timer 1 Interrupt Mask Pointer
#define DAILIMSKP (BIT_26) // Bit 26 - DAI Low Priority Interrupt Mask Pointer
#define GPTMR2IMSKP (BIT_28) // Bit 28 - General Purpose IOP Timer 2 Interrupt Mask Pointer
#define SPILIMSKP (BIT_29) // Bit 19 - SPI Low Priority Interrupt Mask Pointer
// FLAGS register
// FLAGS register - programmable I/O status macro definitions
#define FLG0 (BIT_0) // FLAG0 value (Low = '0', High = '1')
#define FLG1 (BIT_2) // FLAG1 value (Low = '0', High = '1')
#define FLG2 (BIT_4) // FLAG2 value (Low = '0', High = '1')
#define FLG3 (BIT_6) // FLAG3 value (Low = '0', High = '1')
#define FLG4 (BIT_8) // FLAG4 value (Low = '0', High = '1')
#define FLG5 (BIT_10) // FLAG5 value (Low = '0', High = '1')
#define FLG6 (BIT_12) // FLAG6 value (Low = '0', High = '1')
#define FLG7 (BIT_14) // FLAG7 value (Low = '0', High = '1')
#define FLG8 (BIT_16) // FLAG8 value (Low = '0', High = '1')
#define FLG9 (BIT_18) // FLAG9 value (Low = '0', High = '1')
#define FLG10 (BIT_20) // FLAG10 value (Low = '0', High = '1')
#define FLG11 (BIT_22) // FLAG11 value (Low = '0', High = '1')
#define FLG12 (BIT_24) // FLAG12 value (Low = '0', High = '1')
#define FLG13 (BIT_26) // FLAG13 value (Low = '0', High = '1')
#define FLG14 (BIT_28) // FLAG14 value (Low = '0', High = '1')
#define FLG15 (BIT_30) // FLAG15 value (Low = '0', High = '1')
// FLAGS register - programmable I/O control macro definitions
#define FLG0O (BIT_1) // FLAG0 control ('0' = flag input, '1' = flag output)
#define FLG1O (BIT_3) // FLAG1 control ('0' = flag input, '1' = flag output)
#define FLG2O (BIT_5) // FLAG2 control ('0' = flag input, '1' = flag output)
#define FLG3O (BIT_7) // FLAG3 control ('0' = flag input, '1' = flag output)
#define FLG4O (BIT_9) // FLAG4 control ('0' = flag input, '1' = flag output)
#define FLG5O (BIT_11) // FLAG5 control ('0' = flag input, '1' = flag output)
#define FLG6O (BIT_13) // FLAG6 control ('0' = flag input, '1' = flag output)
#define FLG7O (BIT_15) // FLAG7 control ('0' = flag input, '1' = flag output)
#define FLG8O (BIT_17) // FLAG8 control ('0' = flag input, '1' = flag output)
#define FLG9O (BIT_19) // FLAG9 control ('0' = flag input, '1' = flag output)
#define FLG10O (BIT_21) // FLAG10 control ('0' = flag input, '1' = flag output)
#define FLG11O (BIT_23) // FLAG11 control ('0' = flag input, '1' = flag output)
#define FLG12O (BIT_25) // FLAG12 control ('0' = flag input, '1' = flag output)
#define FLG13O (BIT_27) // FLAG13 control ('0' = flag input, '1' = flag output)
#define FLG14O (BIT_29) // FLAG14 control ('0' = flag input, '1' = flag output)
#define FLG15O (BIT_31) // FLAG15 control ('0' = flag input, '1' = flag output)
//========================================================================----
//
// IOP Control/Status Register Bit Definitions
//
//========================================================================----
// EEMUSTAT Register
#define STATPA (BIT_0) // (Read Only) Program Memory Breakpoint Status
#define STATDA0 (BIT_1) // (Read Only) Data Memory Breakpoint #0 Status
#define STATDA1 (BIT_2) // (Read Only) Data Memory Breakpoint #1 Status
#define STATIA0 (BIT_3) // (Read Only) Instruction Breakpoint #0 Status
#define STATIA1 (BIT_4) // (Read Only) Instruction Breakpoint #1 Status
#define STATIA2 (BIT_5) // (Read Only) Instruction Breakpoint #2 Status
#define STATIA3 (BIT_6) // (Read Only) Instruction Breakpoint #3 Status
#define STATIO0 (BIT_7) // (Read Only) I/O Memory Breakpoint #0 Status
#define STATEP (BIT_8) // (Read Only) Ext Memory Breakpoint Status
#define EEMUOUTIRQEN (BIT_9) // EEMUOUT Interrupt Enable
#define EEMUOUTRDY (BIT_10) // (Read Only) EEMUOUT Valid Data Status
#define EEMUOUTFULL (BIT_11) // (Read Only) EEMUOUT FIFO Full Status
#define EEMUINFULL (BIT_12) // (Read Only) EEMUIN FIFO Full Status
#define EEMUENS (BIT_13) // (Read Only) Enhanced Emulation Feature Enable Status
#define OSPIDENS (BIT_14) // (Read Only) Operating System Process ID Enable Status
#define EEMUINENS (BIT_15) // (Read Only) EEMUIN Interrupt Enable Status
#define STATIO1 (BIT_16) // (Read Only) I/O Memory Breakpoint #0 Status
// SYSCTL Register
#define SRST (BIT_0) // Soft Reset
#define IIVT (BIT_2) // Internal Interrupt Vector Table
#define IWT (BIT_3) // Instruction word transfer (0 = data, 1 = inst)
#define DCPR (BIT_7) // Select rotating access priority on DMA Channels
#define IMDW0 (BIT_9) // Internal memory block 0, extended data (48 bit)
#define IMDW1 (BIT_10) // Internal memory block 1, extended data (48 bit)
#define IRQ0EN (BIT_16) // Selects IRQ0 interrupt mode (set) or Flag 0 mode (clear)
#define IRQ1EN (BIT_17) // Selects IRQ1 interrupt mode (set) or Flag 1 mode (clear)
#define IRQ2EN (BIT_18) // Selects IRQ2 interrupt mode (set) or Flag 2 mode (clear)
#define TMREXPEN (BIT_19) // Selects timer-expired mode (set) or Flag 3 mode (clear)
#define PPFLGS (BIT_20) // Parallel Port is selected (clear) or ADDR and DATA are in FLAG mode (set)
// BRKCTL Register
#define PA1MODE (BIT_0|BIT_1) // PA1 Triggering Mode
#define DA1MODE (BIT_2|BIT_3) // DA1 Triggering Mode
#define DA2MODE (BIT_4|BIT_5) // DA2 Triggering Mode
#define IO1MODE (BIT_6|BIT_7) // IO1 Triggering Mode
#define EP1MODE (BIT_8|BIT_9) // EP1 Triggering Mode
#define NEGPA1 (BIT_10) // Negate Program Memory Address Breakpoint #1
#define NEGDA1 (BIT_11) // Negate Data Memory Address Breakpoint #1
#define NEGDA2 (BIT_12) // Negate Data Memory Address Breakpoint #2
#define NEGIA1 (BIT_13) // Negate Instruction Address Breakpoint #1
#define NEGIA2 (BIT_14) // Negate Instruction Address Breakpoint #2
#define NEGIA3 (BIT_15) // Negate Instruction Address Breakpoint #3
#define NEGIA4 (BIT_16) // Negate Instruction Address Breakpoint #4
#define NEGIO1 (BIT_17) // Negate I/0 Address Breakpoint #1
#define NEGEP1 (BIT_18) // Negate External Address Breakpoint #1
#define ENBPA (BIT_19) // Enable Program Memory Address Breakpoints
#define ENBDA (BIT_20) // Enable Data Memory Address Breakpoints
#define ENBIA (BIT_21) // Enable Instruction Address Breakpoints
#define ENBEP (BIT_23) // Enable External Address Breakpoints
#define ANDBKP (BIT_24) // AND the Composite Breakpoints
#define UMODE (BIT_25) // User Mode Breakpoint Functionality Enable
#define IODISABLE (BIT_26|BIT_27) // I/O Breakpoints Enable
//SPICTL register
#define TIMOD1 (BIT_0) // Use core writes for transfers
#define TIMOD2 (BIT_1) // Use DMA for transfers
#define SENDZ (BIT_2) // Send zero when SPITX buffer is empty (set) or send last word (clear)
#define GM (BIT_3) // Overwrite with incoming data when SPIRX is full (set) or discard new data (clear)
#define ISSEN (BIT_4) // enable Input Slave Select
#define DMISO (BIT_5) // Disable MISO pin for broadcasts
#define WL8 (0x00000000) // SPI Word Length = 8
#define WL16 (BIT_7) // SPI Word Length = 16
#define WL32 (BIT_8) // SPI Word Length = 32
#define MSBF (BIT_9) // Send data most significant byte first (set) or LSB first (clear)
#define CPHASE (BIT_10) // Selects transfer format of SPI clock and SPIDSx control
#define CLKPL (BIT_11) // Clock polarity - 0=act.high (low when idle), 1=act.low (high when idle)
#define MS (BIT_12) // Configure SPI as a Master (set) or Slave (clear)
#define OPD (BIT_13) // Open Drain Output enable
#define SPIEN (BIT_14) // SPI Port Enable
#define PACKEN (BIT_15) // Packing enable - 0 = no packing, 1 = 8-/16-bit packing
#define SGN (BIT_16) // Sign extend data
#define SMLS (BIT_17) // Seamless transfer enable
#define TXFLSH (BIT_18) // SPITX buffer flushed
#define RXFLSH (BIT_19) // SPITX buffer flushed
// SPISTAT register
#define SPIF (BIT_0) // SPI transmit or receive transfer complete
#define MME (BIT_1) // Multimaster error
#define TUNF (BIT_2) // TXSPI transmission error (underflow)
#define TXS (BIT_3) // TXSPI data buffer status
#define ROVF (BIT_4) // RXSPI reception error (overflow)
#define RXS (BIT_5) // RXSPI data buffer status
#define TXCOL (BIT_6) // TXSPI transmit collision
// SPIFLG register - only in effect when SPI port enabled in master mode. Otherwise
// FLG0-FLG3 controlled by FLAGS register
#define DS0EN (BIT_0) // Disable FLG0 & Enable SPI device-select-0 when CPHASE=0
#define DS1EN (BIT_1) // Disable FLG1 & Enable SPI device-select-1 when CPHASE=0
#define DS2EN (BIT_2) // Disable FLG2 & Enable SPI device-select-2 when CPHASE=0
#define DS3EN (BIT_3) // Disable FLG3 & Enable SPI device-select-3 when CPHASE=0
#define ISSS (BIT_7) // Reflects status of input slave select pin (dsp as slave)
#define SPIFLG0 (BIT_8) // If SPICTL:CPHASE=1, SW must manually control slave select signals
#define SPIFLG1 (BIT_9) // using these SPIFLGx bits. If CPHASE=0, device-selects are
#define SPIFLG2 (BIT_10)// automatically controlled by the SPI hardware, and these SPIDSx
#define SPIFLG3 (BIT_11)// bits are ignored.
// SPIDMAC Register
#define SPIDEN (BIT_0) // DMA Enable
#define SPIRCV (BIT_1) // DMA Read when set, Transmit when cleared.
#define INTEN (BIT_2) // Enable Interrupt when DMA transfer complete.
#define SPICHEN (BIT_4) // SPI DMA Chaining enable
#define FIFOFLSH (BIT_7) // clear the 4-deep DMA FIFO (seperate from SPIRX and SPITX buffers)
#define INTERR (BIT_8) // Enable interrupt on error
#define SPIOVF (BIT_9) // Receive Overflow error (data rx'd when rx buffer full)
#define SPIUNF (BIT_10) // Transmit Overflow error
#define SPIMME (BIT_11) // Multi-master error
#define SPIS0 (BIT_12) // SPI FIFO buffer status Bit 0
#define SPIS1 (BIT_13) // SPI FIFO buffer status Bit 1
#define SPIERRS (BIT_14) // DMA error status
#define SPIDMAS (BIT_15) // DMA transfer status
#define SPICHS (BIT_16) // DMA Chaining status
// SPMCTL01, SPMCTL23, SPMCTL45 registers
#define MCEA (BIT_0) // Multichannel Mode Enable for channel A
#define MFD0 (0x00000000) // no frame delay, multichannel FS pulse in same SCLK cycle as first data bit
#define MFD1 (BIT_1) // multichannel mode 1 cycle frame sync delay
#define MFD2 (BIT_2) // multichannel mode 2 cycle frame sync delay
#define MFD3 (BIT_1|BIT_2) // multichannel mode 3 cycle frame sync delay
#define MFD4 (BIT_3 // multichannel mode 4 cycle frame sync delay
#define MFD5 (BIT_1|BIT_3) // multichannel mode 5 cycle frame sync delay
#define MFD6 (BIT_2|BIT_3) // multichannel mode 6 cycle frame sync delay
#define MFD7 (BIT_1|BIT_2|BIT_3) // multichannel mode 7 cycle frame sync delay
#define MFD8 (BIT_4) // multichannel mode 8 cycle frame sync delay
#define MFD9 (BIT_1|BIT_4) // multichannel mode 9 cycle frame sync delay
#define MFD10 (BIT_2|BIT_4) // multichannel mode 10 cycle frame sync delay
#define MFD11 (BIT_1|BIT_2|BIT_4) // multichannel mode 11 cycle frame sync delay
#define MFD12 (BIT_3|BIT_4) // multichannel mode 12 cycle frame sync delay
#define MFD13 (BIT_1|BIT_3|BIT_4) // multichannel mode 13 cycle frame sync delay
#define MFD14 (BIT_2|BIT_3|BIT_4) // multichannel mode 14 cycle frame sync delay
#define MFD15 (BIT_1|BIT_2|BIT_3|BIT_4) // multichannel mode 15 cycle frame sync delay
#define NCH (0x00000FE0) // Number of MCM channels - 1
#define NCH0 (0x00000000) // 1 Channel
#define NCH1 (BIT_5) // 2 Channels
#define NCH2 (BIT_6) // 3 Channels
#define NCH3 (BIT_5|BIT_6) // 4 Channels
#define NCH4 (BIT_7) // 5 Channels
#define NCH5 (BIT_5|BIT_7) // 6 Channels
#define NCH6 (BIT_6|BIT_7) // 7 Channels
#define NCH7 (BIT_5|BIT_6|BIT_7) // 8 Channels
#define NCH8 (BIT_8) // 9 Channels
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